Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the
programmable logic (PL) through the AXI port.This AXI port helps
to establish the data path between the PS and PL. In-order to
establish to proper communication data path between PS and PL
the AXI port data path should be configured with the proper
Bus-width values
This patch series Adds afi config drivers support to handle the
PS-PL AXI port bus-width configurations.
Nava kishore Manne (5):
misc: doc: Add binding doc for the afi config driver
misc: zynq: Add afi config driver
firmware: xilinx: Add afi ioctl support
misc: doc: Add binding doc for the zynqmp afi config driver
misc: zynqmp: Add afi config driver
.../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 ++++++
.../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++
drivers/firmware/xilinx/zynqmp.c | 13 ++
drivers/misc/Kconfig | 22 +++
drivers/misc/Makefile | 2 +
drivers/misc/zynq-afi.c | 81 +++++++++++
drivers/misc/zynqmp-afi.c | 83 +++++++++++
include/linux/firmware/xlnx-zynqmp.h | 7 +
8 files changed, 391 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
create mode 100644 drivers/misc/zynq-afi.c
create mode 100644 drivers/misc/zynqmp-afi.c
--
2.18.0
This patch adds the binding document for the afi config
driver.
Signed-off-by: Nava kishore Manne <[email protected]>
---
.../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
new file mode 100644
index 000000000000..9c20a192d6a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,zynq-afi-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq AFI interface Manager.
+
+maintainers:
+ - Nava kishore Manne <[email protected]>
+
+description: |
+ The Zynq Processing System core provides access from PL masters to PS
+ internal peripherals, and memory through AXI FIFO interface(AFI)
+ interfaces.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,zynq-afi-fpga
+ reg:
+ maxItems: 1
+
+ xlnx,afi-buswidth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Size of the afi bus width.
+ 0 - 64-bit AXI data width.
+ 1 - 32-bit AXI data width.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - xlnx,afi-buswidth
+
+additionalProperties: false
+
+examples:
+ - |
+ afi0: afi@f8008000 {
+ compatible = "xlnx,zynq-afi-fpga";
+ reg = <0xf8008000 0x1000>;
+ xlnx,afi-buswidth = <1>;
+ };
+...
--
2.18.0
This patch adds afi ioctl to support dynamic PS-PL
bus width settings.
Signed-off-by: Nava kishore Manne <[email protected]>
---
drivers/firmware/xilinx/zynqmp.c | 13 +++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 7 +++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 7eb9958662dd..ada9eb9e26e3 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -713,6 +713,19 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
+/**
+ * zynqmp_pm_afi() - PM API for setting the PS-PL bus width
+ * @index: Register index value
+ * @value: value to be written into the register
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_afi(u32 index, u32 value)
+{
+ return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_AFI, index, value, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_afi);
+
/**
* zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
* @value: Status value to be written
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 71177b17eee5..792fb4f5d86f 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -113,6 +113,7 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ IOCTL_AFI = 18,
};
enum pm_query_id {
@@ -353,6 +354,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_afi(u32 index, u32 value);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -537,6 +539,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_afi(u32 index, u32 value)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.18.0
This patch adds zynq afi config driver. This is useful for
the configuration of the PS-PL interface on zynq platform.
Signed-off-by: Nava kishore Manne <[email protected]>
---
drivers/misc/Kconfig | 11 ++++++
drivers/misc/Makefile | 1 +
drivers/misc/zynq-afi.c | 81 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 93 insertions(+)
create mode 100644 drivers/misc/zynq-afi.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f532c59bb59b..877b43b3377d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -445,6 +445,17 @@ config HISI_HIKEY_USB
switching between the dual-role USB-C port and the USB-A host ports
using only one USB controller.
+config ZYNQ_AFI
+ tristate "Xilinx ZYNQ AFI support"
+ help
+ Zynq AFI driver support for writing to the AFI registers
+ for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
+ the PS to the programmable logic (PL) through the AXI port.
+ This AXI port helps to establish the data path between the
+ PS and PL.In-order to establish the proper communication path
+ between PS and PL, the AXI port data path should be configured
+ with the proper Bus-width values
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 99b6f15a3c70..e9b03843100f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/
obj-$(CONFIG_UACCE) += uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
+obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c
new file mode 100644
index 000000000000..04317d1bdb98
--- /dev/null
+++ b/drivers/misc/zynq-afi.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZYNQ AFI driver.
+ * Copyright (c) 2018-2021 Xilinx Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+/* Registers and special values for doing register-based operations */
+#define AFI_RDCHAN_CTRL_OFFSET 0x00
+#define AFI_WRCHAN_CTRL_OFFSET 0x14
+
+#define AFI_BUSWIDTH_MASK 0x01
+
+/**
+ * struct afi_fpga - AFI register description
+ * @membase: pointer to register struct
+ * @afi_width: AFI bus width to be written
+ */
+struct zynq_afi_fpga {
+ void __iomem *membase;
+ u32 afi_width;
+};
+
+static int zynq_afi_fpga_probe(struct platform_device *pdev)
+{
+ struct zynq_afi_fpga *afi_fpga;
+ struct resource *res;
+ u32 reg_val;
+ u32 val;
+
+ afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL);
+ if (!afi_fpga)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(afi_fpga->membase))
+ return PTR_ERR(afi_fpga->membase);
+
+ val = device_property_read_u32(&pdev->dev, "xlnx,afi-width",
+ &afi_fpga->afi_width);
+ if (val) {
+ dev_err(&pdev->dev, "failed to get the afi bus width\n");
+ return -EINVAL;
+ }
+
+ reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
+ reg_val &= ~AFI_BUSWIDTH_MASK;
+ writel(reg_val | afi_fpga->afi_width,
+ afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
+ reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
+ reg_val &= ~AFI_BUSWIDTH_MASK;
+ writel(reg_val | afi_fpga->afi_width,
+ afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
+
+ return 0;
+}
+
+static const struct of_device_id zynq_afi_fpga_ids[] = {
+ { .compatible = "xlnx,zynq-afi-fpga" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids);
+
+static struct platform_driver zynq_afi_fpga_driver = {
+ .driver = {
+ .name = "zynq-afi-fpga",
+ .of_match_table = zynq_afi_fpga_ids,
+ },
+ .probe = zynq_afi_fpga_probe,
+};
+module_platform_driver(zynq_afi_fpga_driver);
+
+MODULE_DESCRIPTION("ZYNQ FPGA AFI module");
+MODULE_AUTHOR("Nava kishore Manne <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
This patch adds the binding document for the zynqmp afi
config driver.
Signed-off-by: Nava kishore Manne <[email protected]>
---
.../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
new file mode 100644
index 000000000000..3ae22096b22a
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP AFI interface Manager.
+
+maintainers:
+ - Nava kishore Manne <[email protected]>
+
+description: |
+ The Zynq UltraScale+ MPSoC Processing System core provides access from PL
+ masters to PS internal peripherals, and memory through AXI FIFO interface(AFI)
+ interfaces.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,zynqmp-afi-fpga
+
+ config-afi:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Pairs of <regid value >
+ The possible values of regid and values are
+ regid - Regids of the register to be written possible values
+ 0- AFIFM0_RDCTRL
+ 1- AFIFM0_WRCTRL
+ 2- AFIFM1_RDCTRL
+ 3- AFIFM1_WRCTRL
+ 4- AFIFM2_RDCTRL
+ 5- AFIFM2_WRCTRL
+ 6- AFIFM3_RDCTRL
+ 7- AFIFM3_WRCTRL
+ 8- AFIFM4_RDCTRL
+ 9- AFIFM4_WRCTRL
+ 10- AFIFM5_RDCTRL
+ 11- AFIFM5_WRCTRL
+ 12- AFIFM6_RDCTRL
+ 13- AFIFM6_WRCTRL
+ 14- AFIFS
+ 15- AFIFS_SS2
+ value - Array of values to be written.
+ for FM0_RDCTRL(0) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM0_WRCTRL(1) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM1_RDCTRL(2) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM1_WRCTRL(3) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM2_RDCTRL(4) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM2_WRCTRL(5) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM3_RDCTRL(6) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM3_WRCTRL(7) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM4_RDCTRL(8) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM4_WRCTRL(9) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM5_RDCTRL(10) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM5_WRCTRL(11) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM6_RDCTRL(12) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for FM6_WRCTRL(13) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+ for AFI_FA(14)
+ dw_ss1_sel bits (11:10)
+ dw_ss0_sel bits (9:8)
+ 0x0 - 32-bit AXI data width
+ 0x1 - 64-bit AXI data width
+ 0x2 - 128-bit AXI data width
+ All other bits are 0 write ignored.
+
+ for AFI_FA(15) selects for ss2AXI data width valid values
+ 0x000 - 32-bit AXI data width
+ 0x100 - 64-bit AXI data width
+ 0x200 - 128-bit AXI data width
+ minItems: 1
+ maxItems: 15
+
+required:
+ - compatible
+ - config-afi
+
+additionalProperties: false
+
+examples:
+ - |
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ afi0: afi {
+ compatible = "xlnx,afi-fpga";
+ config-afi = <0 2>, <1 1>, <2 1>;
+ };
+ };
+ };
+
+...
--
2.18.0
This patch adds zynqmp afi config driver.This is useful for
the configuration of the PS-PL interface on Zynq US+ MPSoC
platform.
Signed-off-by: Nava kishore Manne <[email protected]>
---
drivers/misc/Kconfig | 11 ++++++
drivers/misc/Makefile | 1 +
drivers/misc/zynqmp-afi.c | 83 +++++++++++++++++++++++++++++++++++++++
3 files changed, 95 insertions(+)
create mode 100644 drivers/misc/zynqmp-afi.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 877b43b3377d..d1ea1eeb3ac1 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -456,6 +456,17 @@ config ZYNQ_AFI
between PS and PL, the AXI port data path should be configured
with the proper Bus-width values
+config ZYNQMP_AFI
+ tristate "Xilinx ZYNQMP AFI support"
+ help
+ ZynqMP AFI driver support for writing to the AFI registers for
+ configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
+ PS to the programmable logic (PL) through the AXI port. This AXI
+ port helps to establish the data path between the PS and PL.
+ In-order to establish the proper communication path between
+ PS and PL, the AXI port data path should be configured with
+ the proper Bus-width values
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e9b03843100f..54bd0edc511e 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
+obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c
new file mode 100644
index 000000000000..a318652576d2
--- /dev/null
+++ b/drivers/misc/zynqmp-afi.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx FPGA AFI bridge.
+ * Copyright (c) 2018-2021 Xilinx Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/**
+ * struct zynqmp_afi_fpga - AFI register description
+ * @value: value to be written to the register
+ * @regid: Register id for the register to be written
+ */
+struct zynqmp_afi_fpga {
+ u32 value;
+ u32 regid;
+};
+
+static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
+{
+ struct zynqmp_afi_fpga *zynqmp_afi_fpga;
+ struct device_node *np = pdev->dev.of_node;
+ int i, entries, ret;
+ u32 reg, val;
+
+ zynqmp_afi_fpga = devm_kzalloc(&pdev->dev,
+ sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
+ if (!zynqmp_afi_fpga)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, zynqmp_afi_fpga);
+
+ entries = of_property_count_u32_elems(np, "config-afi");
+ if (!entries || (entries % 2)) {
+ dev_err(&pdev->dev, "Invalid number of registers\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < entries / 2; i++) {
+ ret = of_property_read_u32_index(np, "config-afi", i * 2, ®);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to read register\n");
+ return -EINVAL;
+ }
+ ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
+ &val);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to read value\n");
+ return -EINVAL;
+ }
+ ret = zynqmp_pm_afi(reg, val);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "AFI register write error %d\n",
+ ret);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id zynqmp_afi_fpga_ids[] = {
+ { .compatible = "xlnx,zynqmp-afi-fpga" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, zynqmp_afi_fpga_ids);
+
+static struct platform_driver zynqmp_afi_fpga_driver = {
+ .driver = {
+ .name = "zynqmp-afi-fpga",
+ .of_match_table = zynqmp_afi_fpga_ids,
+ },
+ .probe = zynqmp_afi_fpga_probe,
+};
+module_platform_driver(zynqmp_afi_fpga_driver);
+
+MODULE_DESCRIPTION("ZYNQMP FPGA afi module");
+MODULE_AUTHOR("Nava kishore Manne <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
On Tue, Apr 20, 2021 at 01:41:50PM +0530, Nava kishore Manne wrote:
> This patch adds zynq afi config driver. This is useful for
> the configuration of the PS-PL interface on zynq platform.
What is "PS-PL"? Can you describe it better please?
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> drivers/misc/Kconfig | 11 ++++++
> drivers/misc/Makefile | 1 +
> drivers/misc/zynq-afi.c | 81 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 93 insertions(+)
> create mode 100644 drivers/misc/zynq-afi.c
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index f532c59bb59b..877b43b3377d 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> switching between the dual-role USB-C port and the USB-A host ports
> using only one USB controller.
>
> +config ZYNQ_AFI
> + tristate "Xilinx ZYNQ AFI support"
> + help
> + Zynq AFI driver support for writing to the AFI registers
> + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> + the PS to the programmable logic (PL) through the AXI port.
> + This AXI port helps to establish the data path between the
> + PS and PL.In-order to establish the proper communication path
> + between PS and PL, the AXI port data path should be configured
> + with the proper Bus-width values
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index 99b6f15a3c70..e9b03843100f 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/
> obj-$(CONFIG_UACCE) += uacce/
> obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c
> new file mode 100644
> index 000000000000..04317d1bdb98
> --- /dev/null
> +++ b/drivers/misc/zynq-afi.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx ZYNQ AFI driver.
> + * Copyright (c) 2018-2021 Xilinx Inc.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +/* Registers and special values for doing register-based operations */
> +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> +
> +#define AFI_BUSWIDTH_MASK 0x01
> +
> +/**
> + * struct afi_fpga - AFI register description
> + * @membase: pointer to register struct
> + * @afi_width: AFI bus width to be written
> + */
> +struct zynq_afi_fpga {
> + void __iomem *membase;
> + u32 afi_width;
> +};
> +
> +static int zynq_afi_fpga_probe(struct platform_device *pdev)
> +{
> + struct zynq_afi_fpga *afi_fpga;
> + struct resource *res;
> + u32 reg_val;
> + u32 val;
> +
> + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL);
> + if (!afi_fpga)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(afi_fpga->membase))
> + return PTR_ERR(afi_fpga->membase);
> +
> + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width",
> + &afi_fpga->afi_width);
> + if (val) {
> + dev_err(&pdev->dev, "failed to get the afi bus width\n");
> + return -EINVAL;
> + }
> +
> + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> + reg_val &= ~AFI_BUSWIDTH_MASK;
> + writel(reg_val | afi_fpga->afi_width,
> + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> + reg_val &= ~AFI_BUSWIDTH_MASK;
> + writel(reg_val | afi_fpga->afi_width,
> + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> +
> + return 0;
> +}
I do not understand, why is this driver needed at all? Why can't you do
the above from userspace?
All this does is write some values to the hardware at probe time, who
needs this?
thanks,
greg k-h
On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> This patch adds zynqmp afi config driver.This is useful for
> the configuration of the PS-PL interface on Zynq US+ MPSoC
> platform.
Again, please spell out what those terms mean, as I have no idea :(
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> drivers/misc/Kconfig | 11 ++++++
> drivers/misc/Makefile | 1 +
> drivers/misc/zynqmp-afi.c | 83 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 95 insertions(+)
> create mode 100644 drivers/misc/zynqmp-afi.c
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 877b43b3377d..d1ea1eeb3ac1 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -456,6 +456,17 @@ config ZYNQ_AFI
> between PS and PL, the AXI port data path should be configured
> with the proper Bus-width values
>
> +config ZYNQMP_AFI
> + tristate "Xilinx ZYNQMP AFI support"
> + help
> + ZynqMP AFI driver support for writing to the AFI registers for
> + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> + PS to the programmable logic (PL) through the AXI port. This AXI
> + port helps to establish the data path between the PS and PL.
> + In-order to establish the proper communication path between
> + PS and PL, the AXI port data path should be configured with
> + the proper Bus-width values
Please use tabs properly, you mix them above, checkpatch should have
caught that.
thanks,
greg k-h
On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> This patch adds zynqmp afi config driver.This is useful for
> the configuration of the PS-PL interface on Zynq US+ MPSoC
> platform.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> drivers/misc/Kconfig | 11 ++++++
> drivers/misc/Makefile | 1 +
> drivers/misc/zynqmp-afi.c | 83 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 95 insertions(+)
> create mode 100644 drivers/misc/zynqmp-afi.c
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 877b43b3377d..d1ea1eeb3ac1 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -456,6 +456,17 @@ config ZYNQ_AFI
> between PS and PL, the AXI port data path should be configured
> with the proper Bus-width values
>
> +config ZYNQMP_AFI
> + tristate "Xilinx ZYNQMP AFI support"
> + help
> + ZynqMP AFI driver support for writing to the AFI registers for
> + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> + PS to the programmable logic (PL) through the AXI port. This AXI
> + port helps to establish the data path between the PS and PL.
> + In-order to establish the proper communication path between
> + PS and PL, the AXI port data path should be configured with
> + the proper Bus-width values
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index e9b03843100f..54bd0edc511e 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
> obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
> diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c
> new file mode 100644
> index 000000000000..a318652576d2
> --- /dev/null
> +++ b/drivers/misc/zynqmp-afi.c
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx FPGA AFI bridge.
> + * Copyright (c) 2018-2021 Xilinx Inc.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +/**
> + * struct zynqmp_afi_fpga - AFI register description
> + * @value: value to be written to the register
> + * @regid: Register id for the register to be written
> + */
> +struct zynqmp_afi_fpga {
> + u32 value;
> + u32 regid;
> +};
> +
> +static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
> +{
> + struct zynqmp_afi_fpga *zynqmp_afi_fpga;
> + struct device_node *np = pdev->dev.of_node;
> + int i, entries, ret;
> + u32 reg, val;
> +
> + zynqmp_afi_fpga = devm_kzalloc(&pdev->dev,
> + sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
> + if (!zynqmp_afi_fpga)
> + return -ENOMEM;
> + platform_set_drvdata(pdev, zynqmp_afi_fpga);
> +
> + entries = of_property_count_u32_elems(np, "config-afi");
> + if (!entries || (entries % 2)) {
> + dev_err(&pdev->dev, "Invalid number of registers\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < entries / 2; i++) {
> + ret = of_property_read_u32_index(np, "config-afi", i * 2, ®);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to read register\n");
> + return -EINVAL;
> + }
> + ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
> + &val);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to read value\n");
> + return -EINVAL;
> + }
> + ret = zynqmp_pm_afi(reg, val);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "AFI register write error %d\n",
> + ret);
> + return ret;
> + }
> + }
> + return 0;
> +}
Again, why does this have to be in the kernel? All it does is make a
single call to the hardware based on some values read from the device
tree. Can't you do this from userspace?
thanks,
greg k-h
Hi Greg,
Please find my response inline.
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Tuesday, April 20, 2021 2:17 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> <[email protected]>; Dragan Cvetic <[email protected]>;
> [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> Dhamne <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; git <[email protected]>
> Subject: Re: [PATCH 2/5] misc: zynq: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:41:50PM +0530, Nava kishore Manne wrote:
> > This patch adds zynq afi config driver. This is useful for the
> > configuration of the PS-PL interface on zynq platform.
>
> What is "PS-PL"? Can you describe it better please?
>
PS-PL interface is nothing but the interface between processing system(PS) that contains arm cores and Programmable Logic(PL) i.e FPGA.
Will update the description in v2.
> >
> > Signed-off-by: Nava kishore Manne <[email protected]>
> > ---
> > drivers/misc/Kconfig | 11 ++++++
> > drivers/misc/Makefile | 1 +
> > drivers/misc/zynq-afi.c | 81
> > +++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 93 insertions(+)
> > create mode 100644 drivers/misc/zynq-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > f532c59bb59b..877b43b3377d 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> > switching between the dual-role USB-C port and the USB-A host
> ports
> > using only one USB controller.
> >
> > +config ZYNQ_AFI
> > + tristate "Xilinx ZYNQ AFI support"
> > + help
> > + Zynq AFI driver support for writing to the AFI registers
> > + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> > + the PS to the programmable logic (PL) through the AXI port.
> > + This AXI port helps to establish the data path between the
> > + PS and PL.In-order to establish the proper communication path
> > + between PS and PL, the AXI port data path should be configured
> > + with the proper Bus-width values
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > 99b6f15a3c70..e9b03843100f 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) +=
> habanalabs/
> > obj-$(CONFIG_UACCE) += uacce/
> > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new
> > file mode 100644 index 000000000000..04317d1bdb98
> > --- /dev/null
> > +++ b/drivers/misc/zynq-afi.c
> > @@ -0,0 +1,81 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx ZYNQ AFI driver.
> > + * Copyright (c) 2018-2021 Xilinx Inc.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +
> > +/* Registers and special values for doing register-based operations */
> > +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> > +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> > +
> > +#define AFI_BUSWIDTH_MASK 0x01
> > +
> > +/**
> > + * struct afi_fpga - AFI register description
> > + * @membase: pointer to register struct
> > + * @afi_width: AFI bus width to be written
> > + */
> > +struct zynq_afi_fpga {
> > + void __iomem *membase;
> > + u32 afi_width;
> > +};
> > +
> > +static int zynq_afi_fpga_probe(struct platform_device *pdev) {
> > + struct zynq_afi_fpga *afi_fpga;
> > + struct resource *res;
> > + u32 reg_val;
> > + u32 val;
> > +
> > + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga),
> GFP_KERNEL);
> > + if (!afi_fpga)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(afi_fpga->membase))
> > + return PTR_ERR(afi_fpga->membase);
> > +
> > + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width",
> > + &afi_fpga->afi_width);
> > + if (val) {
> > + dev_err(&pdev->dev, "failed to get the afi bus width\n");
> > + return -EINVAL;
> > + }
> > +
> > + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > + writel(reg_val | afi_fpga->afi_width,
> > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > + writel(reg_val | afi_fpga->afi_width,
> > + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> > +
> > + return 0;
> > +}
>
> I do not understand, why is this driver needed at all? Why can't you do the
> above from userspace?
>
> All this does is write some values to the hardware at probe time, who needs
> this?
This driver will be used by the overlay framework for configuring the interface after programming the FPGA and before probing the drivers that are present in the PL.
Regards,
Navakishore.
Hi Greg,
Please find my response inline.
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Tuesday, April 20, 2021 2:18 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> <[email protected]>; Dragan Cvetic <[email protected]>;
> [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> Dhamne <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; git <[email protected]>
> Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > This patch adds zynqmp afi config driver.This is useful for the
> > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
>
> Again, please spell out what those terms mean, as I have no idea :(
>
Will fix in v2
> >
> > Signed-off-by: Nava kishore Manne <[email protected]>
> > ---
> > drivers/misc/Kconfig | 11 ++++++
> > drivers/misc/Makefile | 1 +
> > drivers/misc/zynqmp-afi.c | 83
> > +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 95 insertions(+)
> > create mode 100644 drivers/misc/zynqmp-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 877b43b3377d..d1ea1eeb3ac1 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> > between PS and PL, the AXI port data path should be configured
> > with the proper Bus-width values
> >
> > +config ZYNQMP_AFI
> > + tristate "Xilinx ZYNQMP AFI support"
> > + help
> > + ZynqMP AFI driver support for writing to the AFI registers for
> > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > + PS to the programmable logic (PL) through the AXI port. This AXI
> > + port helps to establish the data path between the PS and PL.
> > + In-order to establish the proper communication path between
> > + PS and PL, the AXI port data path should be configured with
> > + the proper Bus-width values
>
> Please use tabs properly, you mix them above, checkpatch should have
> caught that.
>
Yes, Ideally check patch should report this issue but it's failed to report.
Will fix this issue in v2.
Regards,
Navakishore.
Hi Greg,
Please find my response inline.
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Tuesday, April 20, 2021 2:21 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> <[email protected]>; Dragan Cvetic <[email protected]>;
> [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> Dhamne <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; git <[email protected]>
> Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > This patch adds zynqmp afi config driver.This is useful for the
> > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> >
> > Signed-off-by: Nava kishore Manne <[email protected]>
> > ---
> > drivers/misc/Kconfig | 11 ++++++
> > drivers/misc/Makefile | 1 +
> > drivers/misc/zynqmp-afi.c | 83
> > +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 95 insertions(+)
> > create mode 100644 drivers/misc/zynqmp-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 877b43b3377d..d1ea1eeb3ac1 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> > between PS and PL, the AXI port data path should be configured
> > with the proper Bus-width values
> >
> > +config ZYNQMP_AFI
> > + tristate "Xilinx ZYNQMP AFI support"
> > + help
> > + ZynqMP AFI driver support for writing to the AFI registers for
> > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > + PS to the programmable logic (PL) through the AXI port. This AXI
> > + port helps to establish the data path between the PS and PL.
> > + In-order to establish the proper communication path between
> > + PS and PL, the AXI port data path should be configured with
> > + the proper Bus-width values
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > e9b03843100f..54bd0edc511e 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
> > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
> > diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c new
> > file mode 100644 index 000000000000..a318652576d2
> > --- /dev/null
> > +++ b/drivers/misc/zynqmp-afi.c
> > @@ -0,0 +1,83 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx FPGA AFI bridge.
> > + * Copyright (c) 2018-2021 Xilinx Inc.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/firmware/xlnx-zynqmp.h> #include <linux/io.h>
> > +#include <linux/module.h> #include <linux/of.h> #include
> > +<linux/platform_device.h> #include <linux/slab.h>
> > +
> > +/**
> > + * struct zynqmp_afi_fpga - AFI register description
> > + * @value: value to be written to the register
> > + * @regid: Register id for the register to be written
> > + */
> > +struct zynqmp_afi_fpga {
> > + u32 value;
> > + u32 regid;
> > +};
> > +
> > +static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
> > +{
> > + struct zynqmp_afi_fpga *zynqmp_afi_fpga;
> > + struct device_node *np = pdev->dev.of_node;
> > + int i, entries, ret;
> > + u32 reg, val;
> > +
> > + zynqmp_afi_fpga = devm_kzalloc(&pdev->dev,
> > + sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
> > + if (!zynqmp_afi_fpga)
> > + return -ENOMEM;
> > + platform_set_drvdata(pdev, zynqmp_afi_fpga);
> > +
> > + entries = of_property_count_u32_elems(np, "config-afi");
> > + if (!entries || (entries % 2)) {
> > + dev_err(&pdev->dev, "Invalid number of registers\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < entries / 2; i++) {
> > + ret = of_property_read_u32_index(np, "config-afi", i * 2,
> ®);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to read register\n");
> > + return -EINVAL;
> > + }
> > + ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
> > + &val);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to read value\n");
> > + return -EINVAL;
> > + }
> > + ret = zynqmp_pm_afi(reg, val);
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "AFI register write error %d\n",
> > + ret);
> > + return ret;
> > + }
> > + }
> > + return 0;
> > +}
>
> Again, why does this have to be in the kernel? All it does is make a
> single call to the hardware based on some values read from the device
> tree. Can't you do this from userspace?
>
For every PL design has its own PS-PL configuration.
This driver will be used by the overlay framework for configuring the interface after programming the FPGA and before probing the drivers that are present in the PL.
Regards,
Navakishore.
On Tue, 20 Apr 2021 13:41:52 +0530, Nava kishore Manne wrote:
> This patch adds the binding document for the zynqmp afi
> config driver.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++
> 1 file changed, 136 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.example.dt.yaml:0:0: /example-0/firmware/zynqmp-firmware: failed to match any schema with compatible: ['xlnx,zynqmp-firmware']
Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.example.dt.yaml:0:0: /example-0/firmware/zynqmp-firmware/afi: failed to match any schema with compatible: ['xlnx,afi-fpga']
See https://patchwork.ozlabs.org/patch/1468230
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Tue, Apr 20, 2021 at 01:41:52PM +0530, Nava kishore Manne wrote:
> This patch adds the binding document for the zynqmp afi
> config driver.
Bindings are for h/w blocks, not drivers.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++
> 1 file changed, 136 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
>
> diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
> new file mode 100644
> index 000000000000..3ae22096b22a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
> @@ -0,0 +1,136 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP AFI interface Manager.
> +
> +maintainers:
> + - Nava kishore Manne <[email protected]>
> +
> +description: |
> + The Zynq UltraScale+ MPSoC Processing System core provides access from PL
> + masters to PS internal peripherals, and memory through AXI FIFO interface(AFI)
> + interfaces.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - xlnx,zynqmp-afi-fpga
> +
> + config-afi:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: |
> + Pairs of <regid value >
> + The possible values of regid and values are
> + regid - Regids of the register to be written possible values
If we wanted sequences of register accesses in DT, we'd have a
generic mechanism to do so.
> + 0- AFIFM0_RDCTRL
> + 1- AFIFM0_WRCTRL
> + 2- AFIFM1_RDCTRL
> + 3- AFIFM1_WRCTRL
> + 4- AFIFM2_RDCTRL
> + 5- AFIFM2_WRCTRL
> + 6- AFIFM3_RDCTRL
> + 7- AFIFM3_WRCTRL
> + 8- AFIFM4_RDCTRL
> + 9- AFIFM4_WRCTRL
> + 10- AFIFM5_RDCTRL
> + 11- AFIFM5_WRCTRL
> + 12- AFIFM6_RDCTRL
> + 13- AFIFM6_WRCTRL
> + 14- AFIFS
> + 15- AFIFS_SS2
> + value - Array of values to be written.
> + for FM0_RDCTRL(0) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM0_WRCTRL(1) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM1_RDCTRL(2) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM1_WRCTRL(3) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM2_RDCTRL(4) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM2_WRCTRL(5) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM3_RDCTRL(6) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM3_WRCTRL(7) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM4_RDCTRL(8) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM4_WRCTRL(9) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM5_RDCTRL(10) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM5_WRCTRL(11) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM6_RDCTRL(12) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for FM6_WRCTRL(13) the valid values-fabric width
> + 2 - 32-bit
> + 1 - 64-bit
> + 0 - 128-bit
> + for AFI_FA(14)
> + dw_ss1_sel bits (11:10)
> + dw_ss0_sel bits (9:8)
> + 0x0 - 32-bit AXI data width
> + 0x1 - 64-bit AXI data width
> + 0x2 - 128-bit AXI data width
> + All other bits are 0 write ignored.
> +
> + for AFI_FA(15) selects for ss2AXI data width valid values
> + 0x000 - 32-bit AXI data width
> + 0x100 - 64-bit AXI data width
> + 0x200 - 128-bit AXI data width
> + minItems: 1
> + maxItems: 15
> +
> +required:
> + - compatible
> + - config-afi
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + firmware {
> + zynqmp_firmware: zynqmp-firmware {
> + compatible = "xlnx,zynqmp-firmware";
> + method = "smc";
> + afi0: afi {
> + compatible = "xlnx,afi-fpga";
> + config-afi = <0 2>, <1 1>, <2 1>;
> + };
> + };
> + };
> +
> +...
> --
> 2.18.0
>
On Tue, Apr 20, 2021 at 01:36:51PM +0000, Nava kishore Manne wrote:
> Hi Greg,
>
> Please find my response inline.
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Tuesday, April 20, 2021 2:17 PM
> > To: Nava kishore Manne <[email protected]>
> > Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> > <[email protected]>; Dragan Cvetic <[email protected]>;
> > [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> > <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> > Dhamne <[email protected]>; [email protected]; linux-arm-
> > [email protected]; [email protected];
> > [email protected]; git <[email protected]>
> > Subject: Re: [PATCH 2/5] misc: zynq: Add afi config driver
> >
> > On Tue, Apr 20, 2021 at 01:41:50PM +0530, Nava kishore Manne wrote:
> > > This patch adds zynq afi config driver. This is useful for the
> > > configuration of the PS-PL interface on zynq platform.
> >
> > What is "PS-PL"? Can you describe it better please?
> >
> PS-PL interface is nothing but the interface between processing system(PS) that contains arm cores and Programmable Logic(PL) i.e FPGA.
> Will update the description in v2.
>
> > >
> > > Signed-off-by: Nava kishore Manne <[email protected]>
> > > ---
> > > drivers/misc/Kconfig | 11 ++++++
> > > drivers/misc/Makefile | 1 +
> > > drivers/misc/zynq-afi.c | 81
> > > +++++++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 93 insertions(+)
> > > create mode 100644 drivers/misc/zynq-afi.c
> > >
> > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > > f532c59bb59b..877b43b3377d 100644
> > > --- a/drivers/misc/Kconfig
> > > +++ b/drivers/misc/Kconfig
> > > @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> > > switching between the dual-role USB-C port and the USB-A host
> > ports
> > > using only one USB controller.
> > >
> > > +config ZYNQ_AFI
> > > + tristate "Xilinx ZYNQ AFI support"
> > > + help
> > > + Zynq AFI driver support for writing to the AFI registers
> > > + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> > > + the PS to the programmable logic (PL) through the AXI port.
> > > + This AXI port helps to establish the data path between the
> > > + PS and PL.In-order to establish the proper communication path
> > > + between PS and PL, the AXI port data path should be configured
> > > + with the proper Bus-width values
> > > +
> > > source "drivers/misc/c2port/Kconfig"
> > > source "drivers/misc/eeprom/Kconfig"
> > > source "drivers/misc/cb710/Kconfig"
> > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > > 99b6f15a3c70..e9b03843100f 100644
> > > --- a/drivers/misc/Makefile
> > > +++ b/drivers/misc/Makefile
> > > @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) +=
> > habanalabs/
> > > obj-$(CONFIG_UACCE) += uacce/
> > > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > > +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > > diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new
> > > file mode 100644 index 000000000000..04317d1bdb98
> > > --- /dev/null
> > > +++ b/drivers/misc/zynq-afi.c
> > > @@ -0,0 +1,81 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Xilinx ZYNQ AFI driver.
> > > + * Copyright (c) 2018-2021 Xilinx Inc.
> > > + */
> > > +
> > > +#include <linux/err.h>
> > > +#include <linux/io.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/platform_device.h>
> > > +
> > > +/* Registers and special values for doing register-based operations */
> > > +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> > > +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> > > +
> > > +#define AFI_BUSWIDTH_MASK 0x01
> > > +
> > > +/**
> > > + * struct afi_fpga - AFI register description
> > > + * @membase: pointer to register struct
> > > + * @afi_width: AFI bus width to be written
> > > + */
> > > +struct zynq_afi_fpga {
> > > + void __iomem *membase;
> > > + u32 afi_width;
> > > +};
> > > +
> > > +static int zynq_afi_fpga_probe(struct platform_device *pdev) {
> > > + struct zynq_afi_fpga *afi_fpga;
> > > + struct resource *res;
> > > + u32 reg_val;
> > > + u32 val;
> > > +
> > > + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga),
> > GFP_KERNEL);
> > > + if (!afi_fpga)
> > > + return -ENOMEM;
> > > +
> > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res);
> > > + if (IS_ERR(afi_fpga->membase))
> > > + return PTR_ERR(afi_fpga->membase);
> > > +
> > > + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width",
> > > + &afi_fpga->afi_width);
> > > + if (val) {
> > > + dev_err(&pdev->dev, "failed to get the afi bus width\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > > + writel(reg_val | afi_fpga->afi_width,
> > > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > > + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> > > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > > + writel(reg_val | afi_fpga->afi_width,
> > > + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> > > +
> > > + return 0;
> > > +}
> >
> > I do not understand, why is this driver needed at all? Why can't you do the
> > above from userspace?
> >
> > All this does is write some values to the hardware at probe time, who needs
> > this?
>
> This driver will be used by the overlay framework for configuring the interface after programming the FPGA and before probing the drivers that are present in the PL.
What is a "overlay framework"? And why does the kernel have to do this?
Why can't you write these hardware values from userspace?
confused,
greg k-h
On Tue, Apr 20, 2021 at 01:47:17PM +0000, Nava kishore Manne wrote:
> Hi Greg,
>
> Please find my response inline.
>
> > -----Original Message-----
> > From: Greg KH <[email protected]>
> > Sent: Tuesday, April 20, 2021 2:21 PM
> > To: Nava kishore Manne <[email protected]>
> > Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> > <[email protected]>; Dragan Cvetic <[email protected]>;
> > [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> > <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> > Dhamne <[email protected]>; [email protected]; linux-arm-
> > [email protected]; [email protected];
> > [email protected]; git <[email protected]>
> > Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
> >
> > On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > > This patch adds zynqmp afi config driver.This is useful for the
> > > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> > >
> > > Signed-off-by: Nava kishore Manne <[email protected]>
> > > ---
> > > drivers/misc/Kconfig | 11 ++++++
> > > drivers/misc/Makefile | 1 +
> > > drivers/misc/zynqmp-afi.c | 83
> > > +++++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 95 insertions(+)
> > > create mode 100644 drivers/misc/zynqmp-afi.c
> > >
> > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > > 877b43b3377d..d1ea1eeb3ac1 100644
> > > --- a/drivers/misc/Kconfig
> > > +++ b/drivers/misc/Kconfig
> > > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> > > between PS and PL, the AXI port data path should be configured
> > > with the proper Bus-width values
> > >
> > > +config ZYNQMP_AFI
> > > + tristate "Xilinx ZYNQMP AFI support"
> > > + help
> > > + ZynqMP AFI driver support for writing to the AFI registers for
> > > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > > + PS to the programmable logic (PL) through the AXI port. This AXI
> > > + port helps to establish the data path between the PS and PL.
> > > + In-order to establish the proper communication path between
> > > + PS and PL, the AXI port data path should be configured with
> > > + the proper Bus-width values
> > > +
> > > source "drivers/misc/c2port/Kconfig"
> > > source "drivers/misc/eeprom/Kconfig"
> > > source "drivers/misc/cb710/Kconfig"
> > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > > e9b03843100f..54bd0edc511e 100644
> > > --- a/drivers/misc/Makefile
> > > +++ b/drivers/misc/Makefile
> > > @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
> > > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > > obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > > +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
> > > diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c new
> > > file mode 100644 index 000000000000..a318652576d2
> > > --- /dev/null
> > > +++ b/drivers/misc/zynqmp-afi.c
> > > @@ -0,0 +1,83 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Xilinx FPGA AFI bridge.
> > > + * Copyright (c) 2018-2021 Xilinx Inc.
> > > + */
> > > +
> > > +#include <linux/err.h>
> > > +#include <linux/firmware/xlnx-zynqmp.h> #include <linux/io.h>
> > > +#include <linux/module.h> #include <linux/of.h> #include
> > > +<linux/platform_device.h> #include <linux/slab.h>
> > > +
> > > +/**
> > > + * struct zynqmp_afi_fpga - AFI register description
> > > + * @value: value to be written to the register
> > > + * @regid: Register id for the register to be written
> > > + */
> > > +struct zynqmp_afi_fpga {
> > > + u32 value;
> > > + u32 regid;
> > > +};
> > > +
> > > +static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
> > > +{
> > > + struct zynqmp_afi_fpga *zynqmp_afi_fpga;
> > > + struct device_node *np = pdev->dev.of_node;
> > > + int i, entries, ret;
> > > + u32 reg, val;
> > > +
> > > + zynqmp_afi_fpga = devm_kzalloc(&pdev->dev,
> > > + sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
> > > + if (!zynqmp_afi_fpga)
> > > + return -ENOMEM;
> > > + platform_set_drvdata(pdev, zynqmp_afi_fpga);
> > > +
> > > + entries = of_property_count_u32_elems(np, "config-afi");
> > > + if (!entries || (entries % 2)) {
> > > + dev_err(&pdev->dev, "Invalid number of registers\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + for (i = 0; i < entries / 2; i++) {
> > > + ret = of_property_read_u32_index(np, "config-afi", i * 2,
> > ®);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "failed to read register\n");
> > > + return -EINVAL;
> > > + }
> > > + ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
> > > + &val);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "failed to read value\n");
> > > + return -EINVAL;
> > > + }
> > > + ret = zynqmp_pm_afi(reg, val);
> > > + if (ret < 0) {
> > > + dev_err(&pdev->dev, "AFI register write error %d\n",
> > > + ret);
> > > + return ret;
> > > + }
> > > + }
> > > + return 0;
> > > +}
> >
> > Again, why does this have to be in the kernel? All it does is make a
> > single call to the hardware based on some values read from the device
> > tree. Can't you do this from userspace?
> >
> For every PL design has its own PS-PL configuration.
What is a "PL design", and what is a "PS-PL configuration"? :)
> This driver will be used by the overlay framework for configuring the interface after programming the FPGA and before probing the drivers that are present in the PL.
Again, I have no idea what this means at all.
And again, why does this have to be done in the kernel? All you are
doing is sending some random values read in DT down to a hardware
device. What requires a kernel driver for this?
thanks,
greg k-h
On 4/20/21 1:11 AM, Nava kishore Manne wrote:
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 877b43b3377d..d1ea1eeb3ac1 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -456,6 +456,17 @@ config ZYNQ_AFI
> between PS and PL, the AXI port data path should be configured
> with the proper Bus-width values
>
> +config ZYNQMP_AFI
> + tristate "Xilinx ZYNQMP AFI support"
> + help
> + ZynqMP AFI driver support for writing to the AFI registers for
> + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> + PS to the programmable logic (PL) through the AXI port. This AXI
> + port helps to establish the data path between the PS and PL.
> + In-order to establish the proper communication path between
> + PS and PL, the AXI port data path should be configured with
> + the proper Bus-width values
> +
> source "drivers/misc/c2port/Kconfig"
> source "drivers/misc/eeprom/Kconfig"
> source "drivers/misc/cb710/Kconfig"
Hi,
from my notabot:
Please follow coding-style for Kconfig files:
from Documentation/process/coding-style.rst, section 10):
For all of the Kconfig* configuration files throughout the source tree,
the indentation is somewhat different. Lines under a ``config`` definition
are indented with one tab, while help text is indented an additional two
spaces.
thanks.
--
~Randy
On 4/20/21 1:11 AM, Nava kishore Manne wrote:
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index f532c59bb59b..877b43b3377d 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> switching between the dual-role USB-C port and the USB-A host ports
> using only one USB controller.
>
> +config ZYNQ_AFI
> + tristate "Xilinx ZYNQ AFI support"
> + help
> + Zynq AFI driver support for writing to the AFI registers
> + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> + the PS to the programmable logic (PL) through the AXI port.
> + This AXI port helps to establish the data path between the
> + PS and PL.In-order to establish the proper communication path
> + between PS and PL, the AXI port data path should be configured
> + with the proper Bus-width values
End that last sentence with a period ('.').
thanks.
--
~Randy
Hi Rob,
Please find my response inline.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Tuesday, April 20, 2021 7:29 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Tejas Patel <[email protected]>; Michal Simek
> <[email protected]>; Rajan Vaja <[email protected]>; linux-arm-
> [email protected]; Amit Sunil Dhamne <[email protected]>;
> Dragan Cvetic <[email protected]>; Derek Kiernan <[email protected]>;
> Jolly Shah <[email protected]>; git <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config
> driver
>
> On Tue, 20 Apr 2021 13:41:52 +0530, Nava kishore Manne wrote:
> > This patch adds the binding document for the zynqmp afi config driver.
> >
> > Signed-off-by: Nava kishore Manne <[email protected]>
> > ---
> > .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++
> > 1 file changed, 136 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
Thanks for the providing the update on the new features
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-
> fpga.example.dt.yaml:0:0: /example-0/firmware/zynqmp-firmware: failed to
> match any schema with compatible: ['xlnx,zynqmp-firmware']
> Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-
> fpga.example.dt.yaml:0:0: /example-0/firmware/zynqmp-firmware/afi:
> failed to match any schema with compatible: ['xlnx,afi-fpga']
>
> See https://patchwork.ozlabs.org/patch/1468230
>
> This check can fail if there are any dependencies. The base for a patch series
> is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Will fix in v2.
Regards,
Navakishore.
Hi Rob,
Thanks for the review.
Please find my response inline.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Tuesday, April 20, 2021 7:45 PM
> To: Nava kishore Manne <[email protected]>
> Cc: Michal Simek <[email protected]>; Derek Kiernan
> <[email protected]>; Dragan Cvetic <[email protected]>;
> [email protected]; [email protected]; Rajan Vaja
> <[email protected]>; Jolly Shah <[email protected]>; Tejas Patel
> <[email protected]>; Amit Sunil Dhamne <[email protected]>;
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]; git <[email protected]>
> Subject: Re: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config
> driver
>
> On Tue, Apr 20, 2021 at 01:41:52PM +0530, Nava kishore Manne wrote:
> > This patch adds the binding document for the zynqmp afi config driver.
>
> Bindings are for h/w blocks, not drivers.
>
This Binding are for h/w blocks (PS-PL bus width configurations)
For more info please refer the below links.
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf (Page No: 54)
https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e/v3_2/pg201-zynq-ultrascale-plus-processing-system.pdf (Page No: 42).
Please let me know if you need more info..
> >
> > Signed-off-by: Nava kishore Manne <[email protected]>
> > ---
> > .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++
> > 1 file changed, 136 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
> > b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
> > new file mode 100644
> > index 000000000000..3ae22096b22a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-
> fpga.yaml
> > @@ -0,0 +1,136 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx ZynqMP AFI interface Manager.
> > +
> > +maintainers:
> > + - Nava kishore Manne <[email protected]>
> > +
> > +description: |
> > + The Zynq UltraScale+ MPSoC Processing System core provides access
> > +from PL
> > + masters to PS internal peripherals, and memory through AXI FIFO
> > +interface(AFI)
> > + interfaces.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - xlnx,zynqmp-afi-fpga
> > +
> > + config-afi:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + description: |
> > + Pairs of <regid value >
> > + The possible values of regid and values are
> > + regid - Regids of the register to be written possible values
>
> If we wanted sequences of register accesses in DT, we'd have a generic
> mechanism to do so.
>
I will try to find a better way, will get back you on this
Regards,
Navakishore.
Hi Greg,
Please find my response inline.
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Tuesday, April 20, 2021 8:58 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> <[email protected]>; Dragan Cvetic <[email protected]>;
> [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> Dhamne <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; git <[email protected]>
> Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:47:17PM +0000, Nava kishore Manne wrote:
> > Hi Greg,
> >
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Tuesday, April 20, 2021 2:21 PM
> > > To: Nava kishore Manne <[email protected]>
> > > Cc: [email protected]; Michal Simek <[email protected]>; Derek
> > > Kiernan <[email protected]>; Dragan Cvetic <[email protected]>;
> > > [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> > > <[email protected]>; Tejas Patel <[email protected]>; Amit
> > > Sunil Dhamne <[email protected]>; [email protected];
> > > linux-arm- [email protected]; [email protected];
> > > [email protected]; git <[email protected]>
> > > Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
> > >
> > > On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > > > This patch adds zynqmp afi config driver.This is useful for the
> > > > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> > > >
> > > > Signed-off-by: Nava kishore Manne <[email protected]>
> > > > ---
> > > > drivers/misc/Kconfig | 11 ++++++
> > > > drivers/misc/Makefile | 1 +
> > > > drivers/misc/zynqmp-afi.c | 83
> > > > +++++++++++++++++++++++++++++++++++++++
> > > > 3 files changed, 95 insertions(+) create mode 100644
> > > > drivers/misc/zynqmp-afi.c
> > > >
> > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > > > 877b43b3377d..d1ea1eeb3ac1 100644
> > > > --- a/drivers/misc/Kconfig
> > > > +++ b/drivers/misc/Kconfig
> > > > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> > > > between PS and PL, the AXI port data path should be configured
> > > > with the proper Bus-width values
> > > >
> > > > +config ZYNQMP_AFI
> > > > + tristate "Xilinx ZYNQMP AFI support"
> > > > + help
> > > > + ZynqMP AFI driver support for writing to the AFI registers for
> > > > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > > > + PS to the programmable logic (PL) through the AXI port. This AXI
> > > > + port helps to establish the data path between the PS and PL.
> > > > + In-order to establish the proper communication path between
> > > > + PS and PL, the AXI port data path should be configured with
> > > > + the proper Bus-width values
> > > > +
> > > > source "drivers/misc/c2port/Kconfig"
> > > > source "drivers/misc/eeprom/Kconfig"
> > > > source "drivers/misc/cb710/Kconfig"
> > > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > > > e9b03843100f..54bd0edc511e 100644
> > > > --- a/drivers/misc/Makefile
> > > > +++ b/drivers/misc/Makefile
> > > > @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
> > > > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > > > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > > > obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > > > +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
> > > > diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c
> > > > new file mode 100644 index 000000000000..a318652576d2
> > > > --- /dev/null
> > > > +++ b/drivers/misc/zynqmp-afi.c
> > > > @@ -0,0 +1,83 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Xilinx FPGA AFI bridge.
> > > > + * Copyright (c) 2018-2021 Xilinx Inc.
> > > > + */
> > > > +
> > > > +#include <linux/err.h>
> > > > +#include <linux/firmware/xlnx-zynqmp.h> #include <linux/io.h>
> > > > +#include <linux/module.h> #include <linux/of.h> #include
> > > > +<linux/platform_device.h> #include <linux/slab.h>
> > > > +
> > > > +/**
> > > > + * struct zynqmp_afi_fpga - AFI register description
> > > > + * @value: value to be written to the register
> > > > + * @regid: Register id for the register to be written */ struct
> > > > +zynqmp_afi_fpga {
> > > > + u32 value;
> > > > + u32 regid;
> > > > +};
> > > > +
> > > > +static int zynqmp_afi_fpga_probe(struct platform_device *pdev) {
> > > > + struct zynqmp_afi_fpga *zynqmp_afi_fpga;
> > > > + struct device_node *np = pdev->dev.of_node;
> > > > + int i, entries, ret;
> > > > + u32 reg, val;
> > > > +
> > > > + zynqmp_afi_fpga = devm_kzalloc(&pdev->dev,
> > > > + sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
> > > > + if (!zynqmp_afi_fpga)
> > > > + return -ENOMEM;
> > > > + platform_set_drvdata(pdev, zynqmp_afi_fpga);
> > > > +
> > > > + entries = of_property_count_u32_elems(np, "config-afi");
> > > > + if (!entries || (entries % 2)) {
> > > > + dev_err(&pdev->dev, "Invalid number of registers\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + for (i = 0; i < entries / 2; i++) {
> > > > + ret = of_property_read_u32_index(np, "config-afi", i * 2,
> > > ®);
> > > > + if (ret) {
> > > > + dev_err(&pdev->dev, "failed to read register\n");
> > > > + return -EINVAL;
> > > > + }
> > > > + ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
> > > > + &val);
> > > > + if (ret) {
> > > > + dev_err(&pdev->dev, "failed to read value\n");
> > > > + return -EINVAL;
> > > > + }
> > > > + ret = zynqmp_pm_afi(reg, val);
> > > > + if (ret < 0) {
> > > > + dev_err(&pdev->dev, "AFI register write error
> %d\n",
> > > > + ret);
> > > > + return ret;
> > > > + }
> > > > + }
> > > > + return 0;
> > > > +}
> > >
> > > Again, why does this have to be in the kernel? All it does is make
> > > a single call to the hardware based on some values read from the
> > > device tree. Can't you do this from userspace?
> > >
> > For every PL design has its own PS-PL configuration.
>
> What is a "PL design", and what is a "PS-PL configuration"? :)
>
> > This driver will be used by the overlay framework for configuring the
> interface after programming the FPGA and before probing the drivers that
> are present in the PL.
>
> Again, I have no idea what this means at all.
>
> And again, why does this have to be done in the kernel? All you are doing is
> sending some random values read in DT down to a hardware
> device. What requires a kernel driver for this?
>
The ZynqMP based processing system (PS) that contains ARM cores and Xilinx programmable logic (PL/FPGA) in a single device. The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals.
This enables the designer to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors and can also access memory resources in the PS.
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf (Page No: 1085)
To Program/Re-Program the PL at runtime in Linux we have a an FPGA Manger Framework and this frame work uses DT-Overlays to programming the FPGA and probing the relevant PL drivers.
For more info please refer this link: https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/fpga/fpga-region.txt
Every Zynq/ZynqMP PL(FPGA) design has its own PS-PL configuration. So after programming the FPGA and before probing the relevant PL drivers these PS-PL configurations should be set.
Example DT-Overlay file to program the PL(FPGA) from Linux:
/dts-v1/;
/plugin/;
/ {
fragment@0 { /* fragment 0 contains Bitstream info */
target = <&fpga_full>;
overlay0: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
firmware-name = "Base_Zynq_MPSoC_wrapper.bit.bin";
resets = <&zynqmp_reset 116>;
};
};
fragment@1 { /* fragment 1 contains PS-PL configurations */
target = <&amba>;
overlay1: __overlay__ {
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0xa00>, <15 0x000>;
};
};
};
fragment@2 { /* Fragment 2 contains the relevant drivers for the IP's present in the FPGA design*/
target = <&amba>;
overlay2: __overlay__ {
axi_gpio_0: gpio@a0000000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0xa0000000 0x0 0x1000>;
};
};
} ;
};
In-order to support the PL(FPGA) programming and to configure the interface between PS and PL using FPGA Manager. This Driver is needed in the kernel space.
@Moritz Fischer: Can you please let us know your thoughts on this.
Regards,
Navakishore.
Hi Greg,
Please find my response inline.
> -----Original Message-----
> From: Greg KH <[email protected]>
> Sent: Tuesday, April 20, 2021 8:57 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Derek Kiernan
> <[email protected]>; Dragan Cvetic <[email protected]>;
> [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> <[email protected]>; Tejas Patel <[email protected]>; Amit Sunil
> Dhamne <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; git <[email protected]>
> Subject: Re: [PATCH 2/5] misc: zynq: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:36:51PM +0000, Nava kishore Manne wrote:
> > Hi Greg,
> >
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Greg KH <[email protected]>
> > > Sent: Tuesday, April 20, 2021 2:17 PM
> > > To: Nava kishore Manne <[email protected]>
> > > Cc: [email protected]; Michal Simek <[email protected]>; Derek
> > > Kiernan <[email protected]>; Dragan Cvetic <[email protected]>;
> > > [email protected]; Rajan Vaja <[email protected]>; Jolly Shah
> > > <[email protected]>; Tejas Patel <[email protected]>; Amit
> > > Sunil Dhamne <[email protected]>; [email protected];
> > > linux-arm- [email protected]; [email protected];
> > > [email protected]; git <[email protected]>
> > > Subject: Re: [PATCH 2/5] misc: zynq: Add afi config driver
> > >
> > > On Tue, Apr 20, 2021 at 01:41:50PM +0530, Nava kishore Manne wrote:
> > > > This patch adds zynq afi config driver. This is useful for the
> > > > configuration of the PS-PL interface on zynq platform.
> > >
> > > What is "PS-PL"? Can you describe it better please?
> > >
> > PS-PL interface is nothing but the interface between processing system(PS)
> that contains arm cores and Programmable Logic(PL) i.e FPGA.
> > Will update the description in v2.
> >
> > > >
> > > > Signed-off-by: Nava kishore Manne <[email protected]>
> > > > ---
> > > > drivers/misc/Kconfig | 11 ++++++
> > > > drivers/misc/Makefile | 1 +
> > > > drivers/misc/zynq-afi.c | 81
> > > > +++++++++++++++++++++++++++++++++++++++++
> > > > 3 files changed, 93 insertions(+) create mode 100644
> > > > drivers/misc/zynq-afi.c
> > > >
> > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > > > f532c59bb59b..877b43b3377d 100644
> > > > --- a/drivers/misc/Kconfig
> > > > +++ b/drivers/misc/Kconfig
> > > > @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> > > > switching between the dual-role USB-C port and the USB-A host
> > > ports
> > > > using only one USB controller.
> > > >
> > > > +config ZYNQ_AFI
> > > > + tristate "Xilinx ZYNQ AFI support"
> > > > + help
> > > > + Zynq AFI driver support for writing to the AFI registers
> > > > + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> > > > + the PS to the programmable logic (PL) through the AXI port.
> > > > + This AXI port helps to establish the data path between the
> > > > + PS and PL.In-order to establish the proper communication path
> > > > + between PS and PL, the AXI port data path should be configured
> > > > + with the proper Bus-width values
> > > > +
> > > > source "drivers/misc/c2port/Kconfig"
> > > > source "drivers/misc/eeprom/Kconfig"
> > > > source "drivers/misc/cb710/Kconfig"
> > > > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > > > 99b6f15a3c70..e9b03843100f 100644
> > > > --- a/drivers/misc/Makefile
> > > > +++ b/drivers/misc/Makefile
> > > > @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) +=
> > > habanalabs/
> > > > obj-$(CONFIG_UACCE) += uacce/
> > > > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > > > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > > > +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > > > diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new
> > > > file mode 100644 index 000000000000..04317d1bdb98
> > > > --- /dev/null
> > > > +++ b/drivers/misc/zynq-afi.c
> > > > @@ -0,0 +1,81 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Xilinx ZYNQ AFI driver.
> > > > + * Copyright (c) 2018-2021 Xilinx Inc.
> > > > + */
> > > > +
> > > > +#include <linux/err.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of.h>
> > > > +#include <linux/platform_device.h>
> > > > +
> > > > +/* Registers and special values for doing register-based operations */
> > > > +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> > > > +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> > > > +
> > > > +#define AFI_BUSWIDTH_MASK 0x01
> > > > +
> > > > +/**
> > > > + * struct afi_fpga - AFI register description
> > > > + * @membase: pointer to register struct
> > > > + * @afi_width: AFI bus width to be written
> > > > + */
> > > > +struct zynq_afi_fpga {
> > > > + void __iomem *membase;
> > > > + u32 afi_width;
> > > > +};
> > > > +
> > > > +static int zynq_afi_fpga_probe(struct platform_device *pdev) {
> > > > + struct zynq_afi_fpga *afi_fpga;
> > > > + struct resource *res;
> > > > + u32 reg_val;
> > > > + u32 val;
> > > > +
> > > > + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga),
> > > GFP_KERNEL);
> > > > + if (!afi_fpga)
> > > > + return -ENOMEM;
> > > > +
> > > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res);
> > > > + if (IS_ERR(afi_fpga->membase))
> > > > + return PTR_ERR(afi_fpga->membase);
> > > > +
> > > > + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width",
> > > > + &afi_fpga->afi_width);
> > > > + if (val) {
> > > > + dev_err(&pdev->dev, "failed to get the afi bus width\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > > > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > > > + writel(reg_val | afi_fpga->afi_width,
> > > > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > > > + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> > > > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > > > + writel(reg_val | afi_fpga->afi_width,
> > > > + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
> > > > +
> > > > + return 0;
> > > > +}
> > >
> > > I do not understand, why is this driver needed at all? Why can't
> > > you do the above from userspace?
> > >
> > > All this does is write some values to the hardware at probe time,
> > > who needs this?
> >
> > This driver will be used by the overlay framework for configuring the
> interface after programming the FPGA and before probing the drivers that
> are present in the PL.
>
> What is a "overlay framework"? And why does the kernel have to do this?
> Why can't you write these hardware values from userspace?
>
> confused,
>
The Zynq based processing system (PS) that contains ARM cores and Xilinx programmable logic (PL/FPGA) in a single device. The PS and PL can be tightly or loosely coupled using multiple interfaces and other signals.
This enables the designer to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors and can also access memory resources in the PS.
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf (Page No: 41)
To Program/Re-Program the PL at runtime in Linux we have a an FPGA Manger Framework and this frame work uses DT-Overlays to programming the FPGA and probing the relevant PL drivers.
For more info please refer this link: https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/fpga/fpga-region.txt
Every Zynq/ZynqMP PL(FPGA) design has its own PS-PL configuration. So after programming the FPGA and before probing the relevant PL drivers these PS-PL configurations should be set.
Example DT-Overlay file to program the PL(FPGA) from Linux:
/dts-v1/;
/plugin/;
/ {
fragment@0 { /* fragment 0 contains Bitstream info */
target = <&fpga_full>;
overlay0: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
firmware-name = "Base_Zynq_MPSoC_wrapper.bit.bin";
resets = <&zynqmp_reset 116>;
};
};
fragment@1 { /* fragment 1 contains PS-PL configurations */
target = <&amba>;
overlay1: __overlay__ {
afi0: afi@f8008000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xlnx,zynq-afi-fpga";
reg = <0xf8008000 0x24>;
xlnx,afi-width = <0x1>;
};
};
};
fragment@2 { /* Fragment 2 contains the relevant drivers for the IP's present in the FPGA design*/
target = <&amba>;
overlay2: __overlay__ {
axi_gpio_0: gpio@a0000000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0xa0000000 0x0 0x1000>;
};
};
} ;
};
In-order to support the PL(FPGA) programming and to configure the interface between PS and PL using FPGA Manager. This Driver is needed in the kernel space.
@Moritz Fischer: Can you please let us know your thoughts on this.
Regards,
Navakishore.