From: Daniel Silsby <[email protected]>
In preparation for 32-bit MIPS huge page support.
EVA,XPA are extended-addressing modes for 32-bit MIPS systems. Because
huge pages aren't currently supported in 32-bit MIPS, this doesn't take
any features away from EVA,XPA-enabled systems. However, the soon-to-
come 32-bit MIPS huge page support doesn't yet support them.
This also disables CPU_SUPPORTS_HUGEPAGES for the small number of 32-bit
MIPS CPUs from Alchemy/Netlogic that support a custom 36-bit extended
addressing. It's unknown if they even support huge pages in hardware.
Signed-off-by: Daniel Silsby <[email protected]>
Signed-off-by: Paul Cercueil <[email protected]>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d50fafd7bf3a..ff5f1314241e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2110,6 +2110,7 @@ config CPU_SUPPORTS_ADDRWINCFG
bool
config CPU_SUPPORTS_HUGEPAGES
bool
+ depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
config CPU_SUPPORTS_UNCACHED_ACCELERATED
bool
config MIPS_PGD_C0_CONTEXT
--
2.21.0.593.g511ec345e18
From: Daniel Silsby <[email protected]>
The Ingenic jz47xx SoC series of 32-bit MIPS CPUs support huge pages.
Signed-off-by: Daniel Silsby <[email protected]>
Signed-off-by: Paul Cercueil <[email protected]>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 47d50e37faa4..2a5d80c72c4e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -384,6 +384,7 @@ config MACH_INGENIC
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT_UART16550
+ select CPU_SUPPORTS_HUGEPAGES
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select PINCTRL
--
2.21.0.593.g511ec345e18
From: Daniel Silsby <[email protected]>
During an update long ago to conform to 4-level page code, PMD_ORDER was
changed from 0 to 1, despite the fact that a PMD table is not used at
all in a 32-bit MIPS build. PMD_ORDER does not seem to be used in these
builds. Now, it matches PUD_ORDER, a nonsense #define to give a build
failure with informative error.
The older commit that had redefined PMD_ORDER was
commit c6e8b587718c ("Update MIPS to use the 4-level pagetable code
thereby getting rid of the compacrapability headers.")
Signed-off-by: Daniel Silsby <[email protected]>
Signed-off-by: Paul Cercueil <[email protected]>
---
arch/mips/include/asm/pgtable-32.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index b0a78c9b6434..e600570789f4 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -83,7 +83,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
#define PUD_ORDER aieeee_attempt_to_allocate_pud
-#define PMD_ORDER 1
+#define PMD_ORDER aieeee_attempt_to_allocate_pmd
#define PTE_ORDER 0
#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
--
2.21.0.593.g511ec345e18
Hello,
Paul Cercueil wrote:
> From: Daniel Silsby <[email protected]>
>
> In preparation for 32-bit MIPS huge page support.
>
> EVA,XPA are extended-addressing modes for 32-bit MIPS systems. Because
> huge pages aren't currently supported in 32-bit MIPS, this doesn't take
> any features away from EVA,XPA-enabled systems. However, the soon-to-
> come 32-bit MIPS huge page support doesn't yet support them.
>
> This also disables CPU_SUPPORTS_HUGEPAGES for the small number of 32-bit
> MIPS CPUs from Alchemy/Netlogic that support a custom 36-bit extended
> addressing. It's unknown if they even support huge pages in hardware.
>
> Signed-off-by: Daniel Silsby <[email protected]>
> Signed-off-by: Paul Cercueil <[email protected]>
Series applied to mips-next.
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]
Hello,
Paul Cercueil wrote:
> From: Daniel Silsby <[email protected]>
>
> During an update long ago to conform to 4-level page code, PMD_ORDER was
> changed from 0 to 1, despite the fact that a PMD table is not used at
> all in a 32-bit MIPS build. PMD_ORDER does not seem to be used in these
> builds. Now, it matches PUD_ORDER, a nonsense #define to give a build
> failure with informative error.
>
> The older commit that had redefined PMD_ORDER was
> commit c6e8b587718c ("Update MIPS to use the 4-level pagetable code
> thereby getting rid of the compacrapability headers.")
>
> Signed-off-by: Daniel Silsby <[email protected]>
> Signed-off-by: Paul Cercueil <[email protected]>
Applied to mips-next.
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]
Hello,
Paul Cercueil wrote:
> From: Daniel Silsby <[email protected]>
>
> The Ingenic jz47xx SoC series of 32-bit MIPS CPUs support huge pages.
>
> Signed-off-by: Daniel Silsby <[email protected]>
> Signed-off-by: Paul Cercueil <[email protected]>
Applied to mips-next.
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email [email protected] to report it. ]