i.MX95 has a DDR pmu. This will add a compatible for it.
Signed-off-by: Xu Yang <[email protected]>
---
Changes in v2:
- no changes
Changes in v3:
- let imx95 compatilbe with imx93
---
Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
index 6c96a4204e5d..37e8b98f2cdc 100644
--- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
+++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
@@ -30,6 +30,9 @@ properties:
- items:
- const: fsl,imx8dxl-ddr-pmu
- const: fsl,imx8-ddr-pmu
+ - items:
+ - const: fsl,imx95-ddr-pmu
+ - const: fsl,imx93-ddr-pmu
reg:
maxItems: 1
--
2.34.1
i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports
read beat and write beat filter capabilities. This will add support for
i.MX95 and enhance the driver to support specific filter handling for it.
Usage:
For read beat:
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id=ID/
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id=ID/
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id=ID/
eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x00c/
For write beat:
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=ID/
eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00c/
Signed-off-by: Xu Yang <[email protected]>
---
Changes in v2:
- put soc spefific axi filter events to drvdata according
to franks suggestions.
- adjust pmcfg axi_id and axi_mask config
Changes in v3:
- no changes
---
drivers/perf/fsl_imx9_ddr_perf.c | 203 +++++++++++++++++++++++++------
1 file changed, 169 insertions(+), 34 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 9685645bfe04..fd118773508d 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -11,14 +11,24 @@
#include <linux/perf_event.h>
/* Performance monitor configuration */
-#define PMCFG1 0x00
-#define PMCFG1_RD_TRANS_FILT_EN BIT(31)
-#define PMCFG1_WR_TRANS_FILT_EN BIT(30)
-#define PMCFG1_RD_BT_FILT_EN BIT(29)
-#define PMCFG1_ID_MASK GENMASK(17, 0)
+#define PMCFG1 0x00
+#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
+#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
+#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
+#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
-#define PMCFG2 0x04
-#define PMCFG2_ID GENMASK(17, 0)
+#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31)
+#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30)
+
+#define PMCFG2 0x04
+#define MX93_PMCFG2_ID GENMASK(17, 0)
+
+#define PMCFG3 0x08
+#define PMCFG4 0x0C
+#define PMCFG5 0x10
+#define PMCFG6 0x14
+#define MX95_PMCFG_ID_MASK GENMASK(9, 0)
+#define MX95_PMCFG_ID GENMASK(25, 16)
/* Global control register affects all counters and takes priority over local control registers */
#define PMGC0 0x40
@@ -51,6 +61,7 @@ static DEFINE_IDA(ddr_ida);
struct imx_ddr_devtype_data {
const char *identifier; /* system PMU identifier for userspace */
+ struct attribute **attrs; /* AXI filter attributes */
};
struct ddr_pmu {
@@ -67,16 +78,6 @@ struct ddr_pmu {
int id;
};
-static const struct imx_ddr_devtype_data imx93_devtype_data = {
- .identifier = "imx93",
-};
-
-static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
- {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
-
static ssize_t ddr_perf_identifier_show(struct device *dev,
struct device_attribute *attr,
char *page)
@@ -178,7 +179,6 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
/* counter3 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64),
@@ -190,7 +190,6 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
/* counter4 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64),
@@ -202,7 +201,6 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
/* counter5 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64),
@@ -242,6 +240,28 @@ static const struct attribute_group ddr_perf_events_attr_group = {
.attrs = ddr_perf_events_attrs,
};
+static struct attribute *imx93_ddr_perf_events_attrs[] = {
+ /* counter2 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
+ /* counter3 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
+ /* counter4 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
+ NULL,
+};
+
+static struct attribute *imx95_ddr_perf_events_attrs[] = {
+ /* counter2 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73),
+ /* counter3 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73),
+ /* counter4 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73),
+ /* counter5 specific events */
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73),
+ NULL,
+};
+
PMU_FORMAT_ATTR(event, "config:0-7");
PMU_FORMAT_ATTR(counter, "config:8-15");
PMU_FORMAT_ATTR(axi_id, "config1:0-17");
@@ -268,6 +288,28 @@ static const struct attribute_group *attr_groups[] = {
NULL,
};
+static const struct imx_ddr_devtype_data imx93_devtype_data = {
+ .identifier = "imx93",
+ .attrs = imx93_ddr_perf_events_attrs,
+};
+
+static const struct imx_ddr_devtype_data imx95_devtype_data = {
+ .identifier = "imx95",
+ .attrs = imx95_ddr_perf_events_attrs,
+};
+
+static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
+ { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
+ { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
+
+static inline bool is_imx93(struct ddr_pmu *pmu)
+{
+ return pmu->devtype_data == &imx93_devtype_data;
+}
+
static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
{
if (counter == CYCLES_COUNTER) {
@@ -361,7 +403,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
}
}
-static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2)
+static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2)
{
u32 pmcfg1, pmcfg2;
int event, counter;
@@ -372,30 +414,80 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int
pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
if (counter == 2 && event == 73)
- pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
+ pmcfg1 |= MX93_PMCFG1_RD_TRANS_FILT_EN;
else if (counter == 2 && event != 73)
- pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
+ pmcfg1 &= ~MX93_PMCFG1_RD_TRANS_FILT_EN;
if (counter == 3 && event == 73)
- pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
+ pmcfg1 |= MX93_PMCFG1_WR_TRANS_FILT_EN;
else if (counter == 3 && event != 73)
- pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
+ pmcfg1 &= ~MX93_PMCFG1_WR_TRANS_FILT_EN;
if (counter == 4 && event == 73)
- pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
+ pmcfg1 |= MX93_PMCFG1_RD_BT_FILT_EN;
else if (counter == 4 && event != 73)
- pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
+ pmcfg1 &= ~MX93_PMCFG1_RD_BT_FILT_EN;
- pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
- pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2);
+ pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
+ pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, cfg2);
writel(pmcfg1, pmu->base + PMCFG1);
pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
- pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
- pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1);
+ pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
+ pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, cfg1);
writel(pmcfg2, pmu->base + PMCFG2);
}
+static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2)
+{
+ u32 pmcfg1, pmcfg, offset = 0;
+ int event, counter;
+
+ event = cfg & 0x000000FF;
+ counter = (cfg & 0x0000FF00) >> 8;
+
+ pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
+
+ if (counter == 2 && event == 73) {
+ pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN;
+ offset = PMCFG3;
+ } else if (counter == 2 && event != 73) {
+ pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN;
+ }
+
+ if (counter == 3 && event == 73) {
+ pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
+ offset = PMCFG4;
+ } else if (counter == 3 && event != 73) {
+ pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
+ }
+
+ if (counter == 4 && event == 73) {
+ pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
+ offset = PMCFG5;
+ } else if (counter == 4 && event != 73) {
+ pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
+ }
+
+ if (counter == 5 && event == 73) {
+ pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
+ offset = PMCFG6;
+ } else if (counter == 5 && event != 73) {
+ pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
+ }
+
+ writel(pmcfg1, pmu->base + PMCFG1);
+
+ if (offset) {
+ pmcfg = readl_relaxed(pmu->base + offset);
+ pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
+ FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
+ pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2) |
+ FIELD_PREP(MX95_PMCFG_ID, cfg1));
+ writel(pmcfg, pmu->base + offset);
+ }
+}
+
static void ddr_perf_event_update(struct perf_event *event)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@@ -476,12 +568,16 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
hwc->idx = counter;
hwc->state |= PERF_HES_STOPPED;
+ if (is_imx93(pmu))
+ /* read trans, write trans, read beat */
+ imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
+ else
+ /* write beat, read beat2, read beat1, read beat */
+ imx95_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
+
if (flags & PERF_EF_START)
ddr_perf_event_start(event, flags);
- /* read trans, write trans, read beat */
- ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
-
return 0;
}
@@ -596,6 +692,39 @@ static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
return 0;
}
+static int ddr_perf_add_events(struct ddr_pmu *pmu)
+{
+ int i, ret;
+ struct attribute **attrs = pmu->devtype_data->attrs;
+ struct device *pmu_dev = pmu->pmu.dev;
+
+ if (!attrs)
+ return 0;
+
+ for (i = 0; attrs[i]; i++) {
+ ret = sysfs_add_file_to_group(&pmu_dev->kobj, attrs[i], "events");
+ if (ret) {
+ dev_warn(pmu->dev, "i.MX9 DDR Perf add events failed (%d)\n", ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void ddr_perf_remove_events(struct ddr_pmu *pmu)
+{
+ int i;
+ struct attribute **attrs = pmu->devtype_data->attrs;
+ struct device *pmu_dev = pmu->pmu.dev;
+
+ if (!attrs)
+ return;
+
+ for (i = 0; attrs[i]; i++)
+ sysfs_remove_file_from_group(&pmu_dev->kobj, attrs[i], "events");
+}
+
static int ddr_perf_probe(struct platform_device *pdev)
{
struct ddr_pmu *pmu;
@@ -666,6 +795,10 @@ static int ddr_perf_probe(struct platform_device *pdev)
if (ret)
goto ddr_perf_err;
+ ret = ddr_perf_add_events(pmu);
+ if (ret)
+ dev_warn(&pdev->dev, "i.MX9 DDR Perf filter events are missing\n");
+
return 0;
ddr_perf_err:
@@ -683,6 +816,8 @@ static int ddr_perf_remove(struct platform_device *pdev)
{
struct ddr_pmu *pmu = platform_get_drvdata(pdev);
+ ddr_perf_remove_events(pmu);
+
cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
cpuhp_remove_multi_state(pmu->cpuhp_state);
--
2.34.1
The user can pass any counter ID to perf app. However, current pmu driver
doesn't judge the validity of the counter ID. This will add necessary
check for counter ID from user space. Besides, this pmu has 10 counters
except cycle counter which can be used to count reference events and
counter specific evnets. This will also add supports to auto allocate
counter if the user doesn't pass it the perf. Then, the usage of counter
will be optimized.
Signed-off-by: Xu Yang <[email protected]>
---
Changes in v2:
- limit counter ID from user to 0-10
- combine dynamic and static allocation of counter
Changes in v3:
- no changes
---
drivers/perf/fsl_imx9_ddr_perf.c | 69 +++++++++++++++++++++++++++++++-
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index fd118773508d..4bb80050920c 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -51,6 +51,7 @@
#define NUM_COUNTERS 11
#define CYCLES_COUNTER 0
+#define CYCLES_EVENT_ID 0
#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
@@ -235,6 +236,14 @@ static struct attribute *ddr_perf_events_attrs[] = {
NULL,
};
+static bool ddr_perf_is_specific_event(int event)
+{
+ if (event >= 64 && event <= 73)
+ return true;
+ else
+ return false;
+}
+
static const struct attribute_group ddr_perf_events_attr_group = {
.name = "events",
.attrs = ddr_perf_events_attrs,
@@ -507,6 +516,7 @@ static int ddr_perf_event_init(struct perf_event *event)
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
struct perf_event *sibling;
+ int event_id, counter;
if (event->attr.type != event->pmu->type)
return -ENOENT;
@@ -519,6 +529,18 @@ static int ddr_perf_event_init(struct perf_event *event)
return -EOPNOTSUPP;
}
+ counter = (event->attr.config & 0xFF00) >> 8;
+ if (counter > NUM_COUNTERS) {
+ dev_warn(pmu->dev, "Only counter 0-10 is supported!\n");
+ return -EINVAL;
+ }
+
+ event_id = event->attr.config & 0x00FF;
+ if (ddr_perf_is_specific_event(event_id) && counter == 0) {
+ dev_err(pmu->dev, "Need specify counter for counter specific events!\n");
+ return -EINVAL;
+ }
+
/*
* We must NOT create groups containing mixed PMUs, although software
* events are acceptable (for example to create a CCN group
@@ -552,6 +574,39 @@ static void ddr_perf_event_start(struct perf_event *event, int flags)
hwc->state = 0;
}
+static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter)
+{
+ int i;
+
+ if (event == CYCLES_EVENT_ID) {
+ /*
+ * Always map cycle event to counter 0.
+ * Cycles counter is dedicated for cycle event
+ * can't used for the other events.
+ */
+ if (pmu->events[CYCLES_COUNTER] == NULL)
+ return CYCLES_COUNTER;
+ } else if (counter != 0) {
+ /*
+ * 1. ddr_perf_event_init() will make sure counter
+ * is not 0 for counter specific events.
+ * 2. Allow specify counter for referene event too.
+ */
+ if (pmu->events[counter] == NULL)
+ return counter;
+ } else {
+ /*
+ * Counter may be 0 if user doesn't specify it.
+ * Auto allocate counter for referene event.
+ */
+ for (i = 1; i < NUM_COUNTERS; i++)
+ if (pmu->events[i] == NULL)
+ return i;
+ }
+
+ return -ENOENT;
+}
+
static int ddr_perf_event_add(struct perf_event *event, int flags)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@@ -559,9 +614,17 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
int cfg = event->attr.config;
int cfg1 = event->attr.config1;
int cfg2 = event->attr.config2;
- int counter;
+ int event_id, counter;
- counter = (cfg & 0x0000FF00) >> 8;
+ event_id = cfg & 0x00FF;
+ counter = (cfg & 0xFF00) >> 8;
+
+ /* check if counter is available */
+ counter = ddr_perf_alloc_counter(pmu, event_id, counter);
+ if (counter < 0) {
+ dev_dbg(pmu->dev, "There are not enough counters\n");
+ return -EOPNOTSUPP;
+ }
pmu->events[counter] = event;
pmu->active_events++;
@@ -597,9 +660,11 @@ static void ddr_perf_event_del(struct perf_event *event, int flags)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
+ int counter = hwc->idx;
ddr_perf_event_stop(event, PERF_EF_UPDATE);
+ pmu->events[counter] = NULL;
pmu->active_events--;
hwc->idx = -1;
}
--
2.34.1
Add JSON metrics for i.MX95 DDR Performane Monitor.
Signed-off-by: Xu Yang <[email protected]>
---
Changes in v2:
- fix wrong AXI_MASK setting
- remove unnecessary metrics
- add bandwidth_usage, camera_all, disp_all metrics
Changes in v3:
- no changes
---
.../arch/arm64/freescale/imx95/sys/ddrc.json | 9 +
.../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++
tools/perf/pmu-events/jevents.py | 1 +
3 files changed, 788 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
new file mode 100644
index 000000000000..4dc9d2968bdc
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
@@ -0,0 +1,9 @@
+[
+ {
+ "BriefDescription": "ddr cycles event",
+ "EventCode": "0x00",
+ "EventName": "imx95_ddr.cycles",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
new file mode 100644
index 000000000000..2bfcd4d574a8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
@@ -0,0 +1,778 @@
+[
+ {
+ "BriefDescription": "bandwidth usage for lpddr5 evk board",
+ "MetricName": "imx95_bandwidth_usage.lpddr5",
+ "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)",
+ "ScaleUnit": "1e2%",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all masters read from ddr",
+ "MetricName": "imx95_ddr_read.all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all masters write to ddr",
+ "MetricName": "imx95_ddr_write.all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all a55 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all a55 write to ddr (part1)",
+ "MetricName": "imx95_ddr_write.a55_all_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all a55 write to ddr (part2)",
+ "MetricName": "imx95_ddr_write.a55_all_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 0 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 0 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 1 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 1 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 2 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 2 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 3 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 3 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 4 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 4 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 5 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_5",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 5 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_5",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr",
+ "MetricName": "imx95_ddr_read.cortexa_dsu_l3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr",
+ "MetricName": "imx95_ddr_write.cortexa_dsu_l3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m33 read from ddr",
+ "MetricName": "imx95_ddr_read.m33",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m33 write to ddr",
+ "MetricName": "imx95_ddr_write.m33",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m7 read from ddr",
+ "MetricName": "imx95_ddr_read.m7",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m7 write to ddr",
+ "MetricName": "imx95_ddr_write.m7",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of sentinel read from ddr",
+ "MetricName": "imx95_ddr_read.sentinel",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of sentinel write to ddr",
+ "MetricName": "imx95_ddr_write.sentinel",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma1 read from ddr",
+ "MetricName": "imx95_ddr_read.edma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma1 write to ddr",
+ "MetricName": "imx95_ddr_write.edma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma2 read from ddr",
+ "MetricName": "imx95_ddr_read.edma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma2 write to ddr",
+ "MetricName": "imx95_ddr_write.edma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of netc read from ddr",
+ "MetricName": "imx95_ddr_read.netc",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of netc write to ddr",
+ "MetricName": "imx95_ddr_write.netc",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of npu read from ddr",
+ "MetricName": "imx95_ddr_read.npu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of npu write to ddr",
+ "MetricName": "imx95_ddr_write.npu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of gpu read from ddr",
+ "MetricName": "imx95_ddr_read.gpu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of gpu write to ddr",
+ "MetricName": "imx95_ddr_write.gpu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc1 read from ddr",
+ "MetricName": "imx95_ddr_read.usdhc1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc1 write to ddr",
+ "MetricName": "imx95_ddr_write.usdhc1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc2 read from ddr",
+ "MetricName": "imx95_ddr_read.usdhc2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc2 write to ddr",
+ "MetricName": "imx95_ddr_write.usdhc2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc3 read from ddr",
+ "MetricName": "imx95_ddr_read.usdhc3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc3 write to ddr",
+ "MetricName": "imx95_ddr_write.usdhc3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of xspi read from ddr",
+ "MetricName": "imx95_ddr_read.xspi",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of xspi write to ddr",
+ "MetricName": "imx95_ddr_write.xspi",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie1 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie1 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie2 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie2 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie3 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie3 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie4 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie4 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb1 read from ddr",
+ "MetricName": "imx95_ddr_read.usb1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb1 write to ddr",
+ "MetricName": "imx95_ddr_write.usb1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb2 read from ddr",
+ "MetricName": "imx95_ddr_read.usb2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb2 write to ddr",
+ "MetricName": "imx95_ddr_write.usb2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec primary bus read from ddr",
+ "MetricName": "imx95_ddr_read.vpu_primy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec primary bus write to ddr",
+ "MetricName": "imx95_ddr_write.vpu_primy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec secondary bus read from ddr",
+ "MetricName": "imx95_ddr_read.vpu_secndy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec secondary bus write to ddr",
+ "MetricName": "imx95_ddr_write.vpu_secndy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of jpeg decoder read from ddr",
+ "MetricName": "imx95_ddr_read.jpeg_dec",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of jpeg decoder write to ddr",
+ "MetricName": "imx95_ddr_write.jpeg_dec",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of jpeg encoder read from ddr",
+ "MetricName": "imx95_ddr_read.jpeg_dec",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of jpeg encoder write to ddr",
+ "MetricName": "imx95_ddr_write.jpeg_enc",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all vpu submodules read from ddr",
+ "MetricName": "imx95_ddr_read.vpu_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all vpu submodules write to ddr",
+ "MetricName": "imx95_ddr_write.vpu_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of cortex m0+ read from ddr",
+ "MetricName": "imx95_ddr_read.m0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of cortex m0+ write to ddr",
+ "MetricName": "imx95_ddr_write.m0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of camera edma read from ddr",
+ "MetricName": "imx95_ddr_read.camera_edma",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of camera edma write to ddr",
+ "MetricName": "imx95_ddr_write.camera_edma",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi rd read from ddr",
+ "MetricName": "imx95_ddr_read.isi_rd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi rd write to ddr",
+ "MetricName": "imx95_ddr_write.isi_rd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr y read from ddr",
+ "MetricName": "imx95_ddr_read.isi_wr_y",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr y write to ddr",
+ "MetricName": "imx95_ddr_write.isi_wr_y",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr u read from ddr",
+ "MetricName": "imx95_ddr_read.isi_wr_u",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr u write to ddr",
+ "MetricName": "imx95_ddr_write.isi_wr_u",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr v read from ddr",
+ "MetricName": "imx95_ddr_read.isi_wr_v",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr v write to ddr",
+ "MetricName": "imx95_ddr_write.isi_wr_v",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp input dma1 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_in_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp input dma1 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_in_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp input dma2 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_in_dma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp input dma2 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_in_dma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp output dma1 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_out_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp output dma1 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_out_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp output dma2 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_out_dma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp output dma2 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_out_dma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules read from ddr",
+ "MetricName": "imx95_ddr_read.camera_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules write to ddr (part1)",
+ "MetricName": "imx95_ddr_write.camera_all_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules write to ddr (part2)",
+ "MetricName": "imx95_ddr_write.camera_all_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules write to ddr (part3)",
+ "MetricName": "imx95_ddr_write.camera_all_3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display blitter store read from ddr",
+ "MetricName": "imx95_ddr_read.disp_blit",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display blitter write to ddr",
+ "MetricName": "imx95_ddr_write.disp_blit",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display command sequencer read from ddr",
+ "MetricName": "imx95_ddr_read.disp_cmd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display command sequencer write to ddr",
+ "MetricName": "imx95_ddr_write.disp_cmd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all display submodules read from ddr",
+ "MetricName": "imx95_ddr_read.disp_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all display submodules write to ddr (part1)",
+ "MetricName": "imx95_ddr_write.disp_all_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all display submodules write to ddr (part2)",
+ "MetricName": "imx95_ddr_write.disp_all_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ }
+]
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index 53ab050c8fa4..be4b541a0820 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -284,6 +284,7 @@ class JsonEvent:
'hisi_sccl,hha': 'hisi_sccl,hha',
'hisi_sccl,l3c': 'hisi_sccl,l3c',
'imx8_ddr': 'imx8_ddr',
+ 'imx9_ddr': 'imx9_ddr',
'L3PMC': 'amd_l3',
'DFPMC': 'amd_df',
'UMCPMC': 'amd_umc',
--
2.34.1
> -----Original Message-----
> From: Xu Yang <[email protected]>
> Sent: Monday, January 29, 2024 4:15 AM
> To: Frank Li <[email protected]>; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Xu Yang <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Subject: [PATCH v3 2/4] perf: imx_perf: add support for i.MX95 platform
>
> i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports
> read beat and write beat filter capabilities. This will add support for
> i.MX95 and enhance the driver to support specific filter handling for it.
>
> Usage:
>
> For read beat:
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id
> =ID/
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id
> =ID/
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id
> =ID/
> eg: For edma2: perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x0
> 0c/
>
> For write beat:
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=
> ID/
> eg: For edma2: perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00
> c/
>
> Signed-off-by: Xu Yang <[email protected]>
>
> ---
> Changes in v2:
> - put soc spefific axi filter events to drvdata according
> to franks suggestions.
> - adjust pmcfg axi_id and axi_mask config
> Changes in v3:
> - no changes
> ---
> drivers/perf/fsl_imx9_ddr_perf.c | 203 +++++++++++++++++++++++++-----
I suggest you split this two patch.
1st patch rework imx93 only, which prepare for add imx95. All function is equal.
2nd patch add imx95.
Frank
> -
> 1 file changed, 169 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/perf/fsl_imx9_ddr_perf.c
> b/drivers/perf/fsl_imx9_ddr_perf.c
> index 9685645bfe04..fd118773508d 100644
> --- a/drivers/perf/fsl_imx9_ddr_perf.c
> +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> @@ -11,14 +11,24 @@
> #include <linux/perf_event.h>
>
> /* Performance monitor configuration */
> -#define PMCFG1 0x00
> -#define PMCFG1_RD_TRANS_FILT_EN BIT(31)
> -#define PMCFG1_WR_TRANS_FILT_EN BIT(30)
> -#define PMCFG1_RD_BT_FILT_EN BIT(29)
> -#define PMCFG1_ID_MASK GENMASK(17, 0)
> +#define PMCFG1 0x00
> +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
> +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
> +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
> +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
>
> -#define PMCFG2 0x04
> -#define PMCFG2_ID GENMASK(17, 0)
> +#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31)
> +#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30)
> +
> +#define PMCFG2 0x04
> +#define MX93_PMCFG2_ID GENMASK(17, 0)
> +
> +#define PMCFG3 0x08
> +#define PMCFG4 0x0C
> +#define PMCFG5 0x10
> +#define PMCFG6 0x14
> +#define MX95_PMCFG_ID_MASK GENMASK(9, 0)
> +#define MX95_PMCFG_ID GENMASK(25, 16)
>
> /* Global control register affects all counters and takes priority over local
> control registers */
> #define PMGC0 0x40
> @@ -51,6 +61,7 @@ static DEFINE_IDA(ddr_ida);
>
> struct imx_ddr_devtype_data {
> const char *identifier; /* system PMU identifier for
> userspace */
> + struct attribute **attrs; /* AXI filter attributes */
> };
>
> struct ddr_pmu {
> @@ -67,16 +78,6 @@ struct ddr_pmu {
> int id;
> };
>
> -static const struct imx_ddr_devtype_data imx93_devtype_data = {
> - .identifier = "imx93",
> -};
> -
> -static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
> - {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
> - { /* sentinel */ }
> -};
> -MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
> -
> static ssize_t ddr_perf_identifier_show(struct device *dev,
> struct device_attribute *attr,
> char *page)
> @@ -178,7 +179,6 @@ static struct attribute *ddr_perf_events_attrs[] = {
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70),
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71),
> IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72),
> - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
>
> /* counter3 specific events */
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64),
> @@ -190,7 +190,6 @@ static struct attribute *ddr_perf_events_attrs[] = {
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70),
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71),
> IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72),
> - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
>
> /* counter4 specific events */
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64),
> @@ -202,7 +201,6 @@ static struct attribute *ddr_perf_events_attrs[] = {
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70),
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71),
> IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72),
> - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
>
> /* counter5 specific events */
> IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64),
> @@ -242,6 +240,28 @@ static const struct attribute_group
> ddr_perf_events_attr_group = {
> .attrs = ddr_perf_events_attrs,
> };
>
> +static struct attribute *imx93_ddr_perf_events_attrs[] = {
> + /* counter2 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
> + /* counter3 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
> + /* counter4 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
> + NULL,
> +};
> +
> +static struct attribute *imx95_ddr_perf_events_attrs[] = {
> + /* counter2 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73),
> + /* counter3 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73),
> + /* counter4 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73),
> + /* counter5 specific events */
> + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73),
> + NULL,
> +};
> +
> PMU_FORMAT_ATTR(event, "config:0-7");
> PMU_FORMAT_ATTR(counter, "config:8-15");
> PMU_FORMAT_ATTR(axi_id, "config1:0-17");
> @@ -268,6 +288,28 @@ static const struct attribute_group *attr_groups[] = {
> NULL,
> };
>
> +static const struct imx_ddr_devtype_data imx93_devtype_data = {
> + .identifier = "imx93",
> + .attrs = imx93_ddr_perf_events_attrs,
> +};
> +
> +static const struct imx_ddr_devtype_data imx95_devtype_data = {
> + .identifier = "imx95",
> + .attrs = imx95_ddr_perf_events_attrs,
> +};
> +
> +static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
> + { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
> + { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
> +
> +static inline bool is_imx93(struct ddr_pmu *pmu)
> +{
> + return pmu->devtype_data == &imx93_devtype_data;
> +}
> +
> static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
> {
> if (counter == CYCLES_COUNTER) {
> @@ -361,7 +403,7 @@ static void ddr_perf_counter_local_config(struct
> ddr_pmu *pmu, int config,
> }
> }
>
> -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1,
> int cfg2)
> +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg,
> int cfg1, int cfg2)
> {
> u32 pmcfg1, pmcfg2;
> int event, counter;
> @@ -372,30 +414,80 @@ static void ddr_perf_monitor_config(struct
> ddr_pmu *pmu, int cfg, int cfg1, int
> pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
>
> if (counter == 2 && event == 73)
> - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
> + pmcfg1 |= MX93_PMCFG1_RD_TRANS_FILT_EN;
> else if (counter == 2 && event != 73)
> - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
> + pmcfg1 &= ~MX93_PMCFG1_RD_TRANS_FILT_EN;
>
> if (counter == 3 && event == 73)
> - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
> + pmcfg1 |= MX93_PMCFG1_WR_TRANS_FILT_EN;
> else if (counter == 3 && event != 73)
> - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
> + pmcfg1 &= ~MX93_PMCFG1_WR_TRANS_FILT_EN;
>
> if (counter == 4 && event == 73)
> - pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
> + pmcfg1 |= MX93_PMCFG1_RD_BT_FILT_EN;
> else if (counter == 4 && event != 73)
> - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
> + pmcfg1 &= ~MX93_PMCFG1_RD_BT_FILT_EN;
>
> - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
> - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2);
> + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
> + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, cfg2);
> writel(pmcfg1, pmu->base + PMCFG1);
>
> pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
> - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
> - pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1);
> + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
> + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, cfg1);
> writel(pmcfg2, pmu->base + PMCFG2);
> }
>
> +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg,
> int cfg1, int cfg2)
> +{
> + u32 pmcfg1, pmcfg, offset = 0;
> + int event, counter;
> +
> + event = cfg & 0x000000FF;
> + counter = (cfg & 0x0000FF00) >> 8;
> +
> + pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
> +
> + if (counter == 2 && event == 73) {
> + pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN;
> + offset = PMCFG3;
> + } else if (counter == 2 && event != 73) {
> + pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN;
> + }
> +
> + if (counter == 3 && event == 73) {
> + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
> + offset = PMCFG4;
> + } else if (counter == 3 && event != 73) {
> + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
> + }
> +
> + if (counter == 4 && event == 73) {
> + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
> + offset = PMCFG5;
> + } else if (counter == 4 && event != 73) {
> + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
> + }
> +
> + if (counter == 5 && event == 73) {
> + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
> + offset = PMCFG6;
> + } else if (counter == 5 && event != 73) {
> + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
> + }
> +
> + writel(pmcfg1, pmu->base + PMCFG1);
> +
> + if (offset) {
> + pmcfg = readl_relaxed(pmu->base + offset);
> + pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
> + FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
> + pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2) |
> + FIELD_PREP(MX95_PMCFG_ID, cfg1));
> + writel(pmcfg, pmu->base + offset);
> + }
> +}
> +
> static void ddr_perf_event_update(struct perf_event *event)
> {
> struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> @@ -476,12 +568,16 @@ static int ddr_perf_event_add(struct perf_event
> *event, int flags)
> hwc->idx = counter;
> hwc->state |= PERF_HES_STOPPED;
>
> + if (is_imx93(pmu))
> + /* read trans, write trans, read beat */
> + imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> + else
> + /* write beat, read beat2, read beat1, read beat */
> + imx95_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> +
> if (flags & PERF_EF_START)
> ddr_perf_event_start(event, flags);
>
> - /* read trans, write trans, read beat */
> - ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> -
> return 0;
> }
>
> @@ -596,6 +692,39 @@ static int ddr_perf_offline_cpu(unsigned int cpu,
> struct hlist_node *node)
> return 0;
> }
>
> +static int ddr_perf_add_events(struct ddr_pmu *pmu)
> +{
> + int i, ret;
> + struct attribute **attrs = pmu->devtype_data->attrs;
> + struct device *pmu_dev = pmu->pmu.dev;
> +
> + if (!attrs)
> + return 0;
> +
> + for (i = 0; attrs[i]; i++) {
> + ret = sysfs_add_file_to_group(&pmu_dev->kobj, attrs[i],
> "events");
> + if (ret) {
> + dev_warn(pmu->dev, "i.MX9 DDR Perf add events
> failed (%d)\n", ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void ddr_perf_remove_events(struct ddr_pmu *pmu)
> +{
> + int i;
> + struct attribute **attrs = pmu->devtype_data->attrs;
> + struct device *pmu_dev = pmu->pmu.dev;
> +
> + if (!attrs)
> + return;
> +
> + for (i = 0; attrs[i]; i++)
> + sysfs_remove_file_from_group(&pmu_dev->kobj, attrs[i],
> "events");
> +}
> +
> static int ddr_perf_probe(struct platform_device *pdev)
> {
> struct ddr_pmu *pmu;
> @@ -666,6 +795,10 @@ static int ddr_perf_probe(struct platform_device
> *pdev)
> if (ret)
> goto ddr_perf_err;
>
> + ret = ddr_perf_add_events(pmu);
> + if (ret)
> + dev_warn(&pdev->dev, "i.MX9 DDR Perf filter events are
> missing\n");
> +
> return 0;
>
> ddr_perf_err:
> @@ -683,6 +816,8 @@ static int ddr_perf_remove(struct platform_device
> *pdev)
> {
> struct ddr_pmu *pmu = platform_get_drvdata(pdev);
>
> + ddr_perf_remove_events(pmu);
> +
> cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu-
> >node);
> cpuhp_remove_multi_state(pmu->cpuhp_state);
>
> --
> 2.34.1
> -----Original Message-----
> From: Xu Yang <[email protected]>
> Sent: Monday, January 29, 2024 4:15 AM
> To: Frank Li <[email protected]>; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Xu Yang <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Subject: [PATCH v3 3/4] perf: imx_perf: limit counter ID from user space and
> optimize counter usage
>
> The user can pass any counter ID to perf app. However, current pmu driver
> doesn't judge the validity of the counter ID. This will add necessary
> check for counter ID from user space. Besides, this pmu has 10 counters
> except cycle counter which can be used to count reference events and
> counter specific evnets. This will also add supports to auto allocate
> counter if the user doesn't pass it the perf. Then, the usage of counter
> will be optimized.
>
> Signed-off-by: Xu Yang <[email protected]>
>
> ---
> Changes in v2:
> - limit counter ID from user to 0-10
> - combine dynamic and static allocation of counter
> Changes in v3:
> - no changes
> ---
> drivers/perf/fsl_imx9_ddr_perf.c | 69
> +++++++++++++++++++++++++++++++-
> 1 file changed, 67 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/perf/fsl_imx9_ddr_perf.c
> b/drivers/perf/fsl_imx9_ddr_perf.c
> index fd118773508d..4bb80050920c 100644
> --- a/drivers/perf/fsl_imx9_ddr_perf.c
> +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> @@ -51,6 +51,7 @@
>
> #define NUM_COUNTERS 11
> #define CYCLES_COUNTER 0
> +#define CYCLES_EVENT_ID 0
>
> #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
>
> @@ -235,6 +236,14 @@ static struct attribute *ddr_perf_events_attrs[] = {
> NULL,
> };
>
> +static bool ddr_perf_is_specific_event(int event)
Why call specific? Name is too general. Such as is_fixed? Or Is_with_filter?
Need know what specific?
> +{
> + if (event >= 64 && event <= 73)
> + return true;
> + else
> + return false;
> +}
> +
> static const struct attribute_group ddr_perf_events_attr_group = {
> .name = "events",
> .attrs = ddr_perf_events_attrs,
> @@ -507,6 +516,7 @@ static int ddr_perf_event_init(struct perf_event
> *event)
> struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> struct hw_perf_event *hwc = &event->hw;
> struct perf_event *sibling;
> + int event_id, counter;
>
> if (event->attr.type != event->pmu->type)
> return -ENOENT;
> @@ -519,6 +529,18 @@ static int ddr_perf_event_init(struct perf_event
> *event)
> return -EOPNOTSUPP;
> }
>
> + counter = (event->attr.config & 0xFF00) >> 8;
Define 0xFF00?
> + if (counter > NUM_COUNTERS) {
> + dev_warn(pmu->dev, "Only counter 0-10 is supported!\n");
> + return -EINVAL;
> + }
> +
> + event_id = event->attr.config & 0x00FF;
same for hardcode 0x00FF
> + if (ddr_perf_is_specific_event(event_id) && counter == 0) {
> + dev_err(pmu->dev, "Need specify counter for counter
> specific events!\n");
> + return -EINVAL;
> + }
> +
> /*
> * We must NOT create groups containing mixed PMUs, although
> software
> * events are acceptable (for example to create a CCN group
> @@ -552,6 +574,39 @@ static void ddr_perf_event_start(struct perf_event
> *event, int flags)
> hwc->state = 0;
> }
>
> +static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int
> counter)
> +{
> + int i;
> +
> + if (event == CYCLES_EVENT_ID) {
> + /*
> + * Always map cycle event to counter 0.
> + * Cycles counter is dedicated for cycle event
> + * can't used for the other events.
> + */
> + if (pmu->events[CYCLES_COUNTER] == NULL)
> + return CYCLES_COUNTER;
> + } else if (counter != 0) {
> + /*
> + * 1. ddr_perf_event_init() will make sure counter
> + * is not 0 for counter specific events.
> + * 2. Allow specify counter for referene event too.
> + */
> + if (pmu->events[counter] == NULL)
> + return counter;
> + } else {
> + /*
> + * Counter may be 0 if user doesn't specify it.
> + * Auto allocate counter for referene event.
> + */
> + for (i = 1; i < NUM_COUNTERS; i++)
> + if (pmu->events[i] == NULL)
> + return i;
> + }
> +
> + return -ENOENT;
> +}
> +
> static int ddr_perf_event_add(struct perf_event *event, int flags)
> {
> struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> @@ -559,9 +614,17 @@ static int ddr_perf_event_add(struct perf_event
> *event, int flags)
> int cfg = event->attr.config;
> int cfg1 = event->attr.config1;
> int cfg2 = event->attr.config2;
> - int counter;
> + int event_id, counter;
>
> - counter = (cfg & 0x0000FF00) >> 8;
> + event_id = cfg & 0x00FF;
> + counter = (cfg & 0xFF00) >> 8;
> +
> + /* check if counter is available */
> + counter = ddr_perf_alloc_counter(pmu, event_id, counter);
> + if (counter < 0) {
> + dev_dbg(pmu->dev, "There are not enough counters\n");
> + return -EOPNOTSUPP;
> + }
>
> pmu->events[counter] = event;
> pmu->active_events++;
> @@ -597,9 +660,11 @@ static void ddr_perf_event_del(struct perf_event
> *event, int flags)
> {
> struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> struct hw_perf_event *hwc = &event->hw;
> + int counter = hwc->idx;
>
> ddr_perf_event_stop(event, PERF_EF_UPDATE);
>
> + pmu->events[counter] = NULL;
> pmu->active_events--;
> hwc->idx = -1;
> }
> --
> 2.34.1
> -----Original Message-----
> From: Xu Yang <[email protected]>
> Sent: Monday, January 29, 2024 4:15 AM
> To: Frank Li <[email protected]>; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]
> Cc: dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Xu Yang <[email protected]>; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Subject: [PATCH v3 4/4] perf vendor events arm64:: Add i.MX95 DDR
> Performane Monitor metrics
>
> Add JSON metrics for i.MX95 DDR Performane Monitor.
>
> Signed-off-by: Xu Yang <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Please add [email protected] in next version
>
> ---
> Changes in v2:
> - fix wrong AXI_MASK setting
> - remove unnecessary metrics
> - add bandwidth_usage, camera_all, disp_all metrics
> Changes in v3:
> - no changes
> ---
> .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 +
> .../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++
> tools/perf/pmu-events/jevents.py | 1 +
> 3 files changed, 788 insertions(+)
> create mode 100644 tools/perf/pmu-
> events/arch/arm64/freescale/imx95/sys/ddrc.json
> create mode 100644 tools/perf/pmu-
> events/arch/arm64/freescale/imx95/sys/metrics.json
>
> diff --git a/tools/perf/pmu-
> events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-
> events/arch/arm64/freescale/imx95/sys/ddrc.json
> new file mode 100644
> index 000000000000..4dc9d2968bdc
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
> @@ -0,0 +1,9 @@
> +[
> + {
> + "BriefDescription": "ddr cycles event",
> + "EventCode": "0x00",
> + "EventName": "imx95_ddr.cycles",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + }
> +]
> diff --git a/tools/perf/pmu-
> events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-
> events/arch/arm64/freescale/imx95/sys/metrics.json
> new file mode 100644
> index 000000000000..2bfcd4d574a8
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
> @@ -0,0 +1,778 @@
> +[
> + {
> + "BriefDescription": "bandwidth usage for lpddr5 evk board",
> + "MetricName": "imx95_bandwidth_usage.lpddr5",
> + "MetricExpr":
> "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00
> 0\\,axi_id\\=0x000@ +
> imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000\\,
> axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)",
> + "ScaleUnit": "1e2%",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all masters read from ddr",
> + "MetricName": "imx95_ddr_read.all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x000
> \\,axi_id\\=0x000@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all masters write to ddr",
> + "MetricName": "imx95_ddr_write.all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000
> \\,axi_id\\=0x000@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all a55 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3fc
> \\,axi_id\\=0x000@ +
> imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3fe\\,
> axi_id\\=0x004@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all a55 write to ddr (part1)",
> + "MetricName": "imx95_ddr_write.a55_all_1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3fc\
> \,axi_id\\=0x000@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all a55 write to ddr (part2)",
> + "MetricName": "imx95_ddr_write.a55_all_2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3fe\
> \,axi_id\\=0x004@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 0 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_0",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3ff
> \\,axi_id\\=0x000@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 0 write to ddr",
> + "MetricName": "imx95_ddr_write.a55_0",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3ff\
> \,axi_id\\=0x000@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 1 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f
> \\,axi_id\\=0x001@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 1 write to ddr",
> + "MetricName": "imx95_ddr_write.a55_1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x001@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 2 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f
> \\,axi_id\\=0x002@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 2 write to ddr",
> + "MetricName": "imx95_ddr_write.a55_2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x002@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 3 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f
> \\,axi_id\\=0x003@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 3 write to ddr",
> + "MetricName": "imx95_ddr_write.a55_3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x003@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 4 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_4",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f
> \\,axi_id\\=0x004@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 4 write to ddr",
> + "MetricName": "imx95_ddr_write.a55_4",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x004@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 5 read from ddr",
> + "MetricName": "imx95_ddr_read.a55_5",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f
> \\,axi_id\\=0x005@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of a55 core 5 write to ddr",
> + "MetricName": "imx95_ddr_write.a55_5",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x005@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP
> transactions read from ddr",
> + "MetricName": "imx95_ddr_read.cortexa_dsu_l3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f
> \\,axi_id\\=0x007@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP
> transactions write to ddr",
> + "MetricName": "imx95_ddr_write.cortexa_dsu_l3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x007@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of m33 read from ddr",
> + "MetricName": "imx95_ddr_read.m33",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f
> \\,axi_id\\=0x008@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of m33 write to ddr",
> + "MetricName": "imx95_ddr_write.m33",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x008@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of m7 read from ddr",
> + "MetricName": "imx95_ddr_read.m7",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f
> \\,axi_id\\=0x009@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of m7 write to ddr",
> + "MetricName": "imx95_ddr_write.m7",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x009@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of sentinel read from ddr",
> + "MetricName": "imx95_ddr_read.sentinel",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f
> \\,axi_id\\=0x00a@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of sentinel write to ddr",
> + "MetricName": "imx95_ddr_write.sentinel",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x00a@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of edma1 read from ddr",
> + "MetricName": "imx95_ddr_read.edma1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f
> \\,axi_id\\=0x00b@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of edma1 write to ddr",
> + "MetricName": "imx95_ddr_write.edma1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x00b@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of edma2 read from ddr",
> + "MetricName": "imx95_ddr_read.edma2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f
> \\,axi_id\\=0x00c@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of edma2 write to ddr",
> + "MetricName": "imx95_ddr_write.edma2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x00c@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of netc read from ddr",
> + "MetricName": "imx95_ddr_read.netc",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f
> \\,axi_id\\=0x00d@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of netc write to ddr",
> + "MetricName": "imx95_ddr_write.netc",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x00d@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of npu read from ddr",
> + "MetricName": "imx95_ddr_read.npu",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x010@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of npu write to ddr",
> + "MetricName": "imx95_ddr_write.npu",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x010@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of gpu read from ddr",
> + "MetricName": "imx95_ddr_read.gpu",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x020@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of gpu write to ddr",
> + "MetricName": "imx95_ddr_write.gpu",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x020@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usdhc1 read from ddr",
> + "MetricName": "imx95_ddr_read.usdhc1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x0b0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usdhc1 write to ddr",
> + "MetricName": "imx95_ddr_write.usdhc1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x0b0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usdhc2 read from ddr",
> + "MetricName": "imx95_ddr_read.usdhc2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x0c0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usdhc2 write to ddr",
> + "MetricName": "imx95_ddr_write.usdhc2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x0c0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usdhc3 read from ddr",
> + "MetricName": "imx95_ddr_read.usdhc3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x0d0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usdhc3 write to ddr",
> + "MetricName": "imx95_ddr_write.usdhc3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x0d0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of xspi read from ddr",
> + "MetricName": "imx95_ddr_read.xspi",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x0f0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of xspi write to ddr",
> + "MetricName": "imx95_ddr_write.xspi",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x0f0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie1 read from ddr",
> + "MetricName": "imx95_ddr_read.pcie1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x100@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie1 write to ddr",
> + "MetricName": "imx95_ddr_write.pcie1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x100@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie2 read from ddr",
> + "MetricName": "imx95_ddr_read.pcie2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f
> \\,axi_id\\=0x006@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie2 write to ddr",
> + "MetricName": "imx95_ddr_write.pcie2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\
> \,axi_id\\=0x006@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie3 read from ddr",
> + "MetricName": "imx95_ddr_read.pcie3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x120@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie3 write to ddr",
> + "MetricName": "imx95_ddr_write.pcie3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x120@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie4 read from ddr",
> + "MetricName": "imx95_ddr_read.pcie4",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x130@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of pcie4 write to ddr",
> + "MetricName": "imx95_ddr_write.pcie4",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x130@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usb1 read from ddr",
> + "MetricName": "imx95_ddr_read.usb1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x140@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usb1 write to ddr",
> + "MetricName": "imx95_ddr_write.usb1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x140@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usb2 read from ddr",
> + "MetricName": "imx95_ddr_read.usb2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x150@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of usb2 write to ddr",
> + "MetricName": "imx95_ddr_write.usb2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x150@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of vpu codec primary bus read
> from ddr",
> + "MetricName": "imx95_ddr_read.vpu_primy",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x180@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of vpu codec primary bus write to
> ddr",
> + "MetricName": "imx95_ddr_write.vpu_primy",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x180@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of vpu codec secondary bus read
> from ddr",
> + "MetricName": "imx95_ddr_read.vpu_secndy",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x190@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of vpu codec secondary bus write
> to ddr",
> + "MetricName": "imx95_ddr_write.vpu_secndy",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x190@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of jpeg decoder read from ddr",
> + "MetricName": "imx95_ddr_read.jpeg_dec",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x1a0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of jpeg decoder write to ddr",
> + "MetricName": "imx95_ddr_write.jpeg_dec",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x1a0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of jpeg encoder read from ddr",
> + "MetricName": "imx95_ddr_read.jpeg_dec",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x1b0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of jpeg encoder write to ddr",
> + "MetricName": "imx95_ddr_write.jpeg_enc",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x1b0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all vpu submodules read from
> ddr",
> + "MetricName": "imx95_ddr_read.vpu_all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x380
> \\,axi_id\\=0x180@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all vpu submodules write to ddr",
> + "MetricName": "imx95_ddr_write.vpu_all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x380
> \\,axi_id\\=0x180@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of cortex m0+ read from ddr",
> + "MetricName": "imx95_ddr_read.m0",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x200@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of cortex m0+ write to ddr",
> + "MetricName": "imx95_ddr_write.m0",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x200@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of camera edma read from ddr",
> + "MetricName": "imx95_ddr_read.camera_edma",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x210@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of camera edma write to ddr",
> + "MetricName": "imx95_ddr_write.camera_edma",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x210@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi rd read from ddr",
> + "MetricName": "imx95_ddr_read.isi_rd",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x220@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi rd write to ddr",
> + "MetricName": "imx95_ddr_write.isi_rd",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x220@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi wr y read from ddr",
> + "MetricName": "imx95_ddr_read.isi_wr_y",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x230@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi wr y write to ddr",
> + "MetricName": "imx95_ddr_write.isi_wr_y",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x230@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi wr u read from ddr",
> + "MetricName": "imx95_ddr_read.isi_wr_u",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x240@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi wr u write to ddr",
> + "MetricName": "imx95_ddr_write.isi_wr_u",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x240@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi wr v read from ddr",
> + "MetricName": "imx95_ddr_read.isi_wr_v",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x250@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isi wr v write to ddr",
> + "MetricName": "imx95_ddr_write.isi_wr_v",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x250@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp input dma1 read from ddr",
> + "MetricName": "imx95_ddr_read.isp_in_dma1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x260@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp input dma1 write to ddr",
> + "MetricName": "imx95_ddr_write.isp_in_dma1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x260@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp input dma2 read from ddr",
> + "MetricName": "imx95_ddr_read.isp_in_dma2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x270@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp input dma2 write to ddr",
> + "MetricName": "imx95_ddr_write.isp_in_dma2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x270@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp output dma1 read from ddr",
> + "MetricName": "imx95_ddr_read.isp_out_dma1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x280@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp output dma1 write to ddr",
> + "MetricName": "imx95_ddr_write.isp_out_dma1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x280@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp output dma2 read from ddr",
> + "MetricName": "imx95_ddr_read.isp_out_dma2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x290@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of isp output dma2 write to ddr",
> + "MetricName": "imx95_ddr_write.isp_out_dma2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x290@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all camera submodules read
> from ddr",
> + "MetricName": "imx95_ddr_read.camera_all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x380
> \\,axi_id\\=0x200@ +
> imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,
> axi_id\\=0x280@ +
> imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,
> axi_id\\=0x290@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all camera submodules write to
> ddr (part1)",
> + "MetricName": "imx95_ddr_write.camera_all_1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x380
> \\,axi_id\\=0x200@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all camera submodules write to
> ddr (part2)",
> + "MetricName": "imx95_ddr_write.camera_all_2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x280@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all camera submodules write to
> ddr (part3)",
> + "MetricName": "imx95_ddr_write.camera_all_3",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x290@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of display blitter store read from
> ddr",
> + "MetricName": "imx95_ddr_read.disp_blit",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x2a0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of display blitter write to ddr",
> + "MetricName": "imx95_ddr_write.disp_blit",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x2a0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of display command sequencer
> read from ddr",
> + "MetricName": "imx95_ddr_read.disp_cmd",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0
> \\,axi_id\\=0x2b0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of display command sequencer
> write to ddr",
> + "MetricName": "imx95_ddr_write.disp_cmd",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\
> \,axi_id\\=0x2b0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all display submodules read
> from ddr",
> + "MetricName": "imx95_ddr_read.disp_all",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x300
> \\,axi_id\\=0x300@ +
> imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3a0\\
> ,axi_id\\=0x2a0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all display submodules write to
> ddr (part1)",
> + "MetricName": "imx95_ddr_write.disp_all_1",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x300
> \\,axi_id\\=0x300@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + },
> + {
> + "BriefDescription": "bytes of all display submodules write to
> ddr (part2)",
> + "MetricName": "imx95_ddr_write.disp_all_2",
> + "MetricExpr":
> "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3a0
> \\,axi_id\\=0x2a0@ ) * 32",
> + "ScaleUnit": "9.765625e-4KB",
> + "Unit": "imx9_ddr",
> + "Compat": "imx95"
> + }
> +]
> diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-
> events/jevents.py
> index 53ab050c8fa4..be4b541a0820 100755
> --- a/tools/perf/pmu-events/jevents.py
> +++ b/tools/perf/pmu-events/jevents.py
> @@ -284,6 +284,7 @@ class JsonEvent:
> 'hisi_sccl,hha': 'hisi_sccl,hha',
> 'hisi_sccl,l3c': 'hisi_sccl,l3c',
> 'imx8_ddr': 'imx8_ddr',
> + 'imx9_ddr': 'imx9_ddr',
> 'L3PMC': 'amd_l3',
> 'DFPMC': 'amd_df',
> 'UMCPMC': 'amd_umc',
> --
> 2.34.1
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
> > Subject: [PATCH v3 2/4] perf: imx_perf: add support for i.MX95 platform
> >
> > i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports
> > read beat and write beat filter capabilities. This will add support for
> > i.MX95 and enhance the driver to support specific filter handling for it.
> >
> > Usage:
> >
> > For read beat:
> > ~# perf stat -a -I 1000 -e
> > imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id
> > =ID/
> > ~# perf stat -a -I 1000 -e
> > imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id
> > =ID/
> > ~# perf stat -a -I 1000 -e
> > imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id
> > =ID/
> > eg: For edma2: perf stat -a -I 1000 -e
> > imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x0
> > 0c/
> >
> > For write beat:
> > ~# perf stat -a -I 1000 -e
> > imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=
> > ID/
> > eg: For edma2: perf stat -a -I 1000 -e
> > imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00
> > c/
> >
> > Signed-off-by: Xu Yang <[email protected]>
> >
> > ---
> > Changes in v2:
> > - put soc spefific axi filter events to drvdata according
> > to franks suggestions.
> > - adjust pmcfg axi_id and axi_mask config
> > Changes in v3:
> > - no changes
> > ---
> > drivers/perf/fsl_imx9_ddr_perf.c | 203 +++++++++++++++++++++++++-----
>
> I suggest you split this two patch.
> 1st patch rework imx93 only, which prepare for add imx95. All function is equal.
> 2nd patch add imx95.
Okay, I'll do that in next vesion.
Thanks,
Xu Yang
Hi Frank,
> > Subject: [PATCH v3 3/4] perf: imx_perf: limit counter ID from user space and
> > optimize counter usage
> >
> > The user can pass any counter ID to perf app. However, current pmu driver
> > doesn't judge the validity of the counter ID. This will add necessary
> > check for counter ID from user space. Besides, this pmu has 10 counters
> > except cycle counter which can be used to count reference events and
> > counter specific evnets. This will also add supports to auto allocate
> > counter if the user doesn't pass it the perf. Then, the usage of counter
> > will be optimized.
> >
> > Signed-off-by: Xu Yang <[email protected]>
> >
> > ---
> > Changes in v2:
> > - limit counter ID from user to 0-10
> > - combine dynamic and static allocation of counter
> > Changes in v3:
> > - no changes
> > ---
> > drivers/perf/fsl_imx9_ddr_perf.c | 69
> > +++++++++++++++++++++++++++++++-
> > 1 file changed, 67 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c
> > b/drivers/perf/fsl_imx9_ddr_perf.c
> > index fd118773508d..4bb80050920c 100644
> > --- a/drivers/perf/fsl_imx9_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> > @@ -51,6 +51,7 @@
> >
> > #define NUM_COUNTERS 11
> > #define CYCLES_COUNTER 0
> > +#define CYCLES_EVENT_ID 0
> >
> > #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
> >
> > @@ -235,6 +236,14 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > NULL,
> > };
> >
> > +static bool ddr_perf_is_specific_event(int event)
>
> Why call specific? Name is too general. Such as is_fixed? Or Is_with_filter?
> Need know what specific?
There are only two types of event: reference event and counter specific evnet.
To make it clear, I'll change it to ddr_perf_is_counter_specific_event().
>
> > +{
> > + if (event >= 64 && event <= 73)
> > + return true;
> > + else
> > + return false;
> > +}
> > +
> > static const struct attribute_group ddr_perf_events_attr_group = {
> > .name = "events",
> > .attrs = ddr_perf_events_attrs,
> > @@ -507,6 +516,7 @@ static int ddr_perf_event_init(struct perf_event
> > *event)
> > struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> > struct hw_perf_event *hwc = &event->hw;
> > struct perf_event *sibling;
> > + int event_id, counter;
> >
> > if (event->attr.type != event->pmu->type)
> > return -ENOENT;
> > @@ -519,6 +529,18 @@ static int ddr_perf_event_init(struct perf_event
> > *event)
> > return -EOPNOTSUPP;
> > }
> >
> > + counter = (event->attr.config & 0xFF00) >> 8;
>
> Define 0xFF00?
Okay.
>
> > + if (counter > NUM_COUNTERS) {
> > + dev_warn(pmu->dev, "Only counter 0-10 is supported!\n");
> > + return -EINVAL;
> > + }
> > +
> > + event_id = event->attr.config & 0x00FF;
>
> same for hardcode 0x00FF
Okay.
Thanks,
Xu Yang
>
> > + if (ddr_perf_is_specific_event(event_id) && counter == 0) {
> > + dev_err(pmu->dev, "Need specify counter for counter
> > specific events!\n");
> > + return -EINVAL;
> > + }
> > +
> > /*
> > * We must NOT create groups containing mixed PMUs, although
> > software
> > * events are acceptable (for example to create a CCN group
> > @@ -552,6 +574,39 @@ static void ddr_perf_event_start(struct perf_event
> > *event, int flags)
> > hwc->state = 0;
> > }
> >
> > +static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int
> > counter)
> > +{
> > + int i;
> > +
> > + if (event == CYCLES_EVENT_ID) {
> > + /*
> > + * Always map cycle event to counter 0.
> > + * Cycles counter is dedicated for cycle event
> > + * can't used for the other events.
> > + */
> > + if (pmu->events[CYCLES_COUNTER] == NULL)
> > + return CYCLES_COUNTER;
> > + } else if (counter != 0) {
> > + /*
> > + * 1. ddr_perf_event_init() will make sure counter
> > + * is not 0 for counter specific events.
> > + * 2. Allow specify counter for referene event too.
> > + */
> > + if (pmu->events[counter] == NULL)
> > + return counter;
> > + } else {
> > + /*
> > + * Counter may be 0 if user doesn't specify it.
> > + * Auto allocate counter for referene event.
> > + */
> > + for (i = 1; i < NUM_COUNTERS; i++)
> > + if (pmu->events[i] == NULL)
> > + return i;
> > + }
> > +
> > + return -ENOENT;
> > +}
> > +
> > static int ddr_perf_event_add(struct perf_event *event, int flags)
> > {
> > struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> > @@ -559,9 +614,17 @@ static int ddr_perf_event_add(struct perf_event
> > *event, int flags)
> > int cfg = event->attr.config;
> > int cfg1 = event->attr.config1;
> > int cfg2 = event->attr.config2;
> > - int counter;
> > + int event_id, counter;
> >
> > - counter = (cfg & 0x0000FF00) >> 8;
> > + event_id = cfg & 0x00FF;
> > + counter = (cfg & 0xFF00) >> 8;
> > +
> > + /* check if counter is available */
> > + counter = ddr_perf_alloc_counter(pmu, event_id, counter);
> > + if (counter < 0) {
> > + dev_dbg(pmu->dev, "There are not enough counters\n");
> > + return -EOPNOTSUPP;
> > + }
> >
> > pmu->events[counter] = event;
> > pmu->active_events++;
> > @@ -597,9 +660,11 @@ static void ddr_perf_event_del(struct perf_event
> > *event, int flags)
> > {
> > struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
> > struct hw_perf_event *hwc = &event->hw;
> > + int counter = hwc->idx;
> >
> > ddr_perf_event_stop(event, PERF_EF_UPDATE);
> >
> > + pmu->events[counter] = NULL;
> > pmu->active_events--;
> > hwc->idx = -1;
> > }
> > --
> > 2.34.1
> > Subject: [PATCH v3 4/4] perf vendor events arm64:: Add i.MX95 DDR
> > Performane Monitor metrics
> >
> > Add JSON metrics for i.MX95 DDR Performane Monitor.
> >
> > Signed-off-by: Xu Yang <[email protected]>
>
> Reviewed-by: Frank Li <[email protected]>
>
> Please add [email protected] in next version
Sure.
Thanks,
Xu Yang