This series Adds FPGA manager driver support for Xilinx Versal SoC.
it uses the firmware interface to configure the programmable logic.
Changes for v4:
-Rebase the patch series on linux-next.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
Changes for v5:
-Updated binding doc's.
Changes for v6:
-Updated firmware binding doc.
Changes for v7:
-Updated versal-fpga.c driver to remove unwated priv
struct dependency.
Appana Durga Kedareswara rao (1):
dt-bindings: fpga: Add binding doc for versal fpga manager
Nava kishore Manne (3):
drivers: firmware: Add PDI load API support
dt-bindings: firmware: Add bindings for xilinx firmware
fpga: versal-fpga: Add versal fpga manager driver
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 94 ++++++++++++++++++
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++++++
drivers/firmware/xilinx/zynqmp.c | 17 ++++
drivers/fpga/Kconfig | 9 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 96 +++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 10 ++
7 files changed, 260 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
create mode 100644 drivers/fpga/versal-fpga.c
--
2.17.1
This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.
Signed-off-by: Nava kishore Manne <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
---
Changes for v2:
-Updated API Doc and commit msg.
No functional changes.
Changes for v3:
-None.
Changes for v4:
-Rebased the changes on linux-next.
No functional changes
Changes for v5:
-None.
Changes for v6:
-None.
Changes for v7:
-None.
drivers/firmware/xilinx/zynqmp.c | 17 +++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++
2 files changed, 27 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 15b138326ecc..2db571da9ad8 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1011,6 +1011,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src: Source device where PDI is located
+ * @address: PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+ lower_32_bits(address),
+ upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
/**
* zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
* AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9d1a5c175065..56b426fe020c 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,10 @@
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+/* Loader commands */
+#define PM_LOAD_PDI 0x701
+#define PDI_SRC_DDR 0xF
+
/*
* Firmware FPGA Manager flags
* XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
@@ -411,6 +415,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
u32 *value);
int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
#else
static inline int zynqmp_pm_get_api_version(u32 *version)
{
@@ -622,6 +627,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.17.1
Add documentation to describe Xilinx firmware driver bindings.
Firmware driver provides an interface to firmware APIs.
Interface APIs can be used by any driver to communicate
to Platform Management Unit.
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v4:
-Added new yaml file for xilinx firmware
as suggested by Rob.
Changes for v5:
-Fixed some minor issues and updated the fpga node name to versal_fpga.
Changes for v6:
-Added AES and Clk nodes as a sub nodes to the firmware node.
Changes for v7:
-Fixed child nodes format ssues.
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
new file mode 100644
index 000000000000..8e0241c4c137
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx firmware driver
+
+maintainers:
+ - Nava kishore Manne <[email protected]>
+
+description:
+ The zynqmp-firmware node describes the interface to platform firmware.
+ ZynqMP has an interface to communicate with secure firmware. Firmware
+ driver provides an interface to firmware APIs. Interface APIs can be
+ used by any driver to communicate to PMUFW(Platform Management Unit).
+ These requests include clock management, pin control, device control,
+ power management service, FPGA service and other platform management
+ services.
+
+properties:
+ compatible:
+ oneOf:
+ - description:
+ For implementations complying for Zynq Ultrascale+ MPSoC.
+ const: xlnx,zynqmp-firmware
+
+ - description:
+ For implementations complying for Versal.
+ const: xlnx,versal-firmware
+
+ method:
+ description: |
+ The method of calling the PM-API firmware layer.
+ Permitted values are.
+ - "smc" : SMC #0, following the SMCCC
+ - "hvc" : HVC #0, following the SMCCC
+
+ $ref: /schemas/types.yaml#/definitions/string-array
+ enum:
+ - smc
+ - hvc
+
+ "versal_fpga":
+ $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
+ description: Compatible of the FPGA device.
+ type: object
+
+ "zynqmp-aes":
+ $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
+ description: |
+ The ZynqMP AES-GCM hardened cryptographic accelerator is
+ used to encrypt or decrypt the data with provided key and
+ initialization vector.
+ type: object
+
+ "clock-controller":
+ $ref: /schemas/clock/xlnx,versal-clk.yaml#
+ description: |
+ The clock controller is a hardware block of Xilinx versal
+ clock tree. It reads required input clock frequencies from
+ the devicetree and acts as clock provider for all clock
+ consumers of PS clocks.list of clock specifiers which are
+ external input clocks to the given clock controller.
+ type: object
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ versal-firmware {
+ compatible = "xlnx,versal-firmware";
+ method = "smc";
+
+ versal_fpga: versal_fpga {
+ compatible = "xlnx,versal-fpga";
+ };
+
+ xlnx_aes: zynqmp-aes {
+ compatible = "xlnx,zynqmp-aes";
+ };
+
+ versal_clk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "xlnx,versal-clk";
+ clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
+ clock-names = "ref", "alt_ref", "pl_alt_ref";
+ };
+ };
+
+...
--
2.17.1
Add support for Xilinx Versal FPGA manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
Signed-off-by: Nava kishore Manne <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
---
Changes for v2:
-Updated the Fpga Mgr registrations call's
to 5.11
-Fixed some minor coding issues as suggested by
Moritz.
Changes for v3:
-Rewritten the Versal fpga Kconfig contents.
Changes for v4:
-Rebased the changes on linux-next.
No functional changes.
Changes for v5:
-None.
Changes for v6:
-None.
Changes for v7:
-Updated driver to remove unwated priv struct dependency.
drivers/fpga/Kconfig | 9 ++++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 96 ++++++++++++++++++++++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 drivers/fpga/versal-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 33e15058d0dc..92c20b92357a 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
to configure the programmable logic(PL) through PS
on ZynqMP SoC.
+config FPGA_MGR_VERSAL_FPGA
+ tristate "Xilinx Versal FPGA"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ help
+ Select this option to enable FPGA manager driver support for
+ Xilinx Versal SoC. This driver uses the firmware interface to
+ configure the programmable logic(PL).
+
+ To compile this as a module, choose M here.
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a..0bff783d1b61 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index 000000000000..1bd312a31b23
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+ const char *buf, size_t size)
+{
+ dma_addr_t dma_addr = 0;
+ char *kbuf;
+ int ret;
+
+ kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+ ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
+ dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+ .state = versal_fpga_ops_state,
+ .write_init = versal_fpga_ops_write_init,
+ .write = versal_fpga_ops_write,
+ .write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct fpga_manager *mgr;
+ int ret;
+
+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret < 0) {
+ dev_err(dev, "no usable DMA configuration\n");
+ return ret;
+ }
+
+ mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+ &versal_fpga_ops, NULL);
+ if (!mgr)
+ return -ENOMEM;
+
+ return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+ { .compatible = "xlnx,versal-fpga", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_driver versal_fpga_driver = {
+ .probe = versal_fpga_probe,
+ .driver = {
+ .name = "versal_fpga_manager",
+ .of_match_table = of_match_ptr(versal_fpga_of_match),
+ },
+};
+module_platform_driver(versal_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <[email protected]>");
+MODULE_AUTHOR("Appana Durga Kedareswara rao <[email protected]>");
+MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
+MODULE_LICENSE("GPL");
--
2.17.1
On Fri, Jun 04, 2021 at 05:03:32PM +0530, Nava kishore Manne wrote:
> Add support for Xilinx Versal FPGA manager.
>
> PDI source type can be DDR, OCM, QSPI flash etc..
> But driver allocates memory always from DDR, Since driver supports only
> DDR source type.
>
> Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
> Signed-off-by: Nava kishore Manne <[email protected]>
> Reviewed-by: Moritz Fischer <[email protected]>
> ---
> Changes for v2:
> -Updated the Fpga Mgr registrations call's
> to 5.11
> -Fixed some minor coding issues as suggested by
> Moritz.
>
> Changes for v3:
> -Rewritten the Versal fpga Kconfig contents.
>
> Changes for v4:
> -Rebased the changes on linux-next.
> No functional changes.
>
> Changes for v5:
> -None.
>
> Changes for v6:
> -None.
>
> Changes for v7:
> -Updated driver to remove unwated priv struct dependency.
>
> drivers/fpga/Kconfig | 9 ++++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/versal-fpga.c | 96 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 106 insertions(+)
> create mode 100644 drivers/fpga/versal-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 33e15058d0dc..92c20b92357a 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
> to configure the programmable logic(PL) through PS
> on ZynqMP SoC.
>
> +config FPGA_MGR_VERSAL_FPGA
> + tristate "Xilinx Versal FPGA"
> + depends on ARCH_ZYNQMP || COMPILE_TEST
> + help
> + Select this option to enable FPGA manager driver support for
> + Xilinx Versal SoC. This driver uses the firmware interface to
> + configure the programmable logic(PL).
> +
> + To compile this as a module, choose M here.
> endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 18dc9885883a..0bff783d1b61 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
> obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
> obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
> obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
> obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
> obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
>
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> new file mode 100644
> index 000000000000..1bd312a31b23
> --- /dev/null
> +++ b/drivers/fpga/versal-fpga.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019-2021 Xilinx, Inc.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/string.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> + struct fpga_image_info *info,
> + const char *buf, size_t size)
> +{
> + return 0;
Why have this if it does nothing?
> +}
> +
> +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> + const char *buf, size_t size)
> +{
> + dma_addr_t dma_addr = 0;
> + char *kbuf;
> + int ret;
> +
> + kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
> + if (!kbuf)
> + return -ENOMEM;
> +
> + memcpy(kbuf, buf, size);
> + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
> + dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
> +
> + return ret;
> +}
> +
> +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
> + struct fpga_image_info *info)
> +{
> + return 0;
Same here, why have this at all?
> +}
> +
> +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
> +{
> + return FPGA_MGR_STATE_UNKNOWN;
Shouln't that be the default state of the fpga manager if there is no
state function callback?
This driver should just need a write and probe function, and that's it,
why make it more complex?
thanks,
greg k-h
On 6/4/21 4:48 AM, Greg KH wrote:
> On Fri, Jun 04, 2021 at 05:03:32PM +0530, Nava kishore Manne wrote:
>> Add support for Xilinx Versal FPGA manager.
>>
>> PDI source type can be DDR, OCM, QSPI flash etc..
>> But driver allocates memory always from DDR, Since driver supports only
>> DDR source type.
>>
>> Signed-off-by: Appana Durga Kedareswara rao <[email protected]>
>> Signed-off-by: Nava kishore Manne <[email protected]>
>> Reviewed-by: Moritz Fischer <[email protected]>
>> ---
>> Changes for v2:
>> -Updated the Fpga Mgr registrations call's
>> to 5.11
>> -Fixed some minor coding issues as suggested by
>> Moritz.
>>
>> Changes for v3:
>> -Rewritten the Versal fpga Kconfig contents.
>>
>> Changes for v4:
>> -Rebased the changes on linux-next.
>> No functional changes.
>>
>> Changes for v5:
>> -None.
>>
>> Changes for v6:
>> -None.
>>
>> Changes for v7:
>> -Updated driver to remove unwated priv struct dependency.
>>
>> drivers/fpga/Kconfig | 9 ++++
>> drivers/fpga/Makefile | 1 +
>> drivers/fpga/versal-fpga.c | 96 ++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 106 insertions(+)
>> create mode 100644 drivers/fpga/versal-fpga.c
>>
>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>> index 33e15058d0dc..92c20b92357a 100644
>> --- a/drivers/fpga/Kconfig
>> +++ b/drivers/fpga/Kconfig
>> @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA
>> to configure the programmable logic(PL) through PS
>> on ZynqMP SoC.
>>
>> +config FPGA_MGR_VERSAL_FPGA
>> + tristate "Xilinx Versal FPGA"
>> + depends on ARCH_ZYNQMP || COMPILE_TEST
>> + help
>> + Select this option to enable FPGA manager driver support for
>> + Xilinx Versal SoC. This driver uses the firmware interface to
>> + configure the programmable logic(PL).
>> +
>> + To compile this as a module, choose M here.
>> endif # FPGA
>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
>> index 18dc9885883a..0bff783d1b61 100644
>> --- a/drivers/fpga/Makefile
>> +++ b/drivers/fpga/Makefile
>> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
>> obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
>> obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
>> obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
>> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
>> obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
>> obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
>>
>> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
>> new file mode 100644
>> index 000000000000..1bd312a31b23
>> --- /dev/null
>> +++ b/drivers/fpga/versal-fpga.c
>> @@ -0,0 +1,96 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2019-2021 Xilinx, Inc.
>> + */
>> +
>> +#include <linux/dma-mapping.h>
>> +#include <linux/fpga/fpga-mgr.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/string.h>
>> +#include <linux/firmware/xlnx-zynqmp.h>
>> +
>> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
>> + struct fpga_image_info *info,
>> + const char *buf, size_t size)
>> +{
>> + return 0;
> Why have this if it does nothing?
>
>> +}
>> +
>> +static int versal_fpga_ops_write(struct fpga_manager *mgr,
>> + const char *buf, size_t size)
>> +{
>> + dma_addr_t dma_addr = 0;
>> + char *kbuf;
>> + int ret;
>> +
>> + kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
>> + if (!kbuf)
>> + return -ENOMEM;
>> +
>> + memcpy(kbuf, buf, size);
>> + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
>> + dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
>> +
>> + return ret;
>> +}
>> +
>> +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
>> + struct fpga_image_info *info)
>> +{
>> + return 0;
> Same here, why have this at all?
>
>> +}
>> +
>> +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
>> +{
>> + return FPGA_MGR_STATE_UNKNOWN;
> Shouln't that be the default state of the fpga manager if there is no
> state function callback?
>
> This driver should just need a write and probe function, and that's it,
> why make it more complex?
These empty functions are needed by each board because of an aggressive
check of ops early in the bringup of the fpga mgr.
I did some deck chair shuffling here recently
https://lore.kernel.org/linux-fpga/[email protected]/
that shows location of check.
A finer grained handling of the ops would be better.
I'll add that to the next spin.
Tom
> thanks,
>
> greg k-h
>
On Fri, Jun 04, 2021 at 05:03:31PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx firmware driver bindings.
> Firmware driver provides an interface to firmware APIs.
> Interface APIs can be used by any driver to communicate
> to Platform Management Unit.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> Changes for v4:
> -Added new yaml file for xilinx firmware
> as suggested by Rob.
>
> Changes for v5:
> -Fixed some minor issues and updated the fpga node name to versal_fpga.
>
> Changes for v6:
> -Added AES and Clk nodes as a sub nodes to the firmware node.
>
> Changes for v7:
> -Fixed child nodes format ssues.
>
> .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 94 +++++++++++++++++++
> 1 file changed, 94 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
You need to remove xlnx,zynqmp-firmware.txt
>
> diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> new file mode 100644
> index 000000000000..8e0241c4c137
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx firmware driver
> +
> +maintainers:
> + - Nava kishore Manne <[email protected]>
> +
> +description:
> + The zynqmp-firmware node describes the interface to platform firmware.
> + ZynqMP has an interface to communicate with secure firmware. Firmware
> + driver provides an interface to firmware APIs. Interface APIs can be
> + used by any driver to communicate to PMUFW(Platform Management Unit).
> + These requests include clock management, pin control, device control,
> + power management service, FPGA service and other platform management
> + services.
> +
> +properties:
> + compatible:
> + oneOf:
> + - description:
> + For implementations complying for Zynq Ultrascale+ MPSoC.
> + const: xlnx,zynqmp-firmware
> +
> + - description:
> + For implementations complying for Versal.
> + const: xlnx,versal-firmware
> +
> + method:
> + description: |
> + The method of calling the PM-API firmware layer.
> + Permitted values are.
> + - "smc" : SMC #0, following the SMCCC
> + - "hvc" : HVC #0, following the SMCCC
> +
> + $ref: /schemas/types.yaml#/definitions/string-array
> + enum:
> + - smc
> + - hvc
> +
> + "versal_fpga":
Don't need quotes
> + $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
> + description: Compatible of the FPGA device.
> + type: object
> +
> + "zynqmp-aes":
Don't need quotes
> + $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
> + description: |
> + The ZynqMP AES-GCM hardened cryptographic accelerator is
> + used to encrypt or decrypt the data with provided key and
> + initialization vector.
Don't need '|' here (there's no formatting) and indent 2 more than
'description'.
> + type: object
> +
> + "clock-controller":
> + $ref: /schemas/clock/xlnx,versal-clk.yaml#
> + description: |
> + The clock controller is a hardware block of Xilinx versal
> + clock tree. It reads required input clock frequencies from
> + the devicetree and acts as clock provider for all clock
> + consumers of PS clocks.list of clock specifiers which are
> + external input clocks to the given clock controller.
> + type: object
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + versal-firmware {
> + compatible = "xlnx,versal-firmware";
> + method = "smc";
> +
> + versal_fpga: versal_fpga {
> + compatible = "xlnx,versal-fpga";
> + };
> +
> + xlnx_aes: zynqmp-aes {
> + compatible = "xlnx,zynqmp-aes";
> + };
> +
> + versal_clk: clock-controller {
> + #clock-cells = <1>;
> + compatible = "xlnx,versal-clk";
> + clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
> + clock-names = "ref", "alt_ref", "pl_alt_ref";
> + };
> + };
> +
> +...
> --
> 2.17.1
Hi Rob,
Please find my response inline.
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Thursday, June 10, 2021 9:34 PM
> To: Nava kishore Manne <[email protected]>
> Cc: Michal Simek <[email protected]>; [email protected]; [email protected];
> [email protected]; Rajan Vaja <[email protected]>;
> [email protected]; Amit Sunil Dhamne
> <[email protected]>; Tejas Patel <[email protected]>;
> [email protected]; Sai Krishna Potthuri <[email protected]>; Ravi
> Patel <[email protected]>; [email protected]; Jiaying Liang
> <[email protected]>; [email protected]; linux-arm-
> [email protected]; [email protected]; linux-
> [email protected]; git <[email protected]>; [email protected]
> Subject: Re: [PATCH v7 3/4] dt-bindings: firmware: Add bindings for xilinx
> firmware
>
> On Fri, Jun 04, 2021 at 05:03:31PM +0530, Nava kishore Manne wrote:
> > Add documentation to describe Xilinx firmware driver bindings.
> > Firmware driver provides an interface to firmware APIs.
> > Interface APIs can be used by any driver to communicate to Platform
> > Management Unit.
> >
> > Signed-off-by: Nava kishore Manne <[email protected]>
> > ---
> > Changes for v4:
> > -Added new yaml file for xilinx firmware
> > as suggested by Rob.
> >
> > Changes for v5:
> > -Fixed some minor issues and updated the fpga node name to
> versal_fpga.
> >
> > Changes for v6:
> > -Added AES and Clk nodes as a sub nodes to the firmware node.
> >
> > Changes for v7:
> > -Fixed child nodes format ssues.
> >
> > .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 94
> > +++++++++++++++++++
> > 1 file changed, 94 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmware
> > .yaml
>
> You need to remove xlnx,zynqmp-firmware.txt
>
Will fix in v8.
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > new file mode 100644
> > index 000000000000..8e0241c4c137
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > +++ rmware.yaml
> > @@ -0,0 +1,94 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.ya
> > +ml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx firmware driver
> > +
> > +maintainers:
> > + - Nava kishore Manne <[email protected]>
> > +
> > +description:
> > + The zynqmp-firmware node describes the interface to platform
> firmware.
> > + ZynqMP has an interface to communicate with secure firmware.
> > +Firmware
> > + driver provides an interface to firmware APIs. Interface APIs can
> > +be
> > + used by any driver to communicate to PMUFW(Platform Management
> Unit).
> > + These requests include clock management, pin control, device
> > +control,
> > + power management service, FPGA service and other platform
> > +management
> > + services.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - description:
> > + For implementations complying for Zynq Ultrascale+ MPSoC.
> > + const: xlnx,zynqmp-firmware
> > +
> > + - description:
> > + For implementations complying for Versal.
> > + const: xlnx,versal-firmware
> > +
> > + method:
> > + description: |
> > + The method of calling the PM-API firmware layer.
> > + Permitted values are.
> > + - "smc" : SMC #0, following the SMCCC
> > + - "hvc" : HVC #0, following the SMCCC
> > +
> > + $ref: /schemas/types.yaml#/definitions/string-array
> > + enum:
> > + - smc
> > + - hvc
> > +
> > + "versal_fpga":
>
> Don't need quotes
>
Will fix in v8.
> > + $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
> > + description: Compatible of the FPGA device.
> > + type: object
> > +
> > + "zynqmp-aes":
>
> Don't need quotes
>
Will fix in v8.
> > + $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
> > + description: |
> > + The ZynqMP AES-GCM hardened cryptographic accelerator is
> > + used to encrypt or decrypt the data with provided key and
> > + initialization vector.
>
> Don't need '|' here (there's no formatting) and indent 2 more than
> 'description'.
>
Will fix in v8.
Regards,
Navakishore.