Hi all,
This patch series adds support for the SPI Multi I/O Bus Controller
(RPC-IF) in R-Car Gen4 SoCs, which is very similar to the variant found
in R-Car Gen3 SoCs:
- The first patch fixes a missed initialization issue, which is at
least seen with the current firmware stack on R-Car V4H,
- The second patch adds the actual support, and takes care of the
increased size of the STRTIM field.
This has been tested on the White Hawk development board with R-Car V4H.
Thanks for your comments!
Cong Dang (1):
memory: renesas-rpc-if: Clear HS bit during hardware initialization
Geert Uytterhoeven (1):
memory: renesas-rpc-if: Add support for R-Car Gen4
drivers/memory/renesas-rpc-if.c | 22 +++++++++++++++-------
include/memory/renesas-rpc-if.h | 1 +
2 files changed, 16 insertions(+), 7 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
From: Cong Dang <[email protected]>
According to the datasheet, HS bit should be specified to 1 when using
DMA transfer. As DMA transfer is not supported, it should be cleared to
0.
Previously, the driver relied on the HS bit being cleared by prior
firmware but this is not always the case.
Fix this by ensuring the bit is cleared during hardware initialization.
Fixes: ca7d8b980b67f133 ("memory: add Renesas RPC-IF driver")
Signed-off-by: Cong Dang <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
drivers/memory/renesas-rpc-if.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 4316988d791a527f..61c288d403750b14 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -317,6 +317,9 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
+ /* DMA Transfer is not supported */
+ regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0);
+
if (rpc->type == RPCIF_RCAR_GEN3)
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
--
2.25.1
The SPI Multi I/O Bus Controller (RPC-IF) on R-Car Gen4 SoCs is very
similar to the RPC-IF on R-Car Gen3 SoCs. It does support four instead
of three bits of strobe timing adjustment (STRTIM), and thus requires a
new mask and new settings.
Inspired by a patch in the BSP by Cong Dang.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
drivers/memory/renesas-rpc-if.c | 19 ++++++++++++-------
include/memory/renesas-rpc-if.h | 1 +
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 61c288d403750b14..09cd4318a83d84d3 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -136,7 +136,8 @@
#define RPCIF_PHYCNT_DDRCAL BIT(19)
#define RPCIF_PHYCNT_HS BIT(18)
#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
-#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
+#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
+
#define RPCIF_PHYCNT_WBUF2 BIT(4)
#define RPCIF_PHYCNT_WBUF BIT(2)
#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
@@ -323,6 +324,9 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
if (rpc->type == RPCIF_RCAR_GEN3)
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
+ else if (rpc->type == RPCIF_RCAR_GEN4)
+ regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
+ RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15));
regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
RPCIF_PHYOFFSET1_DDRTMG(3));
@@ -333,17 +337,17 @@ int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
RPCIF_PHYINT_WPVAL, 0);
- if (rpc->type == RPCIF_RCAR_GEN3)
- regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
- RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
- RPCIF_CMNCR_MOIIO(3) |
- RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
- else
+ if (rpc->type == RPCIF_RZ_G2L)
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
RPCIF_CMNCR_BSZ(3),
RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
+ else
+ regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
+ RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
+ RPCIF_CMNCR_MOIIO(3) |
+ RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
/* Set RCF after BSZ update */
regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
@@ -718,6 +722,7 @@ static int rpcif_remove(struct platform_device *pdev)
static const struct of_device_id rpcif_of_match[] = {
{ .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
+ { .compatible = "renesas,rcar-gen4-rpc-if", .data = (void *)RPCIF_RCAR_GEN4 },
{ .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
{},
};
diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index 9c0ad64b8d292d49..862eff613dc7963d 100644
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -59,6 +59,7 @@ struct rpcif_op {
enum rpcif_type {
RPCIF_RCAR_GEN3,
+ RPCIF_RCAR_GEN4,
RPCIF_RZ_G2L,
};
--
2.25.1
On Wed, Oct 12, 2022 at 04:01:51PM +0200, Geert Uytterhoeven wrote:
> From: Cong Dang <[email protected]>
>
> According to the datasheet, HS bit should be specified to 1 when using
> DMA transfer. As DMA transfer is not supported, it should be cleared to
> 0.
>
> Previously, the driver relied on the HS bit being cleared by prior
> firmware but this is not always the case.
>
> Fix this by ensuring the bit is cleared during hardware initialization.
>
> Fixes: ca7d8b980b67f133 ("memory: add Renesas RPC-IF driver")
> Signed-off-by: Cong Dang <[email protected]>
> Signed-off-by: Hai Pham <[email protected]>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
On Wed, Oct 12, 2022 at 04:01:52PM +0200, Geert Uytterhoeven wrote:
> The SPI Multi I/O Bus Controller (RPC-IF) on R-Car Gen4 SoCs is very
> similar to the RPC-IF on R-Car Gen3 SoCs. It does support four instead
> of three bits of strobe timing adjustment (STRTIM), and thus requires a
> new mask and new settings.
>
> Inspired by a patch in the BSP by Cong Dang.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
> +#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
Very minor but I spent a minute to get it: To make sure the reader
easily understands that we want to set bit 27, we could make that maybe
more clear with:
... | !!((v) & 0x8) << 27)
But if you prefer, we can keep it like this.
On Wed, 12 Oct 2022 16:01:50 +0200, Geert Uytterhoeven wrote:
> Hi all,
>
> This patch series adds support for the SPI Multi I/O Bus Controller
> (RPC-IF) in R-Car Gen4 SoCs, which is very similar to the variant found
> in R-Car Gen3 SoCs:
> - The first patch fixes a missed initialization issue, which is at
> least seen with the current firmware stack on R-Car V4H,
> - The second patch adds the actual support, and takes care of the
> increased size of the STRTIM field.
>
> [...]
Applied, thanks!
[1/2] memory: renesas-rpc-if: Clear HS bit during hardware initialization
https://git.kernel.org/krzk/linux-mem-ctrl/c/d37f4c58e47f6129fbb8c52f6d1a70e71fc2c0c7
[2/2] memory: renesas-rpc-if: Add support for R-Car Gen4
https://git.kernel.org/krzk/linux-mem-ctrl/c/455aad51434e9622702373be57973a6c47a88684
Best regards,
--
Krzysztof Kozlowski <[email protected]>