2023-01-06 01:07:26

by Andre Przywara

[permalink] [raw]
Subject: [PATCH 1/4] dts: add riscv include prefix link

The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
die as their R528/T113-s siblings with ARM Cortex-A7 cores.

To allow sharing the basic SoC .dtsi files across those two
architectures as well, introduce a symlink to the RISC-V DT directory.

Signed-off-by: Andre Przywara <[email protected]>
---
scripts/dtc/include-prefixes/riscv | 1 +
1 file changed, 1 insertion(+)
create mode 120000 scripts/dtc/include-prefixes/riscv

diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
new file mode 120000
index 0000000000000..2025094189380
--- /dev/null
+++ b/scripts/dtc/include-prefixes/riscv
@@ -0,0 +1 @@
+../../../arch/riscv/boot/dts
\ No newline at end of file
--
2.35.5


2023-01-08 17:29:01

by Conor Dooley

[permalink] [raw]
Subject: Re: [PATCH 1/4] dts: add riscv include prefix link

On Fri, Jan 06, 2023 at 01:01:52AM +0000, Andre Przywara wrote:
> The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
> die as their R528/T113-s siblings with ARM Cortex-A7 cores.
>
> To allow sharing the basic SoC .dtsi files across those two
> architectures as well, introduce a symlink to the RISC-V DT directory.

Reviewed-by: Conor Dooley <[email protected]>

Thanks,
Conor.

>
> Signed-off-by: Andre Przywara <[email protected]>
> ---
> scripts/dtc/include-prefixes/riscv | 1 +
> 1 file changed, 1 insertion(+)
> create mode 120000 scripts/dtc/include-prefixes/riscv
>
> diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
> new file mode 120000
> index 0000000000000..2025094189380
> --- /dev/null
> +++ b/scripts/dtc/include-prefixes/riscv
> @@ -0,0 +1 @@
> +../../../arch/riscv/boot/dts
> \ No newline at end of file
> --
> 2.35.5
>
>

Attachments:
(No filename) (953.00 B)
 signature.asc (235.00 B)
 Download all attachments

2023-03-07 20:59:40

by Palmer Dabbelt

[permalink] [raw]
Subject: Re: [PATCH 1/4] dts: add riscv include prefix link

On Thu, 05 Jan 2023 17:01:52 PST (-0800), [email protected] wrote:
> The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
> die as their R528/T113-s siblings with ARM Cortex-A7 cores.
>
> To allow sharing the basic SoC .dtsi files across those two
> architectures as well, introduce a symlink to the RISC-V DT directory.
>
> Signed-off-by: Andre Przywara <[email protected]>
> ---
> scripts/dtc/include-prefixes/riscv | 1 +
> 1 file changed, 1 insertion(+)
> create mode 120000 scripts/dtc/include-prefixes/riscv
>
> diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv
> new file mode 120000
> index 0000000000000..2025094189380
> --- /dev/null
> +++ b/scripts/dtc/include-prefixes/riscv
> @@ -0,0 +1 @@
> +../../../arch/riscv/boot/dts
> \ No newline at end of file

Acked-by: Palmer Dabbelt <[email protected]>