This series includes a few minor binding updates and base device tree
files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
The series is dependent on a few driver patches to merge first, for
gcc, rpmhcc and pinctrl
https://lore.kernel.org/patchwork/project/lkml/list/?series=484517
https://lore.kernel.org/patchwork/project/lkml/list/?series=484489
https://lore.kernel.org/patchwork/patch/1379831/
Maulik Shah (3):
arm64: dts: qcom: sc7280: Add RSC and PDC devices
arm64: dts: qcom: Add reserved memory for fw
arm64: dts: qcom: sc7280: Add cpuidle states
Rajendra Nayak (5):
dt-bindings: arm: qcom: Document SC7280 SoC and board
dt-bindings: firmware: scm: Add SC7280 support
arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
dt-bindings: qcom,pdc: Add compatible for sc7280
arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
Sai Prakash Ranjan (4):
dt-bindings: arm-smmu: Add compatible for SC7280 SoC
arm64: dts: qcom: sc7280: Add device node for APPS SMMU
dt-bindings: watchdog: Add compatible for SC7280 SoC
arm64: dts: qcom: sc7280: Add APSS watchdog node
satya priya (1):
arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
.../devicetree/bindings/firmware/qcom,scm.txt | 1 +
.../bindings/interrupt-controller/qcom,pdc.txt | 1 +
.../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
.../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++
8 files changed, 654 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89 ++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 10851e7..f71ba21 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -280,6 +280,95 @@
};
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Maulik Shah <[email protected]>
Add cpuidle states for little and big cpus.
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78 ++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8f2002b..3b86052 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -99,6 +99,9 @@
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -114,6 +117,9 @@
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -126,6 +132,9 @@
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -138,6 +147,9 @@
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -150,6 +162,9 @@
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
@@ -162,6 +177,9 @@
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
@@ -174,6 +192,9 @@
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
@@ -186,12 +207,69 @@
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <549>;
+ exit-latency-us = <901>;
+ min-residency-us = <1774>;
+ local-timer-stop;
+ };
+
+ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-rail-power-down";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <915>;
+ min-residency-us = <4001>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <523>;
+ exit-latency-us = <1244>;
+ min-residency-us = <2207>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-rail-power-down";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <526>;
+ exit-latency-us = <1854>;
+ min-residency-us = <5555>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "cluster-power-down";
+ arm,psci-suspend-param = <0x40003444>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9926>;
+ local-timer-stop;
+ };
+ };
};
memory@80000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b5b9b6a..ef82d77 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -399,6 +399,13 @@
};
};
+ watchdog@17c10000 {
+ compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
+ reg = <0 0x17c10000 0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Add compatible for watchdog timer on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
index 8e3760a..b5b1268 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sc7180
+ - qcom,apss-wdt-sc7280
- qcom,apss-wdt-sdm845
- qcom,apss-wdt-sm8150
- qcom,kpss-timer
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Quoting Rajendra Nayak (2021-02-11 23:28:47)
> From: Sai Prakash Ranjan <[email protected]>
>
> Add compatible for watchdog timer on SC7280 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> Signed-off-by: Rajendra Nayak <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Rajendra Nayak (2021-02-11 23:28:50)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 8f2002b..3b86052 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -186,12 +207,69 @@
> compatible = "arm,kryo";
> reg = <0x0 0x700>;
> enable-method = "psci";
> + cpu-idle-states = <&BIG_CPU_SLEEP_0
> + &BIG_CPU_SLEEP_1
> + &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_700>;
> L2_700: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> };
> };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "little-power-down";
> + arm,psci-suspend-param = <0x40000003>;
> + entry-latency-us = <549>;
> + exit-latency-us = <901>;
> + min-residency-us = <1774>;
Are these preliminary numbers? They're the same as sc7180 from what I
can tell, but presumably things changed between SoC versions?
> + local-timer-stop;
> + };
> +
> + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
> + compatible = "arm,idle-state";
> + idle-state-name = "little-rail-power-down";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <702>;
> + exit-latency-us = <915>;
> + min-residency-us = <4001>;
> + local-timer-stop;
> + };
> +
> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "big-power-down";
> + arm,psci-suspend-param = <0x40000003>;
> + entry-latency-us = <523>;
> + exit-latency-us = <1244>;
> + min-residency-us = <2207>;
Quoting Rajendra Nayak (2021-02-11 23:28:48)
> From: Sai Prakash Ranjan <[email protected]>
>
> Add APSS (Application Processor Subsystem) watchdog
> DT node for SC7280 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> Signed-off-by: Rajendra Nayak <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Hi Stephen,
On 2/23/2021 1:19 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-02-11 23:28:50)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 8f2002b..3b86052 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -186,12 +207,69 @@
>> compatible = "arm,kryo";
>> reg = <0x0 0x700>;
>> enable-method = "psci";
>> + cpu-idle-states = <&BIG_CPU_SLEEP_0
>> + &BIG_CPU_SLEEP_1
>> + &CLUSTER_SLEEP_0>;
>> next-level-cache = <&L2_700>;
>> L2_700: l2-cache {
>> compatible = "cache";
>> next-level-cache = <&L3_0>;
>> };
>> };
>> +
>> + idle-states {
>> + entry-method = "psci";
>> +
>> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "little-power-down";
>> + arm,psci-suspend-param = <0x40000003>;
>> + entry-latency-us = <549>;
>> + exit-latency-us = <901>;
>> + min-residency-us = <1774>;
> Are these preliminary numbers? They're the same as sc7180 from what I
> can tell, but presumably things changed between SoC versions?
yes they are preliminary numbers, we are yet to measure on sc7280 and
will update later once measured.
Thanks,
Maulik
>
>> + local-timer-stop;
>> + };
>> +
>> + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "little-rail-power-down";
>> + arm,psci-suspend-param = <0x40000004>;
>> + entry-latency-us = <702>;
>> + exit-latency-us = <915>;
>> + min-residency-us = <4001>;
>> + local-timer-stop;
>> + };
>> +
>> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "big-power-down";
>> + arm,psci-suspend-param = <0x40000003>;
>> + entry-latency-us = <523>;
>> + exit-latency-us = <1244>;
>> + min-residency-us = <2207>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote:
> This series includes a few minor binding updates and base device tree
> files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
>
> The series is dependent on a few driver patches to merge first, for
> gcc, rpmhcc and pinctrl
> https://lore.kernel.org/patchwork/project/lkml/list/?series=484517
> https://lore.kernel.org/patchwork/project/lkml/list/?series=484489
> https://lore.kernel.org/patchwork/patch/1379831/
>
I'm not able to find v2 of this series, but plenty of patches that
depends on its content. Do I somehow miss it, or is it coming?
Regards,
Bjorn
> Maulik Shah (3):
> arm64: dts: qcom: sc7280: Add RSC and PDC devices
> arm64: dts: qcom: Add reserved memory for fw
> arm64: dts: qcom: sc7280: Add cpuidle states
>
> Rajendra Nayak (5):
> dt-bindings: arm: qcom: Document SC7280 SoC and board
> dt-bindings: firmware: scm: Add SC7280 support
> arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
> dt-bindings: qcom,pdc: Add compatible for sc7280
> arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
>
> Sai Prakash Ranjan (4):
> dt-bindings: arm-smmu: Add compatible for SC7280 SoC
> arm64: dts: qcom: sc7280: Add device node for APPS SMMU
> dt-bindings: watchdog: Add compatible for SC7280 SoC
> arm64: dts: qcom: sc7280: Add APSS watchdog node
>
> satya priya (1):
> arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
>
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
> .../devicetree/bindings/firmware/qcom,scm.txt | 1 +
> .../bindings/interrupt-controller/qcom,pdc.txt | 1 +
> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++
> 8 files changed, 654 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
On 3/11/2021 5:43 AM, Bjorn Andersson wrote:
> On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote:
>
>> This series includes a few minor binding updates and base device tree
>> files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
>>
>> The series is dependent on a few driver patches to merge first, for
>> gcc, rpmhcc and pinctrl
>> https://lore.kernel.org/patchwork/project/lkml/list/?series=484517
>> https://lore.kernel.org/patchwork/project/lkml/list/?series=484489
>> https://lore.kernel.org/patchwork/patch/1379831/
>>
>
> I'm not able to find v2 of this series, but plenty of patches that
> depends on its content. Do I somehow miss it, or is it coming?
I did post v2 [1], and will post v3 shortly addressing some of
the feedback from Stephen on v2. I was waiting on the rpmh clock
fix to come out [2], which addresses the question about the XO clock
frequency [3] in DT
[1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403
[2] https://lore.kernel.org/patchwork/patch/1393159/
[3] https://lore.kernel.org/patchwork/patch/1389019/
> Regards,
> Bjorn
>
>> Maulik Shah (3):
>> arm64: dts: qcom: sc7280: Add RSC and PDC devices
>> arm64: dts: qcom: Add reserved memory for fw
>> arm64: dts: qcom: sc7280: Add cpuidle states
>>
>> Rajendra Nayak (5):
>> dt-bindings: arm: qcom: Document SC7280 SoC and board
>> dt-bindings: firmware: scm: Add SC7280 support
>> arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
>> dt-bindings: qcom,pdc: Add compatible for sc7280
>> arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
>>
>> Sai Prakash Ranjan (4):
>> dt-bindings: arm-smmu: Add compatible for SC7280 SoC
>> arm64: dts: qcom: sc7280: Add device node for APPS SMMU
>> dt-bindings: watchdog: Add compatible for SC7280 SoC
>> arm64: dts: qcom: sc7280: Add APSS watchdog node
>>
>> satya priya (1):
>> arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
>>
>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
>> .../devicetree/bindings/firmware/qcom,scm.txt | 1 +
>> .../bindings/interrupt-controller/qcom,pdc.txt | 1 +
>> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
>> .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++
>> 8 files changed, 654 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
>>
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 3/11/2021 2:45 PM, Rajendra Nayak wrote:
>
> On 3/11/2021 5:43 AM, Bjorn Andersson wrote:
>> On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote:
>>
>>> This series includes a few minor binding updates and base device tree
>>> files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
>>>
>>> The series is dependent on a few driver patches to merge first, for
>>> gcc, rpmhcc and pinctrl
>>> https://lore.kernel.org/patchwork/project/lkml/list/?series=484517
>>> https://lore.kernel.org/patchwork/project/lkml/list/?series=484489
>>> https://lore.kernel.org/patchwork/patch/1379831/
>>>
>>
>> I'm not able to find v2 of this series, but plenty of patches that
>> depends on its content. Do I somehow miss it, or is it coming?
>
> I did post v2 [1], and will post v3 shortly addressing some of
Posted a v3 now [1], also re-based on msm/for-next
[1] https://lore.kernel.org/patchwork/project/lkml/list/?series=488871
> the feedback from Stephen on v2. I was waiting on the rpmh clock
> fix to come out [2], which addresses the question about the XO clock
> frequency [3] in DT
>
> [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403
> [2] https://lore.kernel.org/patchwork/patch/1393159/
> [3] https://lore.kernel.org/patchwork/patch/1389019/
>
>> Regards,
>> Bjorn
>>
>>> Maulik Shah (3):
>>> arm64: dts: qcom: sc7280: Add RSC and PDC devices
>>> arm64: dts: qcom: Add reserved memory for fw
>>> arm64: dts: qcom: sc7280: Add cpuidle states
>>>
>>> Rajendra Nayak (5):
>>> dt-bindings: arm: qcom: Document SC7280 SoC and board
>>> dt-bindings: firmware: scm: Add SC7280 support
>>> arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
>>> dt-bindings: qcom,pdc: Add compatible for sc7280
>>> arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
>>>
>>> Sai Prakash Ranjan (4):
>>> dt-bindings: arm-smmu: Add compatible for SC7280 SoC
>>> arm64: dts: qcom: sc7280: Add device node for APPS SMMU
>>> dt-bindings: watchdog: Add compatible for SC7280 SoC
>>> arm64: dts: qcom: sc7280: Add APSS watchdog node
>>>
>>> satya priya (1):
>>> arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
>>>
>>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
>>> .../devicetree/bindings/firmware/qcom,scm.txt | 1 +
>>> .../bindings/interrupt-controller/qcom,pdc.txt | 1 +
>>> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
>>> .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
>>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++
>>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++
>>> 8 files changed, 654 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
>>> create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
>>>
>>> --
>>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
>>> of Code Aurora Forum, hosted by The Linux Foundation
>>>
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On Thu 11 Mar 03:15 CST 2021, Rajendra Nayak wrote:
>
> On 3/11/2021 5:43 AM, Bjorn Andersson wrote:
> > On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote:
> >
> > > This series includes a few minor binding updates and base device tree
> > > files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
> > >
> > > The series is dependent on a few driver patches to merge first, for
> > > gcc, rpmhcc and pinctrl
> > > https://lore.kernel.org/patchwork/project/lkml/list/?series=484517
> > > https://lore.kernel.org/patchwork/project/lkml/list/?series=484489
> > > https://lore.kernel.org/patchwork/patch/1379831/
> > >
> >
> > I'm not able to find v2 of this series, but plenty of patches that
> > depends on its content. Do I somehow miss it, or is it coming?
>
> I did post v2 [1], and will post v3 shortly addressing some of
> the feedback from Stephen on v2.
Sorry, I had filtered my inbox view a little bit too hard and missed it.
v3 looks good to me, so I'll pick it to allow me to land other pending
patches on top.
Thank you,
Bjorn
> I was waiting on the rpmh clock fix to come out [2], which addresses
> the question about the XO clock frequency [3] in DT
>
> [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403
> [2] https://lore.kernel.org/patchwork/patch/1393159/
> [3] https://lore.kernel.org/patchwork/patch/1389019/
>
> > Regards,
> > Bjorn
> >
> > > Maulik Shah (3):
> > > arm64: dts: qcom: sc7280: Add RSC and PDC devices
> > > arm64: dts: qcom: Add reserved memory for fw
> > > arm64: dts: qcom: sc7280: Add cpuidle states
> > >
> > > Rajendra Nayak (5):
> > > dt-bindings: arm: qcom: Document SC7280 SoC and board
> > > dt-bindings: firmware: scm: Add SC7280 support
> > > arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
> > > dt-bindings: qcom,pdc: Add compatible for sc7280
> > > arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
> > >
> > > Sai Prakash Ranjan (4):
> > > dt-bindings: arm-smmu: Add compatible for SC7280 SoC
> > > arm64: dts: qcom: sc7280: Add device node for APPS SMMU
> > > dt-bindings: watchdog: Add compatible for SC7280 SoC
> > > arm64: dts: qcom: sc7280: Add APSS watchdog node
> > >
> > > satya priya (1):
> > > arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
> > >
> > > Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
> > > .../devicetree/bindings/firmware/qcom,scm.txt | 1 +
> > > .../bindings/interrupt-controller/qcom,pdc.txt | 1 +
> > > .../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> > > .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
> > > arch/arm64/boot/dts/qcom/Makefile | 1 +
> > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++
> > > 8 files changed, 654 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
> > >
> > > --
> > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> > > of Code Aurora Forum, hosted by The Linux Foundation
> > >
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation