This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP
and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
[1] https://lore.kernel.org/patchwork/cover/1379842/
Sai Prakash Ranjan (9):
dt-bindings: arm: msm: Add LLCC for SC7280
soc: qcom: llcc: Add configuration data for SC7280
arm64: dts: qcom: sc7280: Add device tree node for LLCC
dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
dt-bindings: soc: qcom: aoss: Add SC7280 compatible
soc: qcom: aoss: Add AOSS QMP support for SC7280
arm64: dts: qcom: sc7280: Add AOSS QMP node
arm64: dts: qcom: sc7280: Add Coresight support
.../bindings/arm/msm/qcom,llcc.yaml | 1 +
.../bindings/mailbox/qcom-ipcc.yaml | 1 +
.../bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 520 ++++++++++++++++++
drivers/soc/qcom/llcc-qcom.c | 19 +
drivers/soc/qcom/qcom_aoss.c | 1 +
6 files changed, 543 insertions(+)
base-commit: d79b47c59576a51d8e288a6b98b75ccf4afb8acd
prerequisite-patch-id: d8babdd3c8a9923360af342f3d8d9876820272e5
prerequisite-patch-id: 5757e07e4336d773d402769d09106924962ce31b
prerequisite-patch-id: 9b21eb51aa86619f5695a511c65c9236e3bc0f2b
prerequisite-patch-id: 2f834cc892f7f9109cbf32a87d504ba27b64a5df
prerequisite-patch-id: 14b1185357703d750c3411a16e97675489ca7dde
prerequisite-patch-id: 55c143f21b646c18da921a62bbd2801a5df38c8f
prerequisite-patch-id: 66f4c58aff2f1a7283b0103590ff82384907bae3
prerequisite-patch-id: 75e73e6b13ab91ed5e3a96b59957aa5e867d65ea
prerequisite-patch-id: eb46845b4f9eb3706a26911042c2865a58577198
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add LLCC configuration data for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
drivers/soc/qcom/llcc-qcom.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 8403a77b59fe..15a36dcab990 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -109,6 +109,18 @@ static const struct llcc_slice_config sc7180_data[] = {
{ LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
};
+static const struct llcc_slice_config sc7280_data[] = {
+ { LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
+ { LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+ { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+ { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+ { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+ { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
+ { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+ { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+ { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
+};
+
static const struct llcc_slice_config sdm845_data[] = {
{ LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
{ LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
@@ -179,6 +191,12 @@ static const struct qcom_llcc_config sc7180_cfg = {
.need_llcc_cfg = true,
};
+static const struct qcom_llcc_config sc7280_cfg = {
+ .sct_data = sc7280_data,
+ .size = ARRAY_SIZE(sc7280_data),
+ .need_llcc_cfg = true,
+};
+
static const struct qcom_llcc_config sdm845_cfg = {
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
@@ -606,6 +624,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
static const struct of_device_id qcom_llcc_of_match[] = {
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
+ { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3b86052b78bc..aeeb47c70c3a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -338,6 +338,13 @@ uart5: serial@994000 {
};
};
+ system-cache-controller@9200000 {
+ compatible = "qcom,sc7280-llcc";
+ reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0xb220000 0 0x30000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add SC7280 AOSS QMP compatible to the list of possible bindings.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
index 19c059e44681..783dc81b0f26 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
@@ -17,6 +17,7 @@ power-domains.
Value type: <string>
Definition: must be one of:
"qcom,sc7180-aoss-qmp"
+ "qcom,sc7280-aoss-qmp"
"qcom,sdm845-aoss-qmp"
"qcom,sm8150-aoss-qmp"
"qcom,sm8250-aoss-qmp"
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add the IPCC DT node which is used to send and receive IPC
signals with remoteprocs for SC7280 SoC.
Cc: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index aeeb47c70c3a..65c1e0f2fb56 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -315,6 +316,15 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
};
+ ipcc: mailbox@408000 {
+ compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
+ reg = <0 0x00408000 0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add IPCC compatible for SC7280 SoC.
Cc: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index 168beeb7e9f7..06419543d235 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,sc7280-ipcc
- qcom,sm8250-ipcc
- const: qcom,ipcc
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add coresight components found on SC7280 SoC.
Cc: Mathieu Poirier <[email protected]>
Cc: Suzuki K Poulose <[email protected]>
Cc: Mike Leach <[email protected]>
Cc: Leo Yan <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 489 +++++++++++++++++++++++++++
1 file changed, 489 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index cbd567ccc04e..3245a18fa2a1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -349,6 +349,495 @@ uart5: serial@994000 {
};
};
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>,
+ <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint = <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06042000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint = <&merge_funnel_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ funnel1_in4: endpoint {
+ remote-endpoint = <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint = <&swao_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint = <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint = <&funnel1_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&swao_replicator_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+ iommus = <&apps_smmu 0x04c0 0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint = <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06b04000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ swao_funnel_out: endpoint {
+ remote-endpoint = <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ swao_funnel_in: endpoint {
+ remote-endpoint = <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etf@6b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06b05000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint = <&swao_replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint = <&swao_funnel_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06b06000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ qcom,replicator-loses-context;
+
+ out-ports {
+ port {
+ swao_replicator_out: endpoint {
+ remote-endpoint = <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ swao_replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 { /* APSS Funnel */
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in4>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add AOSS QMP support for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
---
drivers/soc/qcom/qcom_aoss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 53acb9423bd6..934fcc4d2b05 100644
--- a/drivers/soc/qcom/qcom_aoss.c
+++ b/drivers/soc/qcom/qcom_aoss.c
@@ -597,6 +597,7 @@ static int qmp_remove(struct platform_device *pdev)
static const struct of_device_id qmp_dt_match[] = {
{ .compatible = "qcom,sc7180-aoss-qmp", },
+ { .compatible = "qcom,sc7280-aoss-qmp", },
{ .compatible = "qcom,sdm845-aoss-qmp", },
{ .compatible = "qcom,sm8150-aoss-qmp", },
{ .compatible = "qcom,sm8250-aoss-qmp", },
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On Thu, Feb 25, 2021 at 03:00:21PM +0530, Sai Prakash Ranjan wrote:
> Add the IPCC DT node which is used to send and receive IPC
> signals with remoteprocs for SC7280 SoC.
>
> Cc: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index aeeb47c70c3a..65c1e0f2fb56 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> / {
> @@ -315,6 +316,15 @@ gcc: clock-controller@100000 {
> #power-domain-cells = <1>;
> };
>
> + ipcc: mailbox@408000 {
> + compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
> + reg = <0 0x00408000 0 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #mbox-cells = <2>;
> + };
> +
> qupv3_id_0: geniqup@9c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0 0x009c0000 0 0x2000>;
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
On Thu, Feb 25, 2021 at 03:00:20PM +0530, Sai Prakash Ranjan wrote:
> Add IPCC compatible for SC7280 SoC.
>
> Cc: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> index 168beeb7e9f7..06419543d235 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> @@ -24,6 +24,7 @@ properties:
> compatible:
> items:
> - enum:
> + - qcom,sc7280-ipcc
> - qcom,sm8250-ipcc
> - const: qcom,ipcc
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
Quoting Sai Prakash Ranjan (2021-02-25 01:30:20)
> Add IPCC compatible for SC7280 SoC.
>
> Cc: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Sai Prakash Ranjan (2021-02-25 01:30:21)
> Add the IPCC DT node which is used to send and receive IPC
> signals with remoteprocs for SC7280 SoC.
>
> Cc: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
> Add a DT node for Last level cache (aka. system cache)
> controller which provides control over the last level
> cache present on SC7280 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Should add system-cache-controller to the devicetree spec. Or just use
cache-controller for the node name.
Quoting Sai Prakash Ranjan (2021-02-25 01:30:23)
> Add AOSS QMP support for SC7280 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Sai Prakash Ranjan (2021-02-25 01:30:22)
> Add SC7280 AOSS QMP compatible to the list of possible bindings.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
On 2021-02-26 01:07, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
>> Add a DT node for Last level cache (aka. system cache)
>> controller which provides control over the last level
>> cache present on SC7280 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <[email protected]>
>> ---
>
> Reviewed-by: Stephen Boyd <[email protected]>
>
> Should add system-cache-controller to the devicetree spec. Or just use
> cache-controller for the node name.
This was as per discussion in [1][2] where dt-schema throws an error
since it expects cache-level to be associated with cache-controller.
[1]
https://lore.kernel.org/lkml/[email protected]/
[2]
https://lore.kernel.org/lkml/[email protected]/
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
> On 2021-02-26 01:07, Stephen Boyd wrote:
> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
> >> Add a DT node for Last level cache (aka. system cache)
> >> controller which provides control over the last level
> >> cache present on SC7280 SoC.
> >>
> >> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> >> ---
> >
> > Reviewed-by: Stephen Boyd <[email protected]>
> >
> > Should add system-cache-controller to the devicetree spec. Or just use
> > cache-controller for the node name.
>
> This was as per discussion in [1][2] where dt-schema throws an error
> since it expects cache-level to be associated with cache-controller.
>
Ah right. Can you add system-cache-controller to the dt spec?
On 2021-02-27 00:15, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
>> On 2021-02-26 01:07, Stephen Boyd wrote:
>> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
>> >> Add a DT node for Last level cache (aka. system cache)
>> >> controller which provides control over the last level
>> >> cache present on SC7280 SoC.
>> >>
>> >> Signed-off-by: Sai Prakash Ranjan <[email protected]>
>> >> ---
>> >
>> > Reviewed-by: Stephen Boyd <[email protected]>
>> >
>> > Should add system-cache-controller to the devicetree spec. Or just use
>> > cache-controller for the node name.
>>
>> This was as per discussion in [1][2] where dt-schema throws an error
>> since it expects cache-level to be associated with cache-controller.
>>
>
> Ah right. Can you add system-cache-controller to the dt spec?
Sure, I'll add it. Hopefully that won't have to block this change?
Because I might need some time to get permissions to add it there.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
Quoting Sai Prakash Ranjan (2021-02-27 05:58:25)
> On 2021-02-27 00:15, Stephen Boyd wrote:
> > Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
> >> On 2021-02-26 01:07, Stephen Boyd wrote:
> >> > Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
> >> >> Add a DT node for Last level cache (aka. system cache)
> >> >> controller which provides control over the last level
> >> >> cache present on SC7280 SoC.
> >> >>
> >> >> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> >> >> ---
> >> >
> >> > Reviewed-by: Stephen Boyd <[email protected]>
> >> >
> >> > Should add system-cache-controller to the devicetree spec. Or just use
> >> > cache-controller for the node name.
> >>
> >> This was as per discussion in [1][2] where dt-schema throws an error
> >> since it expects cache-level to be associated with cache-controller.
> >>
> >
> > Ah right. Can you add system-cache-controller to the dt spec?
>
> Sure, I'll add it. Hopefully that won't have to block this change?
> Because I might need some time to get permissions to add it there.
>
Doesn't block it for me.
On Thu, 25 Feb 2021 15:00:22 +0530, Sai Prakash Ranjan wrote:
> Add SC7280 AOSS QMP compatible to the list of possible bindings.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Thu 25 Feb 03:30 CST 2021, Sai Prakash Ranjan wrote:
> This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP
> and Coresight on SC7280 SoC.
>
> This series is dependent on the base support added for SC7280 in [1].
>
I've picked some of these patches...
It would be helpful if you split series like this based on how they will
be picked up my various maintainers. E.g. I think it's quite likely
Jassi won't find and pick up the mailbox binding patch.
PS. I sent a patch to Jassi adding the mailbox binding directory to
MAINTAINERS.
Regards,
Bjorn
> [1] https://lore.kernel.org/patchwork/cover/1379842/
>
> Sai Prakash Ranjan (9):
> dt-bindings: arm: msm: Add LLCC for SC7280
> soc: qcom: llcc: Add configuration data for SC7280
> arm64: dts: qcom: sc7280: Add device tree node for LLCC
> dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280
> arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoC
> dt-bindings: soc: qcom: aoss: Add SC7280 compatible
> soc: qcom: aoss: Add AOSS QMP support for SC7280
> arm64: dts: qcom: sc7280: Add AOSS QMP node
> arm64: dts: qcom: sc7280: Add Coresight support
>
> .../bindings/arm/msm/qcom,llcc.yaml | 1 +
> .../bindings/mailbox/qcom-ipcc.yaml | 1 +
> .../bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 520 ++++++++++++++++++
> drivers/soc/qcom/llcc-qcom.c | 19 +
> drivers/soc/qcom/qcom_aoss.c | 1 +
> 6 files changed, 543 insertions(+)
>
>
> base-commit: d79b47c59576a51d8e288a6b98b75ccf4afb8acd
> prerequisite-patch-id: d8babdd3c8a9923360af342f3d8d9876820272e5
> prerequisite-patch-id: 5757e07e4336d773d402769d09106924962ce31b
> prerequisite-patch-id: 9b21eb51aa86619f5695a511c65c9236e3bc0f2b
> prerequisite-patch-id: 2f834cc892f7f9109cbf32a87d504ba27b64a5df
> prerequisite-patch-id: 14b1185357703d750c3411a16e97675489ca7dde
> prerequisite-patch-id: 55c143f21b646c18da921a62bbd2801a5df38c8f
> prerequisite-patch-id: 66f4c58aff2f1a7283b0103590ff82384907bae3
> prerequisite-patch-id: 75e73e6b13ab91ed5e3a96b59957aa5e867d65ea
> prerequisite-patch-id: eb46845b4f9eb3706a26911042c2865a58577198
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
On 2021-03-12 04:44, Bjorn Andersson wrote:
> On Thu 25 Feb 03:30 CST 2021, Sai Prakash Ranjan wrote:
>
>> This series enables various hardware blocks such as LLCC, IPCC, AOSS
>> QMP
>> and Coresight on SC7280 SoC.
>>
>> This series is dependent on the base support added for SC7280 in [1].
>>
>
> I've picked some of these patches...
>
>
> It would be helpful if you split series like this based on how they
> will
> be picked up my various maintainers. E.g. I think it's quite likely
> Jassi won't find and pick up the mailbox binding patch.
>
>
> PS. I sent a patch to Jassi adding the mailbox binding directory to
> MAINTAINERS.
>
Sure I will group patches(mainly dt-bindings for other subsystems)
accordingly.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation