This patch set adds supports for i.MX8MQ and i.MX8QM, both of them extend new features.
Fugang Duan (5):
dt-bindings: fec: add the missing clocks properties
dt-bindings: fec: add RGMII delayed clock property
net: fec: add imx8mq and imx8qm new versions support
net: fec: add eee mode tx lpi support
net: fec: add MAC internal delayed clock feature support
.../devicetree/bindings/net/fsl-fec.txt | 15 ++
drivers/net/ethernet/freescale/fec.h | 25 +++
drivers/net/ethernet/freescale/fec_main.c | 145 ++++++++++++++++++
3 files changed, 185 insertions(+)
--
2.17.1
From: Fugang Duan <[email protected]>
Both driver and dts have already used these clocks properties, so add the
missing clocks info.
Signed-off-by: Fugang Duan <[email protected]>
Signed-off-by: Joakim Zhang <[email protected]>
---
Documentation/devicetree/bindings/net/fsl-fec.txt | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 9b543789cd52..6754be1b91c4 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -39,6 +39,17 @@ Optional properties:
tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts.
For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
per second interrupt associated with 1588 precision time protocol(PTP).
+- clocks: Phandles to input clocks.
+- clock-name: Should be the names of the clocks
+ - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
+ - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
+ - "ptp"(option), for IEEE1588 timer clock that requires the clock.
+ - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
+ RGMII TXC clock or RMII reference clock. It depends on board design,
+ the clock is required if RGMII TXC and RMII reference clock source from
+ SOC internal PLL.
+ - "enet_out"(option), output clock for external device, like supply clock
+ for PHY. The clock is required if PHY clock source from SOC.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
--
2.17.1
From: Fugang Duan <[email protected]>
The i.MX8MQ ENET version support IEEE802.3az eee mode, add
eee mode tx lpi enable to support ethtool interface.
usage:
1. set sleep and wake timer to 5ms:
ethtool --set-eee eth0 eee on tx-lpi on tx-timer 5000
2. check the eee mode:
~# ethtool --show-eee eth0
EEE Settings for eth0:
EEE status: enabled - active
Tx LPI: 5000 (us)
Supported EEE link modes: 100baseT/Full
1000baseT/Full
Advertised EEE link modes: 100baseT/Full
1000baseT/Full
Link partner advertised EEE link modes: 100baseT/Full
Note: For realtime case and IEEE1588 ptp case, it should disable
EEE mode.
Signed-off-by: Fugang Duan <[email protected]>
Signed-off-by: Joakim Zhang <[email protected]>
---
drivers/net/ethernet/freescale/fec.h | 6 ++
drivers/net/ethernet/freescale/fec_main.c | 89 +++++++++++++++++++++++
2 files changed, 95 insertions(+)
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index c1f93aa79d63..0a741bc440e4 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -77,6 +77,8 @@
#define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
#define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
#define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */
+#define FEC_LPI_SLEEP 0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */
+#define FEC_LPI_WAKE 0x1f8 /* Set IEEE802.3az LPI Wake Tw time */
#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
@@ -602,6 +604,10 @@ struct fec_enet_private {
unsigned int tx_time_itr;
unsigned int itr_clk_rate;
+ /* tx lpi eee mode */
+ struct ethtool_eee eee;
+ unsigned int clk_ref_rate;
+
u32 rx_copybreak;
/* ptp clock period in ns*/
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index dd0b8715e84e..24082b3f2118 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -2722,6 +2722,92 @@ static int fec_enet_set_tunable(struct net_device *netdev,
return ret;
}
+/* LPI Sleep Ts count base on tx clk (clk_ref).
+ * The lpi sleep cnt value = X us / (cycle_ns).
+ */
+static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+ return us * (fep->clk_ref_rate / 1000) / 1000;
+}
+
+static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ struct ethtool_eee *p = &fep->eee;
+ unsigned int sleep_cycle, wake_cycle;
+ int ret = 0;
+
+ if (enable) {
+ ret = phy_init_eee(ndev->phydev, 0);
+ if (ret)
+ return ret;
+
+ sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
+ wake_cycle = sleep_cycle;
+ } else {
+ sleep_cycle = 0;
+ wake_cycle = 0;
+ }
+
+ p->tx_lpi_enabled = enable;
+ p->eee_enabled = enable;
+ p->eee_active = enable;
+
+ writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
+ writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
+
+ return 0;
+}
+
+static int
+fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ struct ethtool_eee *p = &fep->eee;
+
+ if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
+ return -EOPNOTSUPP;
+
+ if (!netif_running(ndev))
+ return -ENETDOWN;
+
+ edata->eee_enabled = p->eee_enabled;
+ edata->eee_active = p->eee_active;
+ edata->tx_lpi_timer = p->tx_lpi_timer;
+ edata->tx_lpi_enabled = p->tx_lpi_enabled;
+
+ return phy_ethtool_get_eee(ndev->phydev, edata);
+}
+
+static int
+fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ struct ethtool_eee *p = &fep->eee;
+ int ret = 0;
+
+ if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
+ return -EOPNOTSUPP;
+
+ if (!netif_running(ndev))
+ return -ENETDOWN;
+
+ p->tx_lpi_timer = edata->tx_lpi_timer;
+
+ if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
+ !edata->tx_lpi_timer)
+ ret = fec_enet_eee_mode_set(ndev, false);
+ else
+ ret = fec_enet_eee_mode_set(ndev, true);
+
+ if (ret)
+ return ret;
+
+ return phy_ethtool_set_eee(ndev->phydev, edata);
+}
+
static void
fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
{
@@ -2782,6 +2868,8 @@ static const struct ethtool_ops fec_enet_ethtool_ops = {
.set_tunable = fec_enet_set_tunable,
.get_wol = fec_enet_get_wol,
.set_wol = fec_enet_set_wol,
+ .get_eee = fec_enet_get_eee,
+ .set_eee = fec_enet_set_eee,
.get_link_ksettings = phy_ethtool_get_link_ksettings,
.set_link_ksettings = phy_ethtool_set_link_ksettings,
.self_test = net_selftest,
@@ -3722,6 +3810,7 @@ fec_probe(struct platform_device *pdev)
fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
if (IS_ERR(fep->clk_ref))
fep->clk_ref = NULL;
+ fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
--
2.17.1
From: Fugang Duan <[email protected]>
i.MX8QM ENET IP version support timing specification that MAC
integrate clock delay in RGMII mode, the delayed TXC/RXC as an
alternative option to work well with various PHYs.
Signed-off-by: Fugang Duan <[email protected]>
Signed-off-by: Joakim Zhang <[email protected]>
---
drivers/net/ethernet/freescale/fec.h | 6 ++++++
drivers/net/ethernet/freescale/fec_main.c | 26 +++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 0a741bc440e4..ae3259164395 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -381,6 +381,9 @@ struct bufdesc_ex {
#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
+#define FEC_ENET_TXC_DLY ((uint)0x00010000)
+#define FEC_ENET_RXC_DLY ((uint)0x00020000)
+
/* ENET interrupt coalescing macro define */
#define FEC_ITR_CLK_SEL (0x1 << 30)
#define FEC_ITR_EN (0x1 << 31)
@@ -543,6 +546,7 @@ struct fec_enet_private {
struct clk *clk_ref;
struct clk *clk_enet_out;
struct clk *clk_ptp;
+ struct clk *clk_2x_txclk;
bool ptp_clk_on;
struct mutex ptp_clk_mutex;
@@ -565,6 +569,8 @@ struct fec_enet_private {
uint phy_speed;
phy_interface_t phy_interface;
struct device_node *phy_node;
+ bool rgmii_txc_dly;
+ bool rgmii_rxc_dly;
int link;
int full_duplex;
int speed;
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 24082b3f2118..18ab60322688 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -1137,6 +1137,13 @@ fec_restart(struct net_device *ndev)
if (fep->bufdesc_ex)
ecntl |= (1 << 4);
+ if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
+ fep->rgmii_txc_dly)
+ ecntl |= FEC_ENET_TXC_DLY;
+ if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
+ fep->rgmii_rxc_dly)
+ ecntl |= FEC_ENET_RXC_DLY;
+
#ifndef CONFIG_M5272
/* Enable the MIB statistic event counters */
writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
@@ -2000,6 +2007,10 @@ static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
if (ret)
goto failed_clk_ref;
+ ret = clk_prepare_enable(fep->clk_2x_txclk);
+ if (ret)
+ goto failed_clk_2x_txclk;
+
fec_enet_phy_reset_after_clk_enable(ndev);
} else {
clk_disable_unprepare(fep->clk_enet_out);
@@ -2010,10 +2021,14 @@ static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
mutex_unlock(&fep->ptp_clk_mutex);
}
clk_disable_unprepare(fep->clk_ref);
+ clk_disable_unprepare(fep->clk_2x_txclk);
}
return 0;
+failed_clk_2x_txclk:
+ if (fep->clk_ref)
+ clk_disable_unprepare(fep->clk_ref);
failed_clk_ref:
if (fep->clk_ptp) {
mutex_lock(&fep->ptp_clk_mutex);
@@ -3761,6 +3776,12 @@ fec_probe(struct platform_device *pdev)
if (ret)
goto failed_stop_mode;
+ if (of_get_property(np, "fsl,rgmii_txc_dly", NULL))
+ fep->rgmii_txc_dly = true;
+
+ if (of_get_property(np, "fsl,rgmii_rxc_dly", NULL))
+ fep->rgmii_rxc_dly = true;
+
phy_node = of_parse_phandle(np, "phy-handle", 0);
if (!phy_node && of_phy_is_fixed_link(np)) {
ret = of_phy_register_fixed_link(np);
@@ -3812,6 +3833,11 @@ fec_probe(struct platform_device *pdev)
fep->clk_ref = NULL;
fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
+ /* clk_2x_txclk is optional, depends on board */
+ fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
+ if (IS_ERR(fep->clk_2x_txclk))
+ fep->clk_2x_txclk = NULL;
+
fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
if (IS_ERR(fep->clk_ptp)) {
--
2.17.1
From: Fugang Duan <[email protected]>
Add property for RGMII delayed clock.
Signed-off-by: Fugang Duan <[email protected]>
Signed-off-by: Joakim Zhang <[email protected]>
---
Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 6754be1b91c4..f93b9552cfc5 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -50,6 +50,10 @@ Optional properties:
SOC internal PLL.
- "enet_out"(option), output clock for external device, like supply clock
for PHY. The clock is required if PHY clock source from SOC.
+ - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz.
+ The clock is required if SOC RGMII enable clock delay.
+- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC.
+- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
--
2.17.1
From: Fugang Duan <[email protected]>
The ENET of imx8mq and imx8qm are basically the same as imx6sx,
but they have new features support based on imx6sx, like:
- imx8mq: supports IEEE 802.3az EEE standard.
- imx8qm: supports RGMII mode delayed clock.
Signed-off-by: Fugang Duan <[email protected]>
Signed-off-by: Joakim Zhang <[email protected]>
---
drivers/net/ethernet/freescale/fec.h | 13 ++++++++++
drivers/net/ethernet/freescale/fec_main.c | 30 +++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 2e002e4b4b4a..c1f93aa79d63 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -472,6 +472,19 @@ struct bufdesc_ex {
*/
#define FEC_QUIRK_HAS_MULTI_QUEUES (1 << 19)
+/* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
+ * standard. For the transmission, MAC supply two user registers to set
+ * Sleep (TS) and Wake (TW) time.
+ */
+#define FEC_QUIRK_HAS_EEE (1 << 20)
+
+/* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
+ * as an alternative option to make sure it works well with various PHYs.
+ * For the implementation of delayed clock, ENET takes synchronized 250MHz
+ * clocks to generate 2ns delay.
+ */
+#define FEC_QUIRK_DELAYED_CLKS_SUPPORT (1 << 21)
+
struct bufdesc_prop {
int qid;
/* Address of Rx and Tx buffers */
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 8aea707a65a7..dd0b8715e84e 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -135,6 +135,26 @@ static const struct fec_devinfo fec_imx6ul_info = {
FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
};
+static const struct fec_devinfo fec_imx8mq_info = {
+ .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
+ FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
+ FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
+ FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
+ FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
+ FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
+ FEC_QUIRK_HAS_EEE,
+};
+
+static const struct fec_devinfo fec_imx8qm_info = {
+ .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
+ FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
+ FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
+ FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
+ FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
+ FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
+ FEC_QUIRK_DELAYED_CLKS_SUPPORT,
+};
+
static struct platform_device_id fec_devtype[] = {
{
/* keep it for coldfire */
@@ -161,6 +181,12 @@ static struct platform_device_id fec_devtype[] = {
}, {
.name = "imx6ul-fec",
.driver_data = (kernel_ulong_t)&fec_imx6ul_info,
+ }, {
+ .name = "imx8mq-fec",
+ .driver_data = (kernel_ulong_t)&fec_imx8mq_info,
+ }, {
+ .name = "imx8qm-fec",
+ .driver_data = (kernel_ulong_t)&fec_imx8qm_info,
}, {
/* sentinel */
}
@@ -175,6 +201,8 @@ enum imx_fec_type {
MVF600_FEC,
IMX6SX_FEC,
IMX6UL_FEC,
+ IMX8MQ_FEC,
+ IMX8QM_FEC,
};
static const struct of_device_id fec_dt_ids[] = {
@@ -185,6 +213,8 @@ static const struct of_device_id fec_dt_ids[] = {
{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
+ { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
+ { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fec_dt_ids);
--
2.17.1
On Fri, Jul 09, 2021 at 04:18:21PM +0800, Joakim Zhang wrote:
> From: Fugang Duan <[email protected]>
>
> The ENET of imx8mq and imx8qm are basically the same as imx6sx,
> but they have new features support based on imx6sx, like:
> - imx8mq: supports IEEE 802.3az EEE standard.
> - imx8qm: supports RGMII mode delayed clock.
>
> Signed-off-by: Fugang Duan <[email protected]>
> Signed-off-by: Joakim Zhang <[email protected]>
> ---
> drivers/net/ethernet/freescale/fec.h | 13 ++++++++++
> drivers/net/ethernet/freescale/fec_main.c | 30 +++++++++++++++++++++++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
> index 2e002e4b4b4a..c1f93aa79d63 100644
> --- a/drivers/net/ethernet/freescale/fec.h
> +++ b/drivers/net/ethernet/freescale/fec.h
> @@ -472,6 +472,19 @@ struct bufdesc_ex {
> */
> #define FEC_QUIRK_HAS_MULTI_QUEUES (1 << 19)
>
> +/* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
> + * standard. For the transmission, MAC supply two user registers to set
> + * Sleep (TS) and Wake (TW) time.
> + */
> +#define FEC_QUIRK_HAS_EEE (1 << 20)
> +
> +/* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
> + * as an alternative option to make sure it works well with various PHYs.
> + * For the implementation of delayed clock, ENET takes synchronized 250MHz
> + * clocks to generate 2ns delay.
> + */
> +#define FEC_QUIRK_DELAYED_CLKS_SUPPORT (1 << 21)
> +
> struct bufdesc_prop {
> int qid;
> /* Address of Rx and Tx buffers */
> diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
> index 8aea707a65a7..dd0b8715e84e 100644
> --- a/drivers/net/ethernet/freescale/fec_main.c
> +++ b/drivers/net/ethernet/freescale/fec_main.c
> @@ -135,6 +135,26 @@ static const struct fec_devinfo fec_imx6ul_info = {
> FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
> };
>
> +static const struct fec_devinfo fec_imx8mq_info = {
> + .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
> + FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
> + FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
> + FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
> + FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
> + FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
> + FEC_QUIRK_HAS_EEE,
> +};
> +
> +static const struct fec_devinfo fec_imx8qm_info = {
> + .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
> + FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
> + FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
> + FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
> + FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
> + FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
> + FEC_QUIRK_DELAYED_CLKS_SUPPORT,
> +};
> +
> static struct platform_device_id fec_devtype[] = {
> {
> /* keep it for coldfire */
> @@ -161,6 +181,12 @@ static struct platform_device_id fec_devtype[] = {
> }, {
> .name = "imx6ul-fec",
> .driver_data = (kernel_ulong_t)&fec_imx6ul_info,
> + }, {
> + .name = "imx8mq-fec",
> + .driver_data = (kernel_ulong_t)&fec_imx8mq_info,
> + }, {
> + .name = "imx8qm-fec",
> + .driver_data = (kernel_ulong_t)&fec_imx8qm_info,
> }, {
> /* sentinel */
> }
> @@ -175,6 +201,8 @@ enum imx_fec_type {
> MVF600_FEC,
> IMX6SX_FEC,
> IMX6UL_FEC,
> + IMX8MQ_FEC,
> + IMX8QM_FEC,
> };
>
> static const struct of_device_id fec_dt_ids[] = {
> @@ -185,6 +213,8 @@ static const struct of_device_id fec_dt_ids[] = {
> { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
> { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
> { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
> + { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
> + { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
I don't think these are documented.
Rob
On Fri, Jul 09, 2021 at 04:18:19PM +0800, Joakim Zhang wrote:
> From: Fugang Duan <[email protected]>
>
> Both driver and dts have already used these clocks properties, so add the
> missing clocks info.
>
> Signed-off-by: Fugang Duan <[email protected]>
> Signed-off-by: Joakim Zhang <[email protected]>
> ---
> Documentation/devicetree/bindings/net/fsl-fec.txt | 11 +++++++++++
> 1 file changed, 11 insertions(+)
There's enough changes in this series, please convert this to schema.
>
> diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
> index 9b543789cd52..6754be1b91c4 100644
> --- a/Documentation/devicetree/bindings/net/fsl-fec.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
> @@ -39,6 +39,17 @@ Optional properties:
> tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts.
> For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
> per second interrupt associated with 1588 precision time protocol(PTP).
> +- clocks: Phandles to input clocks.
> +- clock-name: Should be the names of the clocks
> + - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
> + - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
> + - "ptp"(option), for IEEE1588 timer clock that requires the clock.
> + - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
> + RGMII TXC clock or RMII reference clock. It depends on board design,
> + the clock is required if RGMII TXC and RMII reference clock source from
> + SOC internal PLL.
> + - "enet_out"(option), output clock for external device, like supply clock
> + for PHY. The clock is required if PHY clock source from SOC.
>
> Optional subnodes:
> - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
> --
> 2.17.1
>
>
On Fri, Jul 09, 2021 at 04:18:20PM +0800, Joakim Zhang wrote:
> From: Fugang Duan <[email protected]>
>
> Add property for RGMII delayed clock.
>
> Signed-off-by: Fugang Duan <[email protected]>
> Signed-off-by: Joakim Zhang <[email protected]>
> ---
> Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
> index 6754be1b91c4..f93b9552cfc5 100644
> --- a/Documentation/devicetree/bindings/net/fsl-fec.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
> @@ -50,6 +50,10 @@ Optional properties:
> SOC internal PLL.
> - "enet_out"(option), output clock for external device, like supply clock
> for PHY. The clock is required if PHY clock source from SOC.
> + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz.
> + The clock is required if SOC RGMII enable clock delay.
> +- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC.
> +- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC.
Don't we have standard properties for this?
>
> Optional subnodes:
> - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
> --
> 2.17.1
>
>
On Wed, Jul 14, 2021 at 05:19:37PM -0600, Rob Herring wrote:
> On Fri, Jul 09, 2021 at 04:18:20PM +0800, Joakim Zhang wrote:
> > From: Fugang Duan <[email protected]>
> >
> > Add property for RGMII delayed clock.
> >
> > Signed-off-by: Fugang Duan <[email protected]>
> > Signed-off-by: Joakim Zhang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/net/fsl-fec.txt | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
> > index 6754be1b91c4..f93b9552cfc5 100644
> > --- a/Documentation/devicetree/bindings/net/fsl-fec.txt
> > +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
> > @@ -50,6 +50,10 @@ Optional properties:
> > SOC internal PLL.
> > - "enet_out"(option), output clock for external device, like supply clock
> > for PHY. The clock is required if PHY clock source from SOC.
> > + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz.
> > + The clock is required if SOC RGMII enable clock delay.
> > +- fsl,rgmii_txc_dly: add RGMII TXC delayed clock from MAC.
> > +- fsl,rgmii_rxc_dly: add RGMII RXC delayed clock from MAC.
>
> Don't we have standard properties for this?
Yes, rx-internal-delay-ps and tx-internal-delay-ps defined in
ethernet-controller.yaml
Andrew
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: 2021??7??15?? 7:19
> To: Joakim Zhang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>
> Subject: Re: [PATCH V1 net-next 1/5] dt-bindings: fec: add the missing clocks
> properties
>
> On Fri, Jul 09, 2021 at 04:18:19PM +0800, Joakim Zhang wrote:
> > From: Fugang Duan <[email protected]>
> >
> > Both driver and dts have already used these clocks properties, so add
> > the missing clocks info.
> >
> > Signed-off-by: Fugang Duan <[email protected]>
> > Signed-off-by: Joakim Zhang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/net/fsl-fec.txt | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
>
> There's enough changes in this series, please convert this to schema.
Hi Rob,
Ok, I will first convert this binding into schema, then resend this patch set.
Best Regards,
Joakim Zhang
> >
> > diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt
> > b/Documentation/devicetree/bindings/net/fsl-fec.txt
> > index 9b543789cd52..6754be1b91c4 100644
> > --- a/Documentation/devicetree/bindings/net/fsl-fec.txt
> > +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
> > @@ -39,6 +39,17 @@ Optional properties:
> > tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII
> interrupts.
> > For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the
> pulse
> > per second interrupt associated with 1588 precision time protocol(PTP).
> > +- clocks: Phandles to input clocks.
> > +- clock-name: Should be the names of the clocks
> > + - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
> > + - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
> > + - "ptp"(option), for IEEE1588 timer clock that requires the clock.
> > + - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
> > + RGMII TXC clock or RMII reference clock. It depends on board design,
> > + the clock is required if RGMII TXC and RMII reference clock source from
> > + SOC internal PLL.
> > + - "enet_out"(option), output clock for external device, like supply clock
> > + for PHY. The clock is required if PHY clock source from SOC.
> >
> > Optional subnodes:
> > - mdio : specifies the mdio bus in the FEC, used as a container for
> > phy nodes
> > --
> > 2.17.1
> >
> >