This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel
(download.01.org/perfmon/) for Icelake. The official encoding
is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0
umask 0x1.
With this patch applied it is possible to run:
$ perf record -a -e cpu/event=0x00,umask=0x1/pp .....
Whereas before this would fail.
To avoid problems with tools which may use the old code, we maintain the old
encoding for Icelake.
Signed-off-by: Stephane Eranian <[email protected]>
---
arch/x86/events/intel/core.c | 5 +++--
arch/x86/events/intel/ds.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9a044438072b..bc3f97f83401 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -243,7 +243,8 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
static struct event_constraint intel_icl_event_constraints[] = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
- FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
+ FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
@@ -288,7 +289,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
static struct event_constraint intel_spr_event_constraints[] = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
- FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 8647713276a7..4dbb55a43dad 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -923,7 +923,8 @@ struct event_constraint intel_skl_pebs_event_constraints[] = {
};
struct event_constraint intel_icl_pebs_event_constraints[] = {
- INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
@@ -943,7 +944,7 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {
};
struct event_constraint intel_spr_pebs_event_constraints[] = {
- INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),
+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
--
2.33.0.1079.g6e70778dc9-goog
On 10/13/2021 5:12 PM, Stephane Eranian wrote:
> This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel
> (download.01.org/perfmon/) for Icelake. The official encoding
> is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0
> umask 0x1.
>
> With this patch applied it is possible to run:
> $ perf record -a -e cpu/event=0x00,umask=0x1/pp .....
>
> Whereas before this would fail.
>
> To avoid problems with tools which may use the old code, we maintain the old
> encoding for Icelake.
>
> Signed-off-by: Stephane Eranian <[email protected]>
Make sense.
Reviewed-by: Andi Kleen <[email protected]>
-Andi
On Wed, Oct 13, 2021 at 05:12:14PM -0700, Stephane Eranian wrote:
> This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel
> (download.01.org/perfmon/) for Icelake. The official encoding
> is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0
> umask 0x1.
>
> With this patch applied it is possible to run:
> $ perf record -a -e cpu/event=0x00,umask=0x1/pp .....
>
> Whereas before this would fail.
>
> To avoid problems with tools which may use the old code, we maintain the old
> encoding for Icelake.
Uuuuhhhhh.. but we 'stole' event=0x00 for the fake events. There must
not be actual hardware events there or we're in trouble. I thought Intel
knew that, I'm sure I told them that.
On Thu, Oct 14, 2021 at 3:09 AM Peter Zijlstra <[email protected]> wrote:
>
> On Wed, Oct 13, 2021 at 05:12:14PM -0700, Stephane Eranian wrote:
> > This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel
> > (download.01.org/perfmon/) for Icelake. The official encoding
> > is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0
> > umask 0x1.
> >
> > With this patch applied it is possible to run:
> > $ perf record -a -e cpu/event=0x00,umask=0x1/pp .....
> >
> > Whereas before this would fail.
> >
> > To avoid problems with tools which may use the old code, we maintain the old
> > encoding for Icelake.
>
> Uuuuhhhhh.. but we 'stole' event=0x00 for the fake events. There must
> not be actual hardware events there or we're in trouble. I thought Intel
> knew that, I'm sure I told them that.
Yes, this is a pseudo event code. INST_RETIRED.PREC_DIST 0x0100 only
works on fixed counter 0
to deliver the better sample distribution.
On Thu, Oct 14, 2021 at 11:01:15AM -0700, Stephane Eranian wrote:
> On Thu, Oct 14, 2021 at 3:09 AM Peter Zijlstra <[email protected]> wrote:
> >
> > On Wed, Oct 13, 2021 at 05:12:14PM -0700, Stephane Eranian wrote:
> > > This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel
> > > (download.01.org/perfmon/) for Icelake. The official encoding
> > > is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0
> > > umask 0x1.
> > >
> > > With this patch applied it is possible to run:
> > > $ perf record -a -e cpu/event=0x00,umask=0x1/pp .....
> > >
> > > Whereas before this would fail.
> > >
> > > To avoid problems with tools which may use the old code, we maintain the old
> > > encoding for Icelake.
> >
> > Uuuuhhhhh.. but we 'stole' event=0x00 for the fake events. There must
> > not be actual hardware events there or we're in trouble. I thought Intel
> > knew that, I'm sure I told them that.
>
> Yes, this is a pseudo event code. INST_RETIRED.PREC_DIST 0x0100 only
> works on fixed counter 0
> to deliver the better sample distribution.
Ah, okay. Thanks!
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 2de71ee153efa93099d2ab864acffeec70a8dcd5
Gitweb: https://git.kernel.org/tip/2de71ee153efa93099d2ab864acffeec70a8dcd5
Author: Stephane Eranian <[email protected]>
AuthorDate: Wed, 13 Oct 2021 17:12:14 -07:00
Committer: Peter Zijlstra <[email protected]>
CommitterDate: Sat, 30 Oct 2021 16:37:24 +02:00
perf/x86/intel: Fix ICL/SPR INST_RETIRED.PREC_DIST encodings
This patch fixes the encoding for INST_RETIRED.PREC_DIST as published by Intel
(download.01.org/perfmon/) for Icelake. The official encoding
is event code 0x00 umask 0x1, a change from Skylake where it was code 0xc0
umask 0x1.
With this patch applied it is possible to run:
$ perf record -a -e cpu/event=0x00,umask=0x1/pp .....
Whereas before this would fail.
To avoid problems with tools which may use the old code, we maintain the old
encoding for Icelake.
Signed-off-by: Stephane Eranian <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
---
arch/x86/events/intel/core.c | 5 +++--
arch/x86/events/intel/ds.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a555e7c..c67d95e 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -243,7 +243,8 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
static struct event_constraint intel_icl_event_constraints[] = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
- FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
+ FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
@@ -287,7 +288,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
static struct event_constraint intel_spr_event_constraints[] = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
- FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 8647713..4dbb55a 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -923,7 +923,8 @@ struct event_constraint intel_skl_pebs_event_constraints[] = {
};
struct event_constraint intel_icl_pebs_event_constraints[] = {
- INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
@@ -943,7 +944,7 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {
};
struct event_constraint intel_spr_pebs_event_constraints[] = {
- INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),
+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),