The SA8155p-ADP board supports on-board ethernet (Gibabit Interface),
with support for both RGMII and RMII buses.
This patchset adds the support for the same.
Note that this patchset is based on an earlier sent patchset
for adding PDC controller support on SM8150 (see [1]).
[1]. https://lore.kernel.org/linux-arm-msm/[email protected]/T
Bhupesh Sharma (3):
clk: qcom: gcc: Add PCIe, EMAC and UFS GDSCs for SM8150
clk: qcom: gcc-sm8150: use runtime PM for the clock controller
clk: qcom: gcc-sm8150: Use PWRSTS_ON (only) as a workaround for emac
gdsc
Bjorn Andersson (1):
net: stmmac: dwmac-qcom-ethqos: Adjust rgmii loopback_en per platform
Vinod Koul (4):
dt-bindings: net: qcom,ethqos: Document SM8150 SoC compatible
net: stmmac: Add support for SM8150
arm64: dts: qcom: sm8150: add ethernet node
arm64: dts: qcom: sa8155p-adp: Enable ethernet node
.../devicetree/bindings/net/qcom,ethqos.txt | 4 +-
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 144 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 ++++
drivers/clk/qcom/gcc-sm8150.c | 105 +++++++++++--
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 37 ++++-
include/dt-bindings/clock/qcom,gcc-sm8150.h | 9 +-
6 files changed, 305 insertions(+), 21 deletions(-)
--
2.34.1
From: Vinod Koul <[email protected]>
This adds compatible, POR config & driver data for ethernet controller
found in SM8150 SoC.
Cc: David S. Miller <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
[bhsharma: Massage the commit log and other cosmetic changes]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
.../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 2ffa0a11eea5..8cdba9d521ec 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -183,6 +183,20 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
.num_por = ARRAY_SIZE(emac_v2_3_0_por),
};
+static const struct ethqos_emac_por emac_v2_1_0_por[] = {
+ { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
+ { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
+ { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
+ { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
+ { .offset = SDCC_USR_CTL, .value = 0x00010800 },
+ { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
+};
+
+static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
+ .por = emac_v2_1_0_por,
+ .num_por = ARRAY_SIZE(emac_v2_1_0_por),
+};
+
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
{
unsigned int val;
@@ -558,6 +572,7 @@ static int qcom_ethqos_remove(struct platform_device *pdev)
static const struct of_device_id qcom_ethqos_match[] = {
{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
+ { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
{ }
};
MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
--
2.34.1
From: Vinod Koul <[email protected]>
SM8150 SoC supports ethqos ethernet controller so add the node for it
Cc: Bjorn Andersson <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
[bhsharma: Correct ethernet interrupt numbers and add power-domain]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 463732bcfc07..70cf4651598a 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -915,6 +915,33 @@ gpi_dma0: dma-controller@800000 {
status = "disabled";
};
+ ethernet: ethernet@20000 {
+ compatible = "qcom,sm8150-ethqos";
+ reg = <0x0 0x00020000 0x0 0x10000>,
+ <0x0 0x00036000 0x0 0x100>;
+ reg-names = "stmmaceth", "rgmii";
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+ clocks = <&gcc GCC_EMAC_AXI_CLK>,
+ <&gcc GCC_EMAC_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC_PTP_CLK>,
+ <&gcc GCC_EMAC_RGMII_CLK>;
+ interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+
+ power-domains = <&gcc EMAC_GDSC>;
+ resets = <&gcc GCC_EMAC_BCR>;
+
+ iommus = <&apps_smmu 0x3C0 0x0>;
+
+ snps,tso;
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <4096>;
+
+ status = "disabled";
+ };
+
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
--
2.34.1
On Wed 26 Jan 16:17 CST 2022, Bhupesh Sharma wrote:
> From: Vinod Koul <[email protected]>
>
> This adds compatible, POR config & driver data for ethernet controller
> found in SM8150 SoC.
>
> Cc: David S. Miller <[email protected]>
> Signed-off-by: Vinod Koul <[email protected]>
> [bhsharma: Massage the commit log and other cosmetic changes]
> Signed-off-by: Bhupesh Sharma <[email protected]>
The series can be picked up by 3 different maintainers and e.g. the
network patches seems ready to be merged.
Please facilitate this by sending it in 3 different series (you may
combine clock and dts in one series, as I merge both).
Regards,
Bjorn
> ---
> .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index 2ffa0a11eea5..8cdba9d521ec 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -183,6 +183,20 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
> .num_por = ARRAY_SIZE(emac_v2_3_0_por),
> };
>
> +static const struct ethqos_emac_por emac_v2_1_0_por[] = {
> + { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
> + { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
> + { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
> + { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
> + { .offset = SDCC_USR_CTL, .value = 0x00010800 },
> + { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
> +};
> +
> +static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
> + .por = emac_v2_1_0_por,
> + .num_por = ARRAY_SIZE(emac_v2_1_0_por),
> +};
> +
> static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
> {
> unsigned int val;
> @@ -558,6 +572,7 @@ static int qcom_ethqos_remove(struct platform_device *pdev)
>
> static const struct of_device_id qcom_ethqos_match[] = {
> { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
> + { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
> --
> 2.34.1
>
Hi Bjorn,
Sorry for the late reply.
On Tue, 1 Feb 2022 at 05:37, Bjorn Andersson <[email protected]> wrote:
>
> On Wed 26 Jan 16:17 CST 2022, Bhupesh Sharma wrote:
>
> > From: Vinod Koul <[email protected]>
> >
> > This adds compatible, POR config & driver data for ethernet controller
> > found in SM8150 SoC.
> >
> > Cc: David S. Miller <[email protected]>
> > Signed-off-by: Vinod Koul <[email protected]>
> > [bhsharma: Massage the commit log and other cosmetic changes]
> > Signed-off-by: Bhupesh Sharma <[email protected]>
>
> The series can be picked up by 3 different maintainers and e.g. the
> network patches seems ready to be merged.
>
> Please facilitate this by sending it in 3 different series (you may
> combine clock and dts in one series, as I merge both).
Sure, I will send 3 different series in v2.
Regards,
Bhupesh
> > ---
> > .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> > index 2ffa0a11eea5..8cdba9d521ec 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> > @@ -183,6 +183,20 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
> > .num_por = ARRAY_SIZE(emac_v2_3_0_por),
> > };
> >
> > +static const struct ethqos_emac_por emac_v2_1_0_por[] = {
> > + { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
> > + { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
> > + { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
> > + { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
> > + { .offset = SDCC_USR_CTL, .value = 0x00010800 },
> > + { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
> > +};
> > +
> > +static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
> > + .por = emac_v2_1_0_por,
> > + .num_por = ARRAY_SIZE(emac_v2_1_0_por),
> > +};
> > +
> > static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
> > {
> > unsigned int val;
> > @@ -558,6 +572,7 @@ static int qcom_ethqos_remove(struct platform_device *pdev)
> >
> > static const struct of_device_id qcom_ethqos_match[] = {
> > { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
> > + { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
> > { }
> > };
> > MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
> > --
> > 2.34.1
> >