Hi,
Not tested on hardware, so please kindly test.
Bindings maintainers might need checking - taken from git log.
Changes since v1
================
1. Make freq-table as matrix of tuples (Nishanth).
2. New patches: convert all bindings and fix up DTS files.
3. Several minor fixes in UFS bindings.
Dependencies
============
1. The DTS patches (10-15) depend on scsi/ufs driver change (patch 9), so
they should go in a following release, after merging driver.
This is also might affect out-of-tree users of these DTSes (other
projects, e.g. U-boot).
Best regards,
Krzysztof
Krzysztof Kozlowski (15):
dt-bindings: ufs: add common platform bindings
dt-bindings: ufs: samsung,exynos-ufs: use common bindings
dt-bindings: ufs: cdns,ufshc: convert to dtschema
dt-bindings: ufs: drop unused/old ufs-qcom PHY bindings
dt-bindings: ufs: qcom,ufs: convert to dtschema
dt-bindings: ufs: hisilicon,ufs: convert to dtschema
dt-bindings: ufs: mediatek,ufs: convert to dtschema
dt-bindings: ufs: snps,tc-dwc-g210: convert to dtschema
scsi: ufs: deprecate 'freq-table-hz' property
arm64: dts: hi3670: use 'freq-table' in UFS node
arm64: dts: ti: use 'freq-table' in UFS node
arm64: dts: qcom: use 'freq-table' in UFS node
arm64: dts: qcom: msm8996: drop unsupported UFS
vddp-ref-clk-max-microamp
arm64: dts: qcom: msm8996: correct UFS compatible
arm64: dts: qcom: sm8350: drop duplicated ref_clk in UFS
.../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---
.../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++
.../bindings/ufs/hisilicon,ufs.yaml | 90 +++++++
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 67 +++++
.../devicetree/bindings/ufs/qcom,ufs.yaml | 241 ++++++++++++++++++
.../bindings/ufs/samsung,exynos-ufs.yaml | 13 +-
.../bindings/ufs/snps,tc-dwc-g210.yaml | 51 ++++
.../bindings/ufs/tc-dwc-g210-pltfrm.txt | 26 --
.../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 9 +-
.../devicetree/bindings/ufs/ufs-common.yaml | 88 +++++++
.../devicetree/bindings/ufs/ufs-hisi.txt | 42 ---
.../devicetree/bindings/ufs/ufs-mediatek.txt | 45 ----
.../devicetree/bindings/ufs/ufs-qcom.txt | 63 -----
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 90 -------
MAINTAINERS | 1 +
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 +-
.../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 -
arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 +-
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 +-
drivers/scsi/ufs/ufshcd-pltfrm.c | 21 +-
26 files changed, 641 insertions(+), 335 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/hisilicon,ufs.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
create mode 100644 Documentation/devicetree/bindings/ufs/snps,tc-dwc-g210.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-common.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-qcom.txt
delete mode 100644 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
--
2.32.0
The 'freq-table-hz' is not correct in DT schema, because '-hz' suffix
defines uint32 type, not an array. Therefore deprecate 'freq-table-hz'
and use 'freq-table' instead.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
drivers/scsi/ufs/ufshcd-pltfrm.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index 87975d1a21c8..2b192477d158 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -47,8 +47,9 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
if (cnt <= 0)
goto out;
- if (!of_get_property(np, "freq-table-hz", &len)) {
- dev_info(dev, "freq-table-hz property not specified\n");
+ if (!of_get_property(np, "freq-table", &len) ||
+ !of_get_property(np, "freq-table-hz", &len)) {
+ dev_info(dev, "freq-table property not specified\n");
goto out;
}
@@ -57,7 +58,7 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
sz = len / sizeof(*clkfreq);
if (sz != 2 * cnt) {
- dev_err(dev, "%s len mismatch\n", "freq-table-hz");
+ dev_err(dev, "%s len mismatch\n", "freq-table");
ret = -EINVAL;
goto out;
}
@@ -69,12 +70,16 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
goto out;
}
- ret = of_property_read_u32_array(np, "freq-table-hz",
+ ret = of_property_read_u32_array(np, "freq-table",
clkfreq, sz);
if (ret && (ret != -EINVAL)) {
- dev_err(dev, "%s: error reading array %d\n",
- "freq-table-hz", ret);
- return ret;
+ ret = of_property_read_u32_array(np, "freq-table-hz",
+ clkfreq, sz);
+ if (ret && (ret != -EINVAL)) {
+ dev_err(dev, "%s: error reading array %d\n",
+ "freq-table", ret);
+ return ret;
+ }
}
for (i = 0; i < sz; i += 2) {
@@ -99,7 +104,7 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
if (!strcmp(name, "ref_clk"))
clki->keep_link_active = true;
- dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
+ dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table",
clki->min_freq, clki->max_freq, clki->name);
list_add_tail(&clki->list, &hba->clk_list_head);
}
--
2.32.0
ref_clk clock in UFS node is already there with a <0 0> frequency, which
matches other DTSI files.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a26bd3f13d4a..cb6442c9e761 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1916,7 +1916,6 @@ ufs_mem_hc: ufshc@1d84000 {
iommus = <&apps_smmu 0xe0 0x0>;
clock-names =
- "ref_clk",
"core_clk",
"bus_aggr_clk",
"iface_clk",
@@ -1926,7 +1925,6 @@ ufs_mem_hc: ufshc@1d84000 {
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -1936,7 +1934,6 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table =
- <75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
--
2.32.0
The Qualcomm UFS bindings require to use specific (qcom,msm8996-ufshc)
and generic (jedec,ufs-2.0) compatibles.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index fad1bbfa1c0a..f25c68511b64 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1728,7 +1728,8 @@ pcie2: pcie@610000 {
};
ufshc: ufshc@624000 {
- compatible = "qcom,ufshc";
+ compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
--
2.32.0
The 'freq-table-hz' property is deprecated by UFS bindings.
The uint32-array requires also element to be passed within one <> block.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 636c8817df7e..754b3a66ec0d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -671,8 +671,8 @@ ufs: ufs@ff3c0000 {
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
--
2.32.0
Convert the Mediatek Universal Flash Storage (UFS) Controller to DT
schema format.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 67 +++++++++++++++++++
.../devicetree/bindings/ufs/ufs-mediatek.txt | 45 -------------
2 files changed, 67 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
new file mode 100644
index 000000000000..1cf530b5c57d
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Stanley Chu <[email protected]>
+
+allOf:
+ - $ref: ufs-common.yaml
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-ufshci
+ - mediatek,mt8192-ufshci
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ufs
+
+ phys:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ vcc-supply: true
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - phys
+ - reg
+ - vcc-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ufs@ff3c0000 {
+ compatible = "mediatek,mt8183-ufshci";
+ reg = <0 0x11270000 0 0x2300>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&ufsphy>;
+
+ clocks = <&infracfg_ao CLK_INFRA_UFS>;
+ clock-names = "ufs";
+ freq-table = <0 0>;
+
+ vcc-supply = <&mt_pmic_vemc_ldo_reg>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
deleted file mode 100644
index 63a953b672d2..000000000000
--- a/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-* Mediatek Universal Flash Storage (UFS) Host Controller
-
-UFS nodes are defined to describe on-chip UFS hardware macro.
-Each UFS Host Controller should have its own node.
-
-To bind UFS PHY with UFS host controller, the controller node should
-contain a phandle reference to UFS M-PHY node.
-
-Required properties for UFS nodes:
-- compatible : Compatible list, contains the following controller:
- "mediatek,mt8183-ufshci" for MediaTek UFS host controller
- present on MT8183 chipsets.
- "mediatek,mt8192-ufshci" for MediaTek UFS host controller
- present on MT8192 chipsets.
-- reg : Address and length of the UFS register set.
-- phys : phandle to m-phy.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. "ufs" is mandatory.
- "ufs": ufshci core control clock.
-- freq-table-hz : Array of <min max> operating frequencies stored in the same
- order as the clocks property. If this property is not
- defined or a value in the array is "0" then it is assumed
- that the frequency is set by the parent clock or a
- fixed rate clock source.
-- vcc-supply : phandle to VCC supply regulator node.
-
-Example:
-
- ufsphy: phy@11fa0000 {
- ...
- };
-
- ufshci@11270000 {
- compatible = "mediatek,mt8183-ufshci";
- reg = <0 0x11270000 0 0x2300>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
- phys = <&ufsphy>;
-
- clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>;
- clock-names = "ufs";
- freq-table-hz = <0 0>;
-
- vcc-supply = <&mt_pmic_vemc_ldo_reg>;
- };
--
2.32.0
The 'freq-table-hz' property is deprecated by UFS bindings.
The uint32-array requires also element to be passed within one <> block.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 599861259a30..34aff40c6b8e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1257,7 +1257,9 @@ ufs@4e84000 {
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
reg = <0x0 0x4e84000 0x0 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
+ freq-table = <250000000 250000000>,
+ <19200000 19200000>,
+ <19200000 19200000>;
clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
clock-names = "core_clk", "phy_clk", "ref_clk";
dma-coherent;
--
2.32.0
Convert the Cadence Universal Flash Storage (UFS) Controlle to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---------
.../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++++++++++++++++
.../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
3 files changed, 71 insertions(+), 36 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt b/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
deleted file mode 100644
index 02347b017abd..000000000000
--- a/Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* Cadence Universal Flash Storage (UFS) Controller
-
-UFS nodes are defined to describe on-chip UFS host controllers.
-Each UFS controller instance should have its own node.
-Please see the ufshcd-pltfrm.txt for a list of all available properties.
-
-Required properties:
-- compatible : Compatible list, contains one of the following controllers:
- "cdns,ufshc" - Generic CDNS HCI,
- "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY
- complemented with the JEDEC version:
- "jedec,ufs-2.0"
-
-- reg : Address and length of the UFS register set.
-- interrupts : One interrupt mapping.
-- freq-table-hz : Clock frequency table.
- See the ufshcd-pltfrm.txt for details.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property. "core_clk" is mandatory.
- Depending on a type of a PHY,
- the "phy_clk" clock can also be added, if needed.
-
-Example:
- ufs@fd030000 {
- compatible = "cdns,ufshc", "jedec,ufs-2.0";
- reg = <0xfd030000 0x10000>;
- interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
- freq-table-hz = <0 0>, <0 0>;
- clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
- clock-names = "core_clk", "phy_clk";
- };
diff --git a/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml b/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
new file mode 100644
index 000000000000..59588914ec76
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Jan Kotas <[email protected]>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - cdns,ufshc
+ - cdns,ufshc-m31-16nm
+ required:
+ - compatible
+
+allOf:
+ - $ref: ufs-common.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - cdns,ufshc
+ # CDNS UFS HC + M31 16nm PHY
+ - cdns,ufshc-m31-16nm
+ - const: jedec,ufs-2.0
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core_clk
+ - const: phy_clk
+ - const: ref_clk
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ufs@fd030000 {
+ compatible = "cdns,ufshc", "jedec,ufs-2.0";
+ reg = <0xfd030000 0x10000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ freq-table = <0 0>, <0 0>;
+ clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
+ clock-names = "core_clk", "phy_clk";
+ };
diff --git a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
index dc93fe2d3458..6cb0001e6a58 100644
--- a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
@@ -47,11 +47,10 @@ required:
patternProperties:
"^ufs@[0-9a-f]+$":
- type: object
+ $ref: cdns,ufshc.yaml
description: |
- Cadence UFS controller node must be the child node. Refer
- Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding
- documentation of child node
+ Cadence UFS controller node must be the child node.
+ unevaluatedProperties: false
additionalProperties: false
--
2.32.0
The 'freq-table-hz' property is deprecated by UFS bindings.
The uint32-array requires also element to be passed within one <> block.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c85825ea1623..fad1bbfa1c0a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1761,7 +1761,7 @@ ufshc: ufshc@624000 {
<&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
- freq-table-hz =
+ freq-table =
<100000000 200000000>,
<0 0>,
<0 0>,
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 2fda21e810c9..87336c5866c0 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -990,7 +990,7 @@ ufshc: ufshc@1da4000 {
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
- freq-table-hz =
+ freq-table =
<50000000 200000000>,
<0 0>,
<0 0>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0d6286d27dd4..23caa29e7862 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2274,7 +2274,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
- freq-table-hz =
+ freq-table =
<50000000 200000000>,
<0 0>,
<0 0>,
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index d15fee495238..db2ac197c630 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1782,7 +1782,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
- freq-table-hz =
+ freq-table =
<37500000 300000000>,
<0 0>,
<0 0>,
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index fdaf303ba047..8c9e3c4ac5ac 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2133,7 +2133,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
+ freq-table =
<37500000 300000000>,
<0 0>,
<0 0>,
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index d242bab69c2e..a26bd3f13d4a 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1935,7 +1935,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
+ freq-table =
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 934e29b9e153..edb904b58c0c 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1398,7 +1398,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
+ freq-table =
<75000000 300000000>,
<0 0>,
<0 0>,
--
2.32.0
Use common UFS bindings in Samsung Exynos UFS to cover generic/common
properties in DTS.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index 95ac1c18334d..c949eb617313 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -11,12 +11,11 @@ maintainers:
description: |
Each Samsung UFS host controller instance should have its own node.
- This binding define Samsung specific binding other then what is used
- in the common ufshcd bindings
- [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
-properties:
+allOf:
+ - $ref: ufs-common.yaml
+properties:
compatible:
enum:
- samsung,exynos7-ufs
@@ -47,9 +46,6 @@ properties:
- const: core_clk
- const: sclk_unipro_main
- interrupts:
- maxItems: 1
-
phys:
maxItems: 1
@@ -67,13 +63,12 @@ properties:
required:
- compatible
- reg
- - interrupts
- phys
- phy-names
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
--
2.32.0
Hi Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Tuesday, February 22, 2022 8:29 PM
>To: Alim Akhtar <[email protected]>; Avri Altman
><[email protected]>; Rob Herring <[email protected]>; Krzysztof
>Kozlowski <[email protected]>; Andy Gross
><[email protected]>; Bjorn Andersson <[email protected]>; Wei
>Xu <[email protected]>; Nishanth Menon <[email protected]>; Vignesh
>Raghavendra <[email protected]>; Tero Kristo <[email protected]>; James E.J.
>Bottomley <[email protected]>; Martin K. Petersen
><[email protected]>; Jan Kotas <[email protected]>; Li Wei
><[email protected]>; Stanley Chu <[email protected]>; Yaniv
>Gardi <[email protected]>; [email protected];
>[email protected]; [email protected]; linux-arm-
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]
>Subject: [PATCH v2 09/15] scsi: ufs: deprecate 'freq-table-hz' property
>
>The 'freq-table-hz' is not correct in DT schema, because '-hz' suffix
defines
>uint32 type, not an array. Therefore deprecate 'freq-table-hz'
>and use 'freq-table' instead.
>
May be once all the dts change migrate to using 'freq-table', just remove
'freq-table-hz' from driver.
>Signed-off-by: Krzysztof Kozlowski <[email protected]>
>---
> drivers/scsi/ufs/ufshcd-pltfrm.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c
b/drivers/scsi/ufs/ufshcd-pltfrm.c
>index 87975d1a21c8..2b192477d158 100644
>--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
>+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
>@@ -47,8 +47,9 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
> if (cnt <= 0)
> goto out;
>
>- if (!of_get_property(np, "freq-table-hz", &len)) {
>- dev_info(dev, "freq-table-hz property not specified\n");
>+ if (!of_get_property(np, "freq-table", &len) ||
>+ !of_get_property(np, "freq-table-hz", &len)) {
>+ dev_info(dev, "freq-table property not specified\n");
> goto out;
> }
>
>@@ -57,7 +58,7 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
>
> sz = len / sizeof(*clkfreq);
> if (sz != 2 * cnt) {
>- dev_err(dev, "%s len mismatch\n", "freq-table-hz");
>+ dev_err(dev, "%s len mismatch\n", "freq-table");
> ret = -EINVAL;
> goto out;
> }
>@@ -69,12 +70,16 @@ static int ufshcd_parse_clock_info(struct ufs_hba
>*hba)
> goto out;
> }
>
>- ret = of_property_read_u32_array(np, "freq-table-hz",
>+ ret = of_property_read_u32_array(np, "freq-table",
> clkfreq, sz);
> if (ret && (ret != -EINVAL)) {
>- dev_err(dev, "%s: error reading array %d\n",
>- "freq-table-hz", ret);
>- return ret;
>+ ret = of_property_read_u32_array(np, "freq-table-hz",
>+ clkfreq, sz);
>+ if (ret && (ret != -EINVAL)) {
>+ dev_err(dev, "%s: error reading array %d\n",
>+ "freq-table", ret);
>+ return ret;
>+ }
> }
>
> for (i = 0; i < sz; i += 2) {
>@@ -99,7 +104,7 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
>
> if (!strcmp(name, "ref_clk"))
> clki->keep_link_active = true;
>- dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-
>hz",
>+ dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table",
> clki->min_freq, clki->max_freq, clki->name);
> list_add_tail(&clki->list, &hba->clk_list_head);
> }
>--
>2.32.0
On Tue 22 Feb 06:58 PST 2022, Krzysztof Kozlowski wrote:
> The 'freq-table-hz' is not correct in DT schema, because '-hz' suffix
> defines uint32 type, not an array. Therefore deprecate 'freq-table-hz'
> and use 'freq-table' instead.
>
Patch looks good in itself, but why don't we use opp-table to describe
the performance states?
In particular looking at the two columns of frequencies for various
Qualcomm boards they require different performance-states.
A concrete example is sm8350.dtsi, which specifies 75MHz and 300MHz as
the first frequency pair. The lower level requires the VDD_CX power rail
to be at least &rpmhpd_opp_low_svs, the higher frequency has a
required-opps of &rpmhpd_opp_nom.
As this isn't possible to express in the current binding we've just been
forced to always run at a higher voltage level and kept this in the todo
list.
But rather than migrating freq-table-hz to freq-table and then having to
introduce an opp table to express the power constraints, could we
perhaps skip the intermediate step?
Or would you have any other suggestion about how we can represent the
required-opps level together with the freq-table (if that's what we want
to stick with).
Regards,
Bjorn
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> drivers/scsi/ufs/ufshcd-pltfrm.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
> index 87975d1a21c8..2b192477d158 100644
> --- a/drivers/scsi/ufs/ufshcd-pltfrm.c
> +++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
> @@ -47,8 +47,9 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
> if (cnt <= 0)
> goto out;
>
> - if (!of_get_property(np, "freq-table-hz", &len)) {
> - dev_info(dev, "freq-table-hz property not specified\n");
> + if (!of_get_property(np, "freq-table", &len) ||
> + !of_get_property(np, "freq-table-hz", &len)) {
> + dev_info(dev, "freq-table property not specified\n");
> goto out;
> }
>
> @@ -57,7 +58,7 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
>
> sz = len / sizeof(*clkfreq);
> if (sz != 2 * cnt) {
> - dev_err(dev, "%s len mismatch\n", "freq-table-hz");
> + dev_err(dev, "%s len mismatch\n", "freq-table");
> ret = -EINVAL;
> goto out;
> }
> @@ -69,12 +70,16 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
> goto out;
> }
>
> - ret = of_property_read_u32_array(np, "freq-table-hz",
> + ret = of_property_read_u32_array(np, "freq-table",
> clkfreq, sz);
> if (ret && (ret != -EINVAL)) {
> - dev_err(dev, "%s: error reading array %d\n",
> - "freq-table-hz", ret);
> - return ret;
> + ret = of_property_read_u32_array(np, "freq-table-hz",
> + clkfreq, sz);
> + if (ret && (ret != -EINVAL)) {
> + dev_err(dev, "%s: error reading array %d\n",
> + "freq-table", ret);
> + return ret;
> + }
> }
>
> for (i = 0; i < sz; i += 2) {
> @@ -99,7 +104,7 @@ static int ufshcd_parse_clock_info(struct ufs_hba *hba)
>
> if (!strcmp(name, "ref_clk"))
> clki->keep_link_active = true;
> - dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
> + dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table",
> clki->min_freq, clki->max_freq, clki->name);
> list_add_tail(&clki->list, &hba->clk_list_head);
> }
> --
> 2.32.0
>
On 22/02/2022 17:44, Alim Akhtar wrote:
> Hi Krzysztof
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: Tuesday, February 22, 2022 8:29 PM
>> To: Alim Akhtar <[email protected]>; Avri Altman
>> <[email protected]>; Rob Herring <[email protected]>; Krzysztof
>> Kozlowski <[email protected]>; Andy Gross
>> <[email protected]>; Bjorn Andersson <[email protected]>; Wei
>> Xu <[email protected]>; Nishanth Menon <[email protected]>; Vignesh
>> Raghavendra <[email protected]>; Tero Kristo <[email protected]>; James E.J.
>> Bottomley <[email protected]>; Martin K. Petersen
>> <[email protected]>; Jan Kotas <[email protected]>; Li Wei
>> <[email protected]>; Stanley Chu <[email protected]>; Yaniv
>> Gardi <[email protected]>; [email protected];
>> [email protected]; [email protected]; linux-arm-
>> [email protected]; [email protected]; linux-samsung-
>> [email protected]; [email protected]
>> Subject: [PATCH v2 09/15] scsi: ufs: deprecate 'freq-table-hz' property
>>
>> The 'freq-table-hz' is not correct in DT schema, because '-hz' suffix
> defines
>> uint32 type, not an array. Therefore deprecate 'freq-table-hz'
>> and use 'freq-table' instead.
>>
> May be once all the dts change migrate to using 'freq-table', just remove
> 'freq-table-hz' from driver.
At some point in the future 'freq-table-hz' parsing could be removed,
but now you have both old and new DTS, so it should stay. Also for DTB
compatibility.
Best regards,
Krzysztof
Convert the Qualcomm Universal Flash Storage (UFS) Controller to DT
schema format.
Except the conversion, add also properties already present in DTS:
iommus, interconnects and power-domains.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/ufs/qcom,ufs.yaml | 241 ++++++++++++++++++
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 90 -------
2 files changed, 241 insertions(+), 90 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
delete mode 100644 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
new file mode 100644
index 000000000000..356217124222
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Yaniv Gardi <[email protected]>
+
+# Select only our matches, not all jedec,ufs-2.0
+select:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ufshc
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,msm8994-ufshc
+ - qcom,msm8996-ufshc
+ - qcom,msm8998-ufshc
+ - qcom,sdm845-ufshc
+ - qcom,sm8150-ufshc
+ - qcom,sm8250-ufshc
+ - qcom,sm8350-ufshc
+ - qcom,sm8450-ufshc
+ - const: qcom,ufshc
+ - const: jedec,ufs-2.0
+
+ clocks:
+ minItems: 8
+ maxItems: 11
+
+ clock-names:
+ minItems: 8
+ maxItems: 11
+
+ interconnects:
+ minItems: 2
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ufs-ddr
+ - const: cpu-ufs
+
+ iommus:
+ minItems: 1
+ maxItems: 2
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: ufsphy
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+ reset-names:
+ items:
+ - const: rst
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ GPIO connected to the RESET pin of the UFS memory device.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: ufs-common.yaml
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-ufshc
+ - qcom,sm8250-ufshc
+ - qcom,sm8350-ufshc
+ - qcom,sm8450-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ - const: rx_lane1_sync_clk
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-ufshc
+ - qcom,sm8150-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 9
+ maxItems: 9
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ - const: rx_lane1_sync_clk
+ - const: ice_core_clk
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 11
+ maxItems: 11
+ clock-names:
+ items:
+ - const: core_clk_src
+ - const: core_clk
+ - const: bus_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro_src
+ - const: core_clk_unipro
+ - const: core_clk_ice
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ # TODO: define clock bindings for qcom,msm8994-ufshc
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8450.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ufs@1d84000 {
+ compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy_lanes>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b_2p5>;
+ vcc-max-microamp = <1100000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ iommus = <&apps_smmu 0xe0 0x0>;
+ interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table = <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
deleted file mode 100644
index d0fee78e6203..000000000000
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-* Universal Flash Storage (UFS) Host Controller
-
-UFSHC nodes are defined to describe on-chip UFS host controllers.
-Each UFS controller instance should have its own node.
-
-Required properties:
-- compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
-
- For Qualcomm SoCs must contain, as below, an
- SoC-specific compatible along with "qcom,ufshc" and
- the appropriate jedec string:
- "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
-- interrupts : <interrupt mapping for UFS host controller IRQ>
-- reg : <registers mapping>
-
-Optional properties:
-- phys : phandle to UFS PHY node
-- phy-names : the string "ufsphy" when is found in a node, along
- with "phys" attribute, provides phandle to UFS PHY node
-- vdd-hba-supply : phandle to UFS host controller supply regulator node
-- vcc-supply : phandle to VCC supply regulator node
-- vccq-supply : phandle to VCCQ supply regulator node
-- vccq2-supply : phandle to VCCQ2 supply regulator node
-- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
- or 2.7-3.6V. This boolean property when set, specifies
- to use low voltage range of 1.7-1.95V. Note for external
- UFS cards this property is invalid and valid VCC range is
- always 2.7-3.6V.
-- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
-- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
-- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
-
-- clocks : List of phandle and clock specifier pairs
-- clock-names : List of clock input name strings sorted in the same
- order as the clocks property.
- "ref_clk" indicates reference clock frequency.
- UFS host supplies reference clock to UFS device and UFS device
- specification allows host to provide one of the 4 frequencies (19.2 MHz,
- 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
- parsed and used to update the reference clock setting in device.
- Defaults to 26 MHz(as per specification) if not specified by host.
-- freq-table-hz : Array of <min max> operating frequencies stored in the same
- order as the clocks property. If this property is not
- defined or a value in the array is "0" then it is assumed
- that the frequency is set by the parent clock or a
- fixed rate clock source.
--lanes-per-direction : number of lanes available per direction - either 1 or 2.
- Note that it is assume same number of lanes is used both
- directions at once. If not specified, default is 2 lanes per direction.
-- #reset-cells : Must be <1> for Qualcomm UFS controllers that expose
- PHY reset from the UFS controller.
-- resets : reset node register
-- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
-- reset-gpios : A phandle and gpio specifier denoting the GPIO connected
- to the RESET pin of the UFS memory device.
-
-Note: If above properties are not defined it can be assumed that the supply
-regulators or clocks are always on.
-
-Example:
- ufshc@fc598000 {
- compatible = "jedec,ufs-1.1";
- reg = <0xfc598000 0x800>;
- interrupts = <0 28 0>;
-
- vdd-hba-supply = <&xxx_reg0>;
- vcc-supply = <&xxx_reg1>;
- vcc-supply-1p8;
- vccq-supply = <&xxx_reg2>;
- vccq2-supply = <&xxx_reg3>;
- vcc-max-microamp = 500000;
- vccq-max-microamp = 200000;
- vccq2-max-microamp = 200000;
-
- clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
- clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
- freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
- resets = <&reset 0 1>;
- reset-names = "rst";
- phys = <&ufsphy1>;
- phy-names = "ufsphy";
- #reset-cells = <1>;
- };
--
2.32.0
On 22/02/2022 19:16, Bjorn Andersson wrote:
> On Tue 22 Feb 06:58 PST 2022, Krzysztof Kozlowski wrote:
>
>> The 'freq-table-hz' is not correct in DT schema, because '-hz' suffix
>> defines uint32 type, not an array. Therefore deprecate 'freq-table-hz'
>> and use 'freq-table' instead.
>>
>
> Patch looks good in itself, but why don't we use opp-table to describe
> the performance states?
>
> In particular looking at the two columns of frequencies for various
> Qualcomm boards they require different performance-states.
>
> A concrete example is sm8350.dtsi, which specifies 75MHz and 300MHz as
> the first frequency pair. The lower level requires the VDD_CX power rail
> to be at least &rpmhpd_opp_low_svs, the higher frequency has a
> required-opps of &rpmhpd_opp_nom.
>
>
> As this isn't possible to express in the current binding we've just been
> forced to always run at a higher voltage level and kept this in the todo
> list.
>
> But rather than migrating freq-table-hz to freq-table and then having to
> introduce an opp table to express the power constraints, could we
> perhaps skip the intermediate step?
>
> Or would you have any other suggestion about how we can represent the
> required-opps level together with the freq-table (if that's what we want
> to stick with).
Usage of OPP tables is interesting solution. It would solve your problem
of power rail levels. This would need several opp-tables - one for each
clock, which is not a big problem.
The problem is that I do not have any UFS hardware (none of my Samsung
Exynos boards have UFS... I don't have even arm64 Exynos chips :( ), so
implementing it theoretically will be painful.
OTOH, I believe that having a working dtschema is very useful. Having
dtschema without errors/warnings is even worth some churn/intermediary work.
The intermediary work is also not that big. Once proper OPP is
implemented, we will have "just" two deprecated properties in the bindings.
Best regards,
Krzysztof
On Wed 23 Feb 03:15 CST 2022, Krzysztof Kozlowski wrote:
> On 22/02/2022 19:16, Bjorn Andersson wrote:
> > On Tue 22 Feb 06:58 PST 2022, Krzysztof Kozlowski wrote:
> >
> >> The 'freq-table-hz' is not correct in DT schema, because '-hz' suffix
> >> defines uint32 type, not an array. Therefore deprecate 'freq-table-hz'
> >> and use 'freq-table' instead.
> >>
> >
> > Patch looks good in itself, but why don't we use opp-table to describe
> > the performance states?
> >
> > In particular looking at the two columns of frequencies for various
> > Qualcomm boards they require different performance-states.
> >
> > A concrete example is sm8350.dtsi, which specifies 75MHz and 300MHz as
> > the first frequency pair. The lower level requires the VDD_CX power rail
> > to be at least &rpmhpd_opp_low_svs, the higher frequency has a
> > required-opps of &rpmhpd_opp_nom.
> >
> >
> > As this isn't possible to express in the current binding we've just been
> > forced to always run at a higher voltage level and kept this in the todo
> > list.
> >
> > But rather than migrating freq-table-hz to freq-table and then having to
> > introduce an opp table to express the power constraints, could we
> > perhaps skip the intermediate step?
> >
> > Or would you have any other suggestion about how we can represent the
> > required-opps level together with the freq-table (if that's what we want
> > to stick with).
>
> Usage of OPP tables is interesting solution. It would solve your problem
> of power rail levels. This would need several opp-tables - one for each
> clock, which is not a big problem.
>
Ahh, so we can only have a single clock, but multiple regulators and
interconnect paths tied to the opp table.
We have a couple of cases where it would have been nice to be able to
key the opp-table off some index (e.g. the UFS gear or PCI Gen) and
control multiple clocks. So I think we need to look into this further...
> The problem is that I do not have any UFS hardware (none of my Samsung
> Exynos boards have UFS... I don't have even arm64 Exynos chips :( ), so
> implementing it theoretically will be painful.
> OTOH, I believe that having a working dtschema is very useful. Having
> dtschema without errors/warnings is even worth some churn/intermediary work.
>
> The intermediary work is also not that big. Once proper OPP is
> implemented, we will have "just" two deprecated properties in the bindings.
>
Fair enough, was just hoping to avoid the middle step. But that's fine,
we'll continue to carry this on our todo list then.
Thanks,
Bjorn
On Tue, 22 Feb 2022 15:58:44 +0100, Krzysztof Kozlowski wrote:
> Convert the Qualcomm Universal Flash Storage (UFS) Controller to DT
> schema format.
>
> Except the conversion, add also properties already present in DTS:
> iommus, interconnects and power-domains.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 241 ++++++++++++++++++
> .../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 90 -------
> 2 files changed, 241 insertions(+), 90 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> delete mode 100644 Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, 22 Feb 2022 15:58:41 +0100, Krzysztof Kozlowski wrote:
> Use common UFS bindings in Samsung Exynos UFS to cover generic/common
> properties in DTS.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, 22 Feb 2022 15:58:42 +0100, Krzysztof Kozlowski wrote:
> Convert the Cadence Universal Flash Storage (UFS) Controlle to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/ufs/cdns,ufshc.txt | 32 ---------
> .../devicetree/bindings/ufs/cdns,ufshc.yaml | 68 +++++++++++++++++++
> .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 7 +-
> 3 files changed, 71 insertions(+), 36 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.txt
> create mode 100644 Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, 22 Feb 2022 15:58:46 +0100, Krzysztof Kozlowski wrote:
> Convert the Mediatek Universal Flash Storage (UFS) Controller to DT
> schema format.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/ufs/mediatek,ufs.yaml | 67 +++++++++++++++++++
> .../devicetree/bindings/ufs/ufs-mediatek.txt | 45 -------------
> 2 files changed, 67 insertions(+), 45 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> delete mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
>
Reviewed-by: Rob Herring <[email protected]>