Changes since v1:
-----------------
- v1 can be found here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Collect ACK from Rob on PATCH 1/4.
- Address review comments from Maulik.
This patchset adds the support for PDC interrupt controller found
on sm8150 SoCs from Qualcomm.
Here we add the device-tree bindings, pinctrl driver support
and the dts support for the same.
Cc: Maulik Shah <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Linus Walleij <[email protected]>
Bhupesh Sharma (4):
dt-bindings: qcom,pdc: Add compatible for SM8150
pinctrl: qcom: sm8150: Specify PDC map
arm64: dts: qcom: sm8150: Add pdc interrupt controller node
arm64: dts: qcom: sm8150: Add PDC as the interrupt parent for tlmm
.../interrupt-controller/qcom,pdc.txt | 1 +
arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 ++++++++++
drivers/pinctrl/qcom/pinctrl-sm8150.c | 22 +++++++++++++++++++
3 files changed, 34 insertions(+)
--
2.35.1
Add pdc interrupt controller for sm8150.
Cc: Maulik Shah <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 6012322a5984..aaeacd379460 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm8150-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x400>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.35.1
On 27-02-22, 00:10, Bhupesh Sharma wrote:
> Changes since v1:
> -----------------
> - v1 can be found here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - Collect ACK from Rob on PATCH 1/4.
> - Address review comments from Maulik.
>
> This patchset adds the support for PDC interrupt controller found
> on sm8150 SoCs from Qualcomm.
>
> Here we add the device-tree bindings, pinctrl driver support
> and the dts support for the same.
Reviewed-by: Vinod Koul <[email protected]>
--
~Vinod
On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote:
> Add pdc interrupt controller for sm8150.
>
> Cc: Maulik Shah <[email protected]>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 6012322a5984..aaeacd379460 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> + reg = <0 0x0b220000 0 0x400>;
> + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> + <125 63 1>;
When I look at the platform documentation I get the impression that this
should be: <0 480 94>, <94 609 32>;
Can you confirm that the last signal is correctly described?
Regards,
Bjorn
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> --
> 2.35.1
>
On Sat, Feb 26, 2022 at 7:40 PM Bhupesh Sharma
<[email protected]> wrote:
> Changes since v1:
> -----------------
> - v1 can be found here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - Collect ACK from Rob on PATCH 1/4.
> - Address review comments from Maulik.
Looks good to me, but I need Bjorns ACK before merging this.
Yours,
Linus Walleij
Hi Bjorn,
Thanks for your review.
On Tue, 15 Mar 2022 at 21:48, Bjorn Andersson
<[email protected]> wrote:
>
> On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote:
>
> > Add pdc interrupt controller for sm8150.
> >
> > Cc: Maulik Shah <[email protected]>
> > Cc: Bjorn Andersson <[email protected]>
> > Cc: Vinod Koul <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Signed-off-by: Bhupesh Sharma <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > index 6012322a5984..aaeacd379460 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + pdc: interrupt-controller@b220000 {
> > + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> > + reg = <0 0x0b220000 0 0x400>;
> > + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> > + <125 63 1>;
>
> When I look at the platform documentation I get the impression that this
> should be: <0 480 94>, <94 609 32>;
>
> Can you confirm that the last signal is correctly described?
Yes, I confirmed by double checking the entries in downstream 'pdc-sm8150.c'.
The pdc pins in the 2nd range start from 94 and end at 124, so a total
of 31 entries, but both 94 and 124 pins included.
Or, am I missing something?
Thanks,
Bhupesh
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&intc>;
> > + interrupt-controller;
> > + };
> > +
> > ufs_mem_hc: ufshc@1d84000 {
> > compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> > "jedec,ufs-2.0";
> > --
> > 2.35.1
> >
On Wed 16 Mar 22:51 PDT 2022, Bhupesh Sharma wrote:
> Hi Bjorn,
>
> Thanks for your review.
>
> On Tue, 15 Mar 2022 at 21:48, Bjorn Andersson
> <[email protected]> wrote:
> >
> > On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote:
> >
> > > Add pdc interrupt controller for sm8150.
> > >
> > > Cc: Maulik Shah <[email protected]>
> > > Cc: Bjorn Andersson <[email protected]>
> > > Cc: Vinod Koul <[email protected]>
> > > Cc: Rob Herring <[email protected]>
> > > Signed-off-by: Bhupesh Sharma <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > index 6012322a5984..aaeacd379460 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> > > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> > > };
> > >
> > > + pdc: interrupt-controller@b220000 {
> > > + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> > > + reg = <0 0x0b220000 0 0x400>;
> > > + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> > > + <125 63 1>;
> >
> > When I look at the platform documentation I get the impression that this
> > should be: <0 480 94>, <94 609 32>;
> >
> > Can you confirm that the last signal is correctly described?
>
> Yes, I confirmed by double checking the entries in downstream 'pdc-sm8150.c'.
> The pdc pins in the 2nd range start from 94 and end at 124, so a total
> of 31 entries, but both 94 and 124 pins included.
>
> Or, am I missing something?
>
Thanks for double checking, let's follow the downstream kernel.
I will merge the patch as you proposed it.
Thanks,
Bjorn
> Thanks,
> Bhupesh
>
> > > + #interrupt-cells = <2>;
> > > + interrupt-parent = <&intc>;
> > > + interrupt-controller;
> > > + };
> > > +
> > > ufs_mem_hc: ufshc@1d84000 {
> > > compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> > > "jedec,ufs-2.0";
> > > --
> > > 2.35.1
> > >