2022-04-23 14:01:08

by Vidya Sagar

Subject: [PATCH V2 1/8] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block

Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
module instantiated once for each PCIe lane between Synopsys DesignWare
core based PCIe IP and Universal PHY block.

Signed-off-by: Vidya Sagar <[email protected]>
---
V2:
* Addressed review comments from Rob and Raul
* Ran 'dt_binding_check' and 'dtbs_check' on this change

.../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
index 9a89d05efbda..4dc5205d893b 100644
--- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
@@ -4,7 +4,7 @@
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

-title: NVIDIA Tegra194 P2U binding
+title: NVIDIA Tegra194 & Tegra234 P2U binding

maintainers:
- Thierry Reding <[email protected]>
@@ -12,13 +12,17 @@ maintainers:
description: >
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
Speed) each interfacing with 12 and 8 P2U instances respectively.
+ Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
+ each interfacing with 8, 8 and 8 P2U instances respectively.
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
- interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
- lane.
+ interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
+ PCIe lane.

properties:
compatible:
- const: nvidia,tegra194-p2u
+ enum:
+ - nvidia,tegra194-p2u
+ - nvidia,tegra234-p2u

reg:
maxItems: 1
@@ -28,6 +32,11 @@ properties:
items:
- const: ctl

+ nvidia,skip-sz-protect-en:
+ description: Should be present if two PCIe retimers are present between
+ the root port and its immediate downstream device.
+ type: boolean
+
'#phy-cells':
const: 0

--
2.17.1

2022-05-03 01:25:04

by Rob Herring (Arm)

Subject: Re: [PATCH V2 1/8] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block

On Sat, 23 Apr 2022 18:18:51 +0530, Vidya Sagar wrote:
> Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
> module instantiated once for each PCIe lane between Synopsys DesignWare
> core based PCIe IP and Universal PHY block.
>
> Signed-off-by: Vidya Sagar <[email protected]>
> ---
> V2:
> * Addressed review comments from Rob and Raul
> * Ran 'dt_binding_check' and 'dtbs_check' on this change
>
> .../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>

Reviewed-by: Rob Herring <[email protected]>