2022-05-03 14:40:23

by Robert Foss

Subject: [PATCH v2 8/8] arm64: dts: qcom: sm8350: Add DISPCC node

Add the dispcc clock-controller DT node for sm8350.

Signed-off-by: Robert Foss <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 52428b6df64e..94c2519e9f48 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,7 +3,9 @@
* Copyright (c) 2020, Linaro Limited
*/

+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -2525,6 +2527,31 @@ usb_2_dwc3: usb@a800000 {
};
};

+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8350-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ power-domains = <&rpmhpd SM8350_MMCX>;
+ power-domain-names = "mmcx";
+ };
+
adsp: remoteproc@17300000 {
compatible = "qcom,sm8350-adsp-pas";
reg = <0 0x17300000 0 0x100>;
--
2.34.1

2022-05-04 02:16:01

by Bjorn Andersson

Subject: Re: [PATCH v2 8/8] arm64: dts: qcom: sm8350: Add DISPCC node

On Tue 03 May 08:04 CDT 2022, Robert Foss wrote:

> Add the dispcc clock-controller DT node for sm8350.
>
> Signed-off-by: Robert Foss <[email protected]>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 52428b6df64e..94c2519e9f48 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,7 +3,9 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include <dt-bindings/interconnect/qcom,sm8350.h>

This looks unrelated.

Rest looks good.

Regards,
Bjorn

> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
> #include <dt-bindings/clock/qcom,gcc-sm8350.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> @@ -2525,6 +2527,31 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + dispcc: clock-controller@af00000 {
> + compatible = "qcom,sm8350-dispcc";
> + reg = <0 0x0af00000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>,
> + <0>;
> + clock-names = "bi_tcxo",
> + "dsi0_phy_pll_out_byteclk",
> + "dsi0_phy_pll_out_dsiclk",
> + "dsi1_phy_pll_out_byteclk",
> + "dsi1_phy_pll_out_dsiclk",
> + "dp_phy_pll_link_clk",
> + "dp_phy_pll_vco_div_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> +
> + power-domains = <&rpmhpd SM8350_MMCX>;
> + power-domain-names = "mmcx";
> + };
> +
> adsp: remoteproc@17300000 {
> compatible = "qcom,sm8350-adsp-pas";
> reg = <0 0x17300000 0 0x100>;
> --
> 2.34.1
>