From: Wei Fang <[email protected]>
Add the fec node on i.MX8ULP platfroms.
And enable the fec support on i.MX8ULP EVK boards.
Wei Fang (3):
dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items
arm64: dts: imx8ulp: Add the fec support
arm64: dts: imx8ulp-evk: Add the fec support
.../devicetree/bindings/net/fsl,fec.yaml | 5 ++
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 11 ++++
3 files changed, 73 insertions(+)
--
2.25.1
From: Wei Fang <[email protected]>
Add the fec support on i.MX8ULP platforms.
Signed-off-by: Wei Fang <[email protected]>
---
V2 change:
Remove the external clocks which is related to specific board.
V3 change:
No change.
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 60c1b018bf03..3e8a1e4f0fc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -16,6 +16,7 @@ / {
#size-cells = <2>;
aliases {
+ ethernet0 = &fec;
gpio0 = &gpiod;
gpio1 = &gpioe;
gpio2 = &gpiof;
@@ -365,6 +366,16 @@ usdhc2: mmc@298f0000 {
bus-width = <4>;
status = "disabled";
};
+
+ fec: ethernet@29950000 {
+ compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
+ reg = <0x29950000 0x10000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0";
+ fsl,num-tx-queues = <1>;
+ fsl,num-rx-queues = <1>;
+ status = "disabled";
+ };
};
gpioe: gpio@2d000080 {
--
2.25.1
From: Wei Fang <[email protected]>
Enable the fec on i.MX8ULP EVK board.
Signed-off-by: Wei Fang <[email protected]>
---
V2 change:
Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
V3 change:
No change.
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 33e84c4e9ed8..ebce716b10e6 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -19,6 +19,21 @@ memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
+
+ clock_ext_rmii: clock-ext-rmii {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "ext_rmii_clk";
+ #clock-cells = <0>;
+ };
+
+ clock_ext_ts: clock-ext-ts {
+ compatible = "fixed-clock";
+ /* External ts clock is 50MHZ from PHY on EVK board. */
+ clock-frequency = <50000000>;
+ clock-output-names = "ext_ts_clk";
+ #clock-cells = <0>;
+ };
};
&lpuart5 {
@@ -38,7 +53,49 @@ &usdhc0 {
status = "okay";
};
+&fec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_enet>;
+ pinctrl-1 = <&pinctrl_enet>;
+ clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+ <&pcc4 IMX8ULP_CLK_ENET>,
+ <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
+ <&clock_ext_rmii>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
+ assigned-clock-parents = <&clock_ext_ts>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
&iomuxc1 {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8ULP_PAD_PTE15__ENET0_MDC 0x43
+ MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
+ MX8ULP_PAD_PTE17__ENET0_RXER 0x43
+ MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
+ MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
+ MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
+ MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
+ MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
+ MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
+ MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
+ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+ >;
+ };
+
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
--
2.25.1
From: Wei Fang <[email protected]>
Add fsl,imx8ulp-fec for i.MX8ULP platform.
Signed-off-by: Wei Fang <[email protected]>
---
V2 change:
Add fsl,imx6q-fec
V3 change:
No change.
---
Documentation/devicetree/bindings/net/fsl,fec.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml
index daa2f79a294f..4d2454ade3b6 100644
--- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
@@ -58,6 +58,11 @@ properties:
- fsl,imx8qxp-fec
- const: fsl,imx8qm-fec
- const: fsl,imx6sx-fec
+ - items:
+ - enum:
+ - fsl,imx8ulp-fec
+ - const: fsl,imx6ul-fec
+ - const: fsl,imx6q-fec
reg:
maxItems: 1
--
2.25.1
On 18.07.22 16:22, [email protected] wrote:
> From: Wei Fang <[email protected]>
>
> Enable the fec on i.MX8ULP EVK board.
>
> Signed-off-by: Wei Fang <[email protected]>
> ---
> V2 change:
> Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> V3 change:
> No change.
> ---
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index 33e84c4e9ed8..ebce716b10e6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -19,6 +19,21 @@ memory@80000000 {
> device_type = "memory";
> reg = <0x0 0x80000000 0 0x80000000>;
> };
> +
> + clock_ext_rmii: clock-ext-rmii {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "ext_rmii_clk";
> + #clock-cells = <0>;
> + };
> +
> + clock_ext_ts: clock-ext-ts {
> + compatible = "fixed-clock";
> + /* External ts clock is 50MHZ from PHY on EVK board. */
> + clock-frequency = <50000000>;
> + clock-output-names = "ext_ts_clk";
> + #clock-cells = <0>;
> + };
> };
>
> &lpuart5 {
> @@ -38,7 +53,49 @@ &usdhc0 {
> status = "okay";
> };
>
> +&fec {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_enet>;
> + pinctrl-1 = <&pinctrl_enet>;
> + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> + <&pcc4 IMX8ULP_CLK_ENET>,
> + <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
> + <&clock_ext_rmii>;
> + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
> + assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
> + assigned-clock-parents = <&clock_ext_ts>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy: ethernet-phy {
@1
> + reg = <1>;
> + micrel,led-mode = <1>;
> + };
> + };
> +};
> +
> &iomuxc1 {
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX8ULP_PAD_PTE15__ENET0_MDC 0x43
> + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
> + MX8ULP_PAD_PTE17__ENET0_RXER 0x43
> + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
> + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
> + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
> + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
> + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
> + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
> + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
> + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
> + >;
> + };
> +
> pinctrl_lpuart5: lpuart5grp {
> fsl,pins = <
> MX8ULP_PAD_PTF14__LPUART5_TX 0x3
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 18.07.22 16:22, [email protected] wrote:
> From: Wei Fang <[email protected]>
>
> Add the fec support on i.MX8ULP platforms.
>
> Signed-off-by: Wei Fang <[email protected]>
Reviewed-by: Ahmad Fatoum <[email protected]>
> ---
> V2 change:
> Remove the external clocks which is related to specific board.
> V3 change:
> No change.
> ---
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 60c1b018bf03..3e8a1e4f0fc2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -16,6 +16,7 @@ / {
> #size-cells = <2>;
>
> aliases {
> + ethernet0 = &fec;
> gpio0 = &gpiod;
> gpio1 = &gpioe;
> gpio2 = &gpiof;
> @@ -365,6 +366,16 @@ usdhc2: mmc@298f0000 {
> bus-width = <4>;
> status = "disabled";
> };
> +
> + fec: ethernet@29950000 {
> + compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
> + reg = <0x29950000 0x10000>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "int0";
> + fsl,num-tx-queues = <1>;
> + fsl,num-rx-queues = <1>;
> + status = "disabled";
> + };
> };
>
> gpioe: gpio@2d000080 {
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On 18/07/2022 16:22, [email protected] wrote:
> From: Wei Fang <[email protected]>
>
> Add fsl,imx8ulp-fec for i.MX8ULP platform.
>
> Signed-off-by: Wei Fang <[email protected]>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540
If a tag was not added on purpose, please state why and what changed.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: 2022??7??18?? 21:40
> To: Wei Fang <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; Peng Fan <[email protected]>; Jacky Bai
> <[email protected]>; [email protected];
> [email protected]; Aisheng Dong <[email protected]>
> Subject: Re: [PATCH V3 1/3] dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items
>
> On 18/07/2022 16:22, [email protected] wrote:
> > From: Wei Fang <[email protected]>
> >
> > Add fsl,imx8ulp-fec for i.MX8ULP platform.
> >
> > Signed-off-by: Wei Fang <[email protected]>
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
I'm very grateful for your instruction, it is very useful. And I'm so sorry that I did not
add Acked-by tags for the new version. Can you sign the Acked-by/Reviewed-by
tags again? I will be very appreciated.
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Felixir.bo
> otlin.com%2Flinux%2Fv5.17%2Fsource%2FDocumentation%2Fprocess%2Fsub
> mitting-patches.rst%23L540&data=05%7C01%7Cwei.fang%40nxp.com%7
> Cdd610ad40d334a733fc308da68c3068a%7C686ea1d3bc2b4c6fa92cd99c5c3
> 01635%7C0%7C0%7C637937484092274900%7CUnknown%7CTWFpbGZsb3d
> 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3
> D%7C3000%7C%7C%7C&sdata=84RF0scrg8oqwRLfspH55pdbISLdd3La5D
> uhKuw0NqA%3D&reserved=0
>
> If a tag was not added on purpose, please state why and what changed.
>
>
>
> Best regards,
> Krzysztof
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + ethphy: ethernet-phy {
>
> @1
The DT tools should of warned about this as well. So maybe the build
testing needs extending to run all the DT tools?
Andrew