From: Kah Jing Lee <[email protected]>
Hi,
Patches have been internally reviewed by colleagues at Intel.
New sysid driver for Altera(Intel) Sysid component is generally part of an
FPGA design. The component can be hotplugged when the FPGA is reconfigured.
This patch fixes the driver to support the component being hotplugged.
Thanks,
KJ
Kah Jing Lee (2):
drivers: misc: intel_sysid: Add sysid from arch to drivers
dt-bindings: misc: Add the system id binding for Altera(Intel) FPGA
platform
.../misc/intel,socfpga-sysid-1.0.yaml | 39 +++++
drivers/misc/Kconfig | 9 ++
drivers/misc/Makefile | 1 +
drivers/misc/intel_sysid.c | 142 ++++++++++++++++++
4 files changed, 191 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/
intel,socfpga-sysid-1.0.yaml
create mode 100644 drivers/misc/intel_sysid.c
--
2.25.1
From: Kah Jing Lee <[email protected]>
Opps, I think I missed out the in-reply-to for the patch series.
Will do that for v2 once I get back from Intel OTC folks, and resent =).
Thanks,
KJ
On Thu, Jun 02, 2022 at 08:20:09PM +0800, [email protected] wrote:
> From: Kah Jing Lee <[email protected]>
>
> Hi,
> Patches have been internally reviewed by colleagues at Intel.
But you did not send them as a series, or as a v2, or send out patch
1/2?
Please take a look at the kernel documentation for how to do this all
properly.
thanks,
greg k-h
From: Kah Jing Lee <[email protected]>
Hi,
I would like to request review for the new System ID driver for Intel FPGA
platform.
New sysid driver for Altera(Intel) Sysid component is generally part of an
FPGA design. The component can be hotplugged when the FPGA is reconfigured.
There are two basic ways to use the system ID core:
- Verify the system ID before downloading new software to a system. This
method can be used by software development tools, before downloading a
program to a target hardware system, if the program is compiled for
different hardware.
- Check system ID after reset. If a program is running on hardware other
than the expected Platform Designer system, the program may fail to
function altogether. If the program does not crash, it can behave
erroneously in subtle ways that are difficult to debug. To protect against
this case, a program can compare the expected system ID against the
system ID core, and report an error if they do not match.
Documentation link:
https://rocketboards.org/foswiki/Documentation/AgilexSoCGSRD#PR_Files
Feedback from maintainers:
https://lore.kernel.org/lkml/[email protected]/#t
Kah Jing Lee (3):
drivers: misc: intel_sysid: Add sysid from arch to drivers
dt-bindings: misc: intel_sysid: Add the system id binding for
Altera(Intel) FPGA platform
documentation: misc: intel_sysid: Add the system id sysfs
documentation for Altera(Intel) FPGA platform
.../testing/sysfs-devices-platform-soc-sysid | 27 +++++
.../bindings/misc/intel,socfpga-sysid.yaml | 41 +++++++
drivers/misc/Kconfig | 9 ++
drivers/misc/Makefile | 1 +
drivers/misc/intel_sysid.c | 114 ++++++++++++++++++
5 files changed, 192 insertions(+)
create mode 100644 Documentation/ABI/testing/
sysfs-devices-platform-soc-sysid
create mode 100644 Documentation/devicetree/bindings/misc/
intel,socfpga-sysid.yaml
create mode 100644 drivers/misc/intel_sysid.c
--
2.25.1
From: Kah Jing Lee <[email protected]>
This sysfs documentation is created for Altera(Intel) FPGA platform
System ID soft IP. The Altera(Intel) Sysid component is generally
part of an FPGA design.
The component can be hotplugged when the FPGA is reconfigured.
Based on an initial contribution from Ley Foon Tan at Altera
Signed-off-by: Kah Jing Lee <[email protected]>
Reviewed-by: Zhou Furong <[email protected]>
Reviewed-by: Pierre-Louis Bossart <[email protected]>
---
.../testing/sysfs-devices-platform-soc-sysid | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
new file mode 100644
index 000000000000..9fa58fd88dc0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
@@ -0,0 +1,27 @@
+What: /sys/devices/platform/soc@X/soc:base_fpga_region/
+soc:base_fpga_region:fpga_pr_region0/XXXXXXXX.sysid/
+Date: May 2022
+KernelVersion: v5.18
+Contact: Kah Jing Lee <[email protected]>
+Description:
+ The soc@X/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/
+ XXXXXXXX.sysid/ directory contains read-only attributes exposing
+ information about an System ID soft IP device. The X values could vary,
+ based on the FPGA platform System ID soft IP register address.
+
+What: .../XXXXXXX.sysid/sysid
+Date: May 2022
+KernelVersion: v5.18
+Contact: Kah Jing Lee <[email protected]>
+Description:
+ The .../XXXXXXX.sysid/sysid file contains the System ID for the FPGA
+ platform which is unique for the platform type and can be used for
+ checking the platform type for software download purposes.
+
+What: .../XXXXXXX.sysid/buildtime
+Date: May 2022
+KernelVersion: v5.18
+Contact: Kah Jing Lee <[email protected]>
+Description:
+ The .../XXXXXXX.sysid/buildtime file contains the buildtime for the
+ FPGA board file generation.
--
2.25.1
From: Kah Jing Lee <[email protected]>
This binding is created for Altera(Intel) FPGA platform System ID soft IP.
The Altera(Intel) Sysid component is generally part of an FPGA design.
The component can be hotplugged when the FPGA is reconfigured.
Based on an initial contribution from Ley Foon Tan at Altera
Signed-off-by: Kah Jing Lee <[email protected]>
Reviewed-by: Zhou Furong <[email protected]>
Reviewed-by: Pierre-Louis Bossart <[email protected]>
---
.../bindings/misc/intel,socfpga-sysid.yaml | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
new file mode 100644
index 000000000000..055f4cb305ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022, Intel Corporation.
+# Copyright (C) 2013-2015, Altera Corporation.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,socfpga-sysid.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera(Intel) Sysid IP core driver
+
+maintainers:
+ - Arnd Bergmann <[email protected]>
+ - Greg Kroah-Hartman <[email protected]>
+
+description: |
+ The Altera(Intel) Sysid component is generally part of an FPGA design. The
+ component can be hotplugged when the FPGA is reconfigured. This patch
+ fixes the driver to support the component being hotplugged.
+
+properties:
+ compatible:
+ items:
+ - const: intel,socfpga-sysid-1.0
+
+ reg:
+ items:
+ - description: physical address and length of the registers which
+ contain revision and debug features
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ sysid_qsys: sysid@10000 {
+ compatible = "intel,socfpga-sysid-1.0";
+ reg = < 0x10000 0x00000008 >;
+ };
--
2.25.1
On Thu, Jul 21, 2022 at 08:32:59PM +0800, [email protected] wrote:
> From: Kah Jing Lee <[email protected]>
>
> This sysfs documentation is created for Altera(Intel) FPGA platform
> System ID soft IP. The Altera(Intel) Sysid component is generally
> part of an FPGA design.
> The component can be hotplugged when the FPGA is reconfigured.
>
> Based on an initial contribution from Ley Foon Tan at Altera
> Signed-off-by: Kah Jing Lee <[email protected]>
> Reviewed-by: Zhou Furong <[email protected]>
> Reviewed-by: Pierre-Louis Bossart <[email protected]>
> ---
> .../testing/sysfs-devices-platform-soc-sysid | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
>
> diff --git a/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> new file mode 100644
> index 000000000000..9fa58fd88dc0
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> @@ -0,0 +1,27 @@
> +What: /sys/devices/platform/soc@X/soc:base_fpga_region/
> +soc:base_fpga_region:fpga_pr_region0/XXXXXXXX.sysid/
> +Date: May 2022
> +KernelVersion: v5.18
5.18 is long released. And it's after May 2022 now :(
> +Contact: Kah Jing Lee <[email protected]>
> +Description:
> + The soc@X/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/
> + XXXXXXXX.sysid/ directory contains read-only attributes exposing
> + information about an System ID soft IP device. The X values could vary,
> + based on the FPGA platform System ID soft IP register address.
> +
> +What: .../XXXXXXX.sysid/sysid
> +Date: May 2022
> +KernelVersion: v5.18
> +Contact: Kah Jing Lee <[email protected]>
> +Description:
> + The .../XXXXXXX.sysid/sysid file contains the System ID for the FPGA
> + platform which is unique for the platform type and can be used for
> + checking the platform type for software download purposes.
What format is this data in?
> +
> +What: .../XXXXXXX.sysid/buildtime
> +Date: May 2022
> +KernelVersion: v5.18
> +Contact: Kah Jing Lee <[email protected]>
> +Description:
> + The .../XXXXXXX.sysid/buildtime file contains the buildtime for the
> + FPGA board file generation.
What format is this data in?
Please be specific.
thanks,
greg k-h
On Thu, Jul 21, 2022 at 08:32:17PM +0800, [email protected] wrote:
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2022, Intel Corporation.
> +# Copyright (C) 2013-2015, Altera Corporation.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/intel,socfpga-sysid.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera(Intel) Sysid IP core driver
> +
> +maintainers:
> + - Arnd Bergmann <[email protected]>
> + - Greg Kroah-Hartman <[email protected]>
You want me to maintain an Intel-only file? Great, where do I send my
billing rates to? :)
thanks,
greg k-h
From: Kah Jing Lee <[email protected]>
> You want me to maintain an Intel-only file? Great, where do I send my
> billing rates to? :)
Updated, and will resend.
Too bad that's beyond my paygrade to approve ;)
Regards,
Lee, Kah Jing
From: Kah Jing Lee <[email protected]>
This binding is created for Altera(Intel) FPGA platform System ID soft IP.
The Altera(Intel) Sysid component is generally part of an FPGA design.
The component can be hotplugged when the FPGA is reconfigured.
Based on an initial contribution from Ley Foon Tan at Altera
Signed-off-by: Kah Jing Lee <[email protected]>
Reviewed-by: Zhou Furong <[email protected]>
Reviewed-by: Pierre-Louis Bossart <[email protected]>
---
v2->v3:
- Updated maintainer
---
---
.../bindings/misc/intel,socfpga-sysid.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
diff --git a/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
new file mode 100644
index 000000000000..7426cbe4462b
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,socfpga-sysid.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022, Intel Corporation.
+# Copyright (C) 2013-2015, Altera Corporation.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,socfpga-sysid.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera(Intel) Sysid IP core driver
+
+maintainers:
+ - Kah Jing Lee <[email protected]>
+
+description: |
+ The Altera(Intel) Sysid component is generally part of an FPGA design. The
+ component can be hotplugged when the FPGA is reconfigured. This patch
+ fixes the driver to support the component being hotplugged.
+
+properties:
+ compatible:
+ items:
+ - const: intel,socfpga-sysid-1.0
+
+ reg:
+ items:
+ - description: physical address and length of the registers which
+ contain revision and debug features
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ sysid_qsys: sysid@10000 {
+ compatible = "intel,socfpga-sysid-1.0";
+ reg = < 0x10000 0x00000008 >;
+ };
--
2.25.1
From: Kah Jing Lee <[email protected]>
This sysfs documentation is created for Altera(Intel) FPGA platform
System ID soft IP. The Altera(Intel) Sysid component is generally
part of an FPGA design.
The component can be hotplugged when the FPGA is reconfigured.
Based on an initial contribution from Ley Foon Tan at Altera
Signed-off-by: Kah Jing Lee <[email protected]>
Reviewed-by: Zhou Furong <[email protected]>
Reviewed-by: Pierre-Louis Bossart <[email protected]>
---
v2->v3:
- Updated kernel version & date
- Added format for sysid & builtime output
---
---
.../testing/sysfs-devices-platform-soc-sysid | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
new file mode 100644
index 000000000000..6e40d154601f
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
@@ -0,0 +1,41 @@
+What: /sys/devices/platform/soc@X/soc:base_fpga_region/
+soc:base_fpga_region:fpga_pr_region0/XXXXXXXX.sysid/
+Date: July 2022
+KernelVersion: v5.20
+Contact: Kah Jing Lee <[email protected]>
+Description:
+ The soc@X/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/
+ XXXXXXXX.sysid/ directory contains read-only attributes exposing
+ information about an System ID soft IP device. The X values could vary,
+ based on the FPGA platform System ID soft IP register address.
+
+What: .../XXXXXXX.sysid/sysid
+Date: July 2022
+KernelVersion: v5.20
+Contact: Kah Jing Lee <[email protected]>
+Description:
+ The .../XXXXXXX.sysid/sysid file contains the System ID for the FPGA
+ platform which is unique for the platform type and can be used for
+ checking the platform type for software download purposes. Sysid value
+ reported is in numerical format, and can also be printed in hex format
+ for human-readable string.
+ E.g:
+ root@agilex:~# cat /sys/bus/platform/drivers/altera_sysid/
+ f9000900.sysid/sysid/id
+ 4207856382
+ root@agilex:~# cat /sys/bus/platform/drivers/altera_sysid/
+ f9000900.sysid/sysid/id | xargs printf "0x%08x\n"
+ 0xfacecafe
+
+What: .../XXXXXXX.sysid/buildtime
+Date: July 2022
+KernelVersion: v5.20
+Contact: Kah Jing Lee <[email protected]>
+Description:
+ The .../XXXXXXX.sysid/buildtime file contains the buildtime for the
+ FPGA board file generation. Buildtime value reported in
+ <Unix timestamp> (YYYY-mm-dd HH:MM:SS UTC) format.
+ E.g:
+ root@agilex:~# cat /sys/bus/platform/drivers/altera_sysid/
+ f9000900.sysid/sysid/timestamp
+ 1637751409 (2021-11-24 10:56:49 UTC)
--
2.25.1
On Thu, Jul 21, 2022 at 08:30:19PM +0800, [email protected] wrote:
> From: Kah Jing Lee <[email protected]>
>
> Hi,
>
> I would like to request review for the new System ID driver for Intel FPGA
> platform.
>
> New sysid driver for Altera(Intel) Sysid component is generally part of an
> FPGA design. The component can be hotplugged when the FPGA is reconfigured.
>
> There are two basic ways to use the system ID core:
> - Verify the system ID before downloading new software to a system. This
> method can be used by software development tools, before downloading a
> program to a target hardware system, if the program is compiled for
> different hardware.
>
> - Check system ID after reset. If a program is running on hardware other
> than the expected Platform Designer system, the program may fail to
> function altogether. If the program does not crash, it can behave
> erroneously in subtle ways that are difficult to debug. To protect against
> this case, a program can compare the expected system ID against the
> system ID core, and report an error if they do not match.
>
> Documentation link:
> https://rocketboards.org/foswiki/Documentation/AgilexSoCGSRD#PR_Files
>
> Feedback from maintainers:
> https://lore.kernel.org/lkml/[email protected]/#t
That does not describe what changed from the previous version at all, it
just points to a response from me saying you all need to work on this
driver.
thanks,
greg k-h
On Mon, Jul 25, 2022 at 11:59:41AM +0800, [email protected] wrote:
> From: Kah Jing Lee <[email protected]>
>
> This sysfs documentation is created for Altera(Intel) FPGA platform
> System ID soft IP. The Altera(Intel) Sysid component is generally
> part of an FPGA design.
> The component can be hotplugged when the FPGA is reconfigured.
>
> Based on an initial contribution from Ley Foon Tan at Altera
> Signed-off-by: Kah Jing Lee <[email protected]>
You always need a blank line before the signed-off-by, didn't checkpatch
complain about this?
> Reviewed-by: Zhou Furong <[email protected]>
> Reviewed-by: Pierre-Louis Bossart <[email protected]>
>
> ---
> v2->v3:
> - Updated kernel version & date
> - Added format for sysid & builtime output
Please resend patches as whole new series, not as odd responses to
responses like this as it is impossible to figure out this way.
Please take some time and review patches from others to see just how
this process works.
> ---
> ---
> .../testing/sysfs-devices-platform-soc-sysid | 41 +++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
>
> diff --git a/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> new file mode 100644
> index 000000000000..6e40d154601f
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> @@ -0,0 +1,41 @@
> +What: /sys/devices/platform/soc@X/soc:base_fpga_region/
> +soc:base_fpga_region:fpga_pr_region0/XXXXXXXX.sysid/
> +Date: July 2022
July is almost over.
> +KernelVersion: v5.20
> +Contact: Kah Jing Lee <[email protected]>
> +Description:
> + The soc@X/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/
> + XXXXXXXX.sysid/ directory contains read-only attributes exposing
> + information about an System ID soft IP device. The X values could vary,
> + based on the FPGA platform System ID soft IP register address.
> +
> +What: .../XXXXXXX.sysid/sysid
> +Date: July 2022
> +KernelVersion: v5.20
> +Contact: Kah Jing Lee <[email protected]>
> +Description:
> + The .../XXXXXXX.sysid/sysid file contains the System ID for the FPGA
> + platform which is unique for the platform type and can be used for
> + checking the platform type for software download purposes. Sysid value
> + reported is in numerical format, and can also be printed in hex format
> + for human-readable string.
> + E.g:
> + root@agilex:~# cat /sys/bus/platform/drivers/altera_sysid/
> + f9000900.sysid/sysid/id
Why the line wrapping?
> + 4207856382
> + root@agilex:~# cat /sys/bus/platform/drivers/altera_sysid/
> + f9000900.sysid/sysid/id | xargs printf "0x%08x\n"
> + 0xfacecafe
If userspace wants this in hex format, just have the sysfs file export a
hex format. No need to provide a tutorial for how to convert bases in
userspace, right?
> +
> +What: .../XXXXXXX.sysid/buildtime
> +Date: July 2022
> +KernelVersion: v5.20
> +Contact: Kah Jing Lee <[email protected]>
> +Description:
> + The .../XXXXXXX.sysid/buildtime file contains the buildtime for the
> + FPGA board file generation. Buildtime value reported in
> + <Unix timestamp> (YYYY-mm-dd HH:MM:SS UTC) format.
> + E.g:
> + root@agilex:~# cat /sys/bus/platform/drivers/altera_sysid/
> + f9000900.sysid/sysid/timestamp
> + 1637751409 (2021-11-24 10:56:49 UTC)
Why not use the proper RFC format for time here instead of making up a
new one? And who will use this file, why does it have to be parsed like
this?
thanks,
greg k-h