2023-07-10 17:14:28

by Naresh Solanki

Subject: [PATCH 2/2] hwmon: (dimmtemp) Add Sapphire Rappids support

From: Patrick Rudolph <[email protected]>

This patch extends the functionality of the hwmon (dimmtemp) to include
support for Sapphire Rappids platform.

Sapphire Rappids can accommodate up to 8 CPUs, each with 16 DIMMs. To
accommodate this configuration, the maximum supported DIMM count is
increased, and the corresponding Sapphire Rappids ID and threshold code
are added.

The patch has been tested on a 4S system with 64 DIMMs installed.
Default thresholds are utilized for Sapphire Rappids, as accessing the
threshold requires accessing the UBOX device on Uncore bus 0, which can
only be achieved using MSR access. The non-PCI-compliant MMIO BARs are
not available for this purpose.

Signed-off-by: Patrick Rudolph <[email protected]>
---
drivers/hwmon/peci/dimmtemp.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
index ce89da3937a0..ea4ac5a023cf 100644
--- a/drivers/hwmon/peci/dimmtemp.c
+++ b/drivers/hwmon/peci/dimmtemp.c
@@ -30,8 +30,10 @@
#define DIMM_IDX_MAX_ON_ICX 2
#define CHAN_RANK_MAX_ON_ICXD 4
#define DIMM_IDX_MAX_ON_ICXD 2
+#define CHAN_RANK_MAX_ON_SPR 128
+#define DIMM_IDX_MAX_ON_SPR 2

-#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
+#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR
#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
#define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)

@@ -534,6 +536,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
return 0;
}

+static int
+read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
+{
+ /* Use defaults */
+ *data = (95 << 16) | (90 << 8);
+
+ return 0;
+}
+
static const struct dimm_info dimm_hsx = {
.chan_rank_max = CHAN_RANK_MAX_ON_HSX,
.dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
@@ -576,6 +587,13 @@ static const struct dimm_info dimm_icxd = {
.read_thresholds = &read_thresholds_icx,
};

+static const struct dimm_info dimm_spr = {
+ .chan_rank_max = CHAN_RANK_MAX_ON_SPR,
+ .dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
+ .min_peci_revision = 0x40,
+ .read_thresholds = &read_thresholds_spr,
+};
+
static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
{
.name = "peci_cpu.dimmtemp.hsx",
@@ -601,6 +619,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
.name = "peci_cpu.dimmtemp.icxd",
.driver_data = (kernel_ulong_t)&dimm_icxd,
},
+ {
+ .name = "peci_cpu.dimmtemp.spr",
+ .driver_data = (kernel_ulong_t)&dimm_spr,
+ },
{ }
};
MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
--
2.41.0

2023-07-10 18:53:49

by Guenter Roeck

Subject: Re: [PATCH 2/2] hwmon: (dimmtemp) Add Sapphire Rappids support

On Mon, Jul 10, 2023 at 06:47:04PM +0200, Naresh Solanki wrote:
> From: Patrick Rudolph <[email protected]>
>
> This patch extends the functionality of the hwmon (dimmtemp) to include
> support for Sapphire Rappids platform.
>
> Sapphire Rappids can accommodate up to 8 CPUs, each with 16 DIMMs. To
> accommodate this configuration, the maximum supported DIMM count is
> increased, and the corresponding Sapphire Rappids ID and threshold code
> are added.
>
> The patch has been tested on a 4S system with 64 DIMMs installed.
> Default thresholds are utilized for Sapphire Rappids, as accessing the
> threshold requires accessing the UBOX device on Uncore bus 0, which can
> only be achieved using MSR access. The non-PCI-compliant MMIO BARs are
> not available for this purpose.
>
> Signed-off-by: Patrick Rudolph <[email protected]>

Does this patch depend on the other patch, the one introducing
Sapphire Rappids to peci/cputemp ?

Guenter

> ---
> drivers/hwmon/peci/dimmtemp.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
> index ce89da3937a0..ea4ac5a023cf 100644
> --- a/drivers/hwmon/peci/dimmtemp.c
> +++ b/drivers/hwmon/peci/dimmtemp.c
> @@ -30,8 +30,10 @@
> #define DIMM_IDX_MAX_ON_ICX 2
> #define CHAN_RANK_MAX_ON_ICXD 4
> #define DIMM_IDX_MAX_ON_ICXD 2
> +#define CHAN_RANK_MAX_ON_SPR 128
> +#define DIMM_IDX_MAX_ON_SPR 2
>
> -#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
> +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR
> #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
> #define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)
>
> @@ -534,6 +536,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
> return 0;
> }
>
> +static int
> +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
> +{
> + /* Use defaults */
> + *data = (95 << 16) | (90 << 8);
> +
> + return 0;
> +}
> +
> static const struct dimm_info dimm_hsx = {
> .chan_rank_max = CHAN_RANK_MAX_ON_HSX,
> .dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
> @@ -576,6 +587,13 @@ static const struct dimm_info dimm_icxd = {
> .read_thresholds = &read_thresholds_icx,
> };
>
> +static const struct dimm_info dimm_spr = {
> + .chan_rank_max = CHAN_RANK_MAX_ON_SPR,
> + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
> + .min_peci_revision = 0x40,
> + .read_thresholds = &read_thresholds_spr,
> +};
> +
> static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
> {
> .name = "peci_cpu.dimmtemp.hsx",
> @@ -601,6 +619,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
> .name = "peci_cpu.dimmtemp.icxd",
> .driver_data = (kernel_ulong_t)&dimm_icxd,
> },
> + {
> + .name = "peci_cpu.dimmtemp.spr",
> + .driver_data = (kernel_ulong_t)&dimm_spr,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
> --
> 2.41.0
>

2023-07-11 15:32:49

by Naresh Solanki

Subject: Re: [PATCH 2/2] hwmon: (dimmtemp) Add Sapphire Rappids support

Hi Guenter,

On Mon, 10 Jul 2023 at 20:48, Guenter Roeck <[email protected]> wrote:
>
> On Mon, Jul 10, 2023 at 06:47:04PM +0200, Naresh Solanki wrote:
> > From: Patrick Rudolph <[email protected]>
> >
> > This patch extends the functionality of the hwmon (dimmtemp) to include
> > support for Sapphire Rappids platform.
> >
> > Sapphire Rappids can accommodate up to 8 CPUs, each with 16 DIMMs. To
> > accommodate this configuration, the maximum supported DIMM count is
> > increased, and the corresponding Sapphire Rappids ID and threshold code
> > are added.
> >
> > The patch has been tested on a 4S system with 64 DIMMs installed.
> > Default thresholds are utilized for Sapphire Rappids, as accessing the
> > threshold requires accessing the UBOX device on Uncore bus 0, which can
> > only be achieved using MSR access. The non-PCI-compliant MMIO BARs are
> > not available for this purpose.
> >
> > Signed-off-by: Patrick Rudolph <[email protected]>
>
> Does this patch depend on the other patch, the one introducing
> Sapphire Rappids to peci/cputemp ?
Yes they are dependent.
Will bundle them together & resend.

~Naresh

>
> Guenter
>
> > ---
> > drivers/hwmon/peci/dimmtemp.c | 24 +++++++++++++++++++++++-
> > 1 file changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
> > index ce89da3937a0..ea4ac5a023cf 100644
> > --- a/drivers/hwmon/peci/dimmtemp.c
> > +++ b/drivers/hwmon/peci/dimmtemp.c
> > @@ -30,8 +30,10 @@
> > #define DIMM_IDX_MAX_ON_ICX 2
> > #define CHAN_RANK_MAX_ON_ICXD 4
> > #define DIMM_IDX_MAX_ON_ICXD 2
> > +#define CHAN_RANK_MAX_ON_SPR 128
> > +#define DIMM_IDX_MAX_ON_SPR 2
> >
> > -#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX
> > +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR
> > #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX
> > #define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX)
> >
> > @@ -534,6 +536,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u
> > return 0;
> > }
> >
> > +static int
> > +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
> > +{
> > + /* Use defaults */
> > + *data = (95 << 16) | (90 << 8);
> > +
> > + return 0;
> > +}
> > +
> > static const struct dimm_info dimm_hsx = {
> > .chan_rank_max = CHAN_RANK_MAX_ON_HSX,
> > .dimm_idx_max = DIMM_IDX_MAX_ON_HSX,
> > @@ -576,6 +587,13 @@ static const struct dimm_info dimm_icxd = {
> > .read_thresholds = &read_thresholds_icx,
> > };
> >
> > +static const struct dimm_info dimm_spr = {
> > + .chan_rank_max = CHAN_RANK_MAX_ON_SPR,
> > + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR,
> > + .min_peci_revision = 0x40,
> > + .read_thresholds = &read_thresholds_spr,
> > +};
> > +
> > static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
> > {
> > .name = "peci_cpu.dimmtemp.hsx",
> > @@ -601,6 +619,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
> > .name = "peci_cpu.dimmtemp.icxd",
> > .driver_data = (kernel_ulong_t)&dimm_icxd,
> > },
> > + {
> > + .name = "peci_cpu.dimmtemp.spr",
> > + .driver_data = (kernel_ulong_t)&dimm_spr,
> > + },
> > { }
> > };
> > MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
> > --
> > 2.41.0
> >