From: Radhey Shyam Pandey <[email protected]>
Convert the bindings document for Xilinx AXI Ethernet Subsystem
from txt to yaml. No changes to existing binding description.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
---
Changes in V7:
1) Addressed below review comments.
a) phy-mode: lists.
b) Update axistream-connected description.
c) Moved $ref: /schemas/net/ethernet-controller.yaml# to allOf.
d) Add type to mdio.
Changes in V6:
1) Addressed below review comments.
a)add a $ref to ethernet-controller.yaml for pcs-handle.
b)Drop unused labels(axi_ethernetlite_0_mdio).
c)Not relevant to the binding(interrupt-parent).
Changes in V5:
1) Removed .txt file which was missed in V4
Changes in V4:
1)Changed the interrupts property and add allOf:if:then for it.
Changes in V3:
1) Moved RFC to PATCH.
2) Addressed below review comments
a) Indentation.
b) maxItems:3 does not match your description.
c) Filename matching compatibles.
Changes in V2:
1) remove .txt and change the name of file to xlnx,axiethernet.yaml.
2) Fix DT check warning('device_type' does not match any of the regexes:
'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/net
/xilinx_axienet.yaml).
---
.../bindings/net/xilinx_axienet.txt | 101 ----------
.../bindings/net/xlnx,axi-ethernet.yaml | 173 ++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 174 insertions(+), 101 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/xilinx_axienet.txt
create mode 100644 Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
deleted file mode 100644
index 80e505a2fda1..000000000000
--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ /dev/null
@@ -1,101 +0,0 @@
-XILINX AXI ETHERNET Device Tree Bindings
---------------------------------------------------------
-
-Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
-provides connectivity to an external ethernet PHY supporting different
-interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
-segments of memory for buffering TX and RX, as well as the capability of
-offloading TX/RX checksum calculation off the processor.
-
-Management configuration is done through the AXI interface, while payload is
-sent and received through means of an AXI DMA controller. This driver
-includes the DMA driver code, so this driver is incompatible with AXI DMA
-driver.
-
-For more details about mdio please refer phy.txt file in the same directory.
-
-Required properties:
-- compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
- "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
-- reg : Address and length of the IO space, as well as the address
- and length of the AXI DMA controller IO space, unless
- axistream-connected is specified, in which case the reg
- attribute of the node referenced by it is used.
-- interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
- and optionally Ethernet core. If axistream-connected is
- specified, the TX/RX DMA interrupts should be on that node
- instead, and only the Ethernet core interrupt is optionally
- specified here.
-- phy-handle : Should point to the external phy device if exists. Pointing
- this to the PCS/PMA PHY is deprecated and should be avoided.
- See ethernet.txt file in the same directory.
-- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
-
-Optional properties:
-- phy-mode : See ethernet.txt
-- xlnx,phy-type : Deprecated, do not use, but still accepted in preference
- to phy-mode.
-- xlnx,txcsum : 0 or empty for disabling TX checksum offload,
- 1 to enable partial TX checksum offload,
- 2 to enable full TX checksum offload
-- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
-- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
- support both 1000BaseX and SGMII modes. If set, the phy-mode
- should be set to match the mode selected on core reset (i.e.
- by the basex_or_sgmii core input line).
-- clock-names: Tuple listing input clock names. Possible clocks:
- s_axi_lite_clk: Clock for AXI register slave interface
- axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
- ref_clk: Ethernet reference clock, used by signal delay
- primitives and transceivers
- mgt_clk: MGT reference clock (used by optional internal
- PCS/PMA PHY)
-
- Note that if s_axi_lite_clk is not specified by name, the
- first clock of any name is used for this. If that is also not
- specified, the clock rate is auto-detected from the CPU clock
- (but only on platforms where this is possible). New device
- trees should specify all applicable clocks by name - the
- fallbacks to an unnamed clock or to CPU clock are only for
- backward compatibility.
-- clocks: Phandles to input clocks matching clock-names. Refer to common
- clock bindings.
-- axistream-connected: Reference to another node which contains the resources
- for the AXI DMA controller used by this device.
- If this is specified, the DMA-related resources from that
- device (DMA registers and DMA TX/RX interrupts) rather
- than this one will be used.
- - mdio : Child node for MDIO bus. Must be defined if PHY access is
- required through the core's MDIO interface (i.e. always,
- unless the PHY is accessed through a different bus).
- Non-standard MDIO bus frequency is supported via
- "clock-frequency", see mdio.yaml.
-
- - pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
- modes, where "pcs-handle" should be used to point
- to the PCS/PMA PHY, and "phy-handle" should point to an
- external PHY if exists.
-
-Example:
- axi_ethernet_eth: ethernet@40c00000 {
- compatible = "xlnx,axi-ethernet-1.00.a";
- device_type = "network";
- interrupt-parent = <µblaze_0_axi_intc>;
- interrupts = <2 0 1>;
- clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
- clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
- phy-mode = "mii";
- reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
- xlnx,rxcsum = <0x2>;
- xlnx,rxmem = <0x800>;
- xlnx,txcsum = <0x2>;
- phy-handle = <&phy0>;
- axi_ethernetlite_0_mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- phy0: phy@0 {
- device_type = "ethernet-phy";
- reg = <1>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
new file mode 100644
index 000000000000..80843c177029
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AXI 1G/2.5G Ethernet Subsystem
+
+description: |
+ Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
+ provides connectivity to an external ethernet PHY supporting different
+ interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
+ segments of memory for buffering TX and RX, as well as the capability of
+ offloading TX/RX checksum calculation off the processor.
+
+ Management configuration is done through the AXI interface, while payload is
+ sent and received through means of an AXI DMA controller. This driver
+ includes the DMA driver code, so this driver is incompatible with AXI DMA
+ driver.
+
+maintainers:
+ - Radhey Shyam Pandey <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - xlnx,axi-ethernet-1.00.a
+ - xlnx,axi-ethernet-1.01.a
+ - xlnx,axi-ethernet-2.01.a
+
+ reg:
+ description:
+ Address and length of the IO space, as well as the address
+ and length of the AXI DMA controller IO space, unless
+ axistream-connected is specified, in which case the reg
+ attribute of the node referenced by it is used.
+ maxItems: 2
+
+ interrupts:
+ items:
+ - description: Ethernet core interrupt
+ - description: Tx DMA interrupt
+ - description: Rx DMA interrupt
+ description:
+ Ethernet core interrupt is optional. If axistream-connected property is
+ present DMA node should contains TX/RX DMA interrupts else DMA interrupt
+ resources are mentioned on ethernet node.
+ minItems: 1
+
+ phy-handle: true
+
+ xlnx,rxmem:
+ description:
+ Set to allocated memory buffer for Rx/Tx in the hardware.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ phy-mode:
+ items:
+ - description: MII
+ - description: GMII
+ - description: RGMII
+ - description: SGMII
+ - description: 1000BaseX
+ minItems: 1
+
+ xlnx,phy-type:
+ description:
+ Do not use, but still accepted in preference to phy-mode.
+ deprecated: true
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ xlnx,txcsum:
+ description:
+ TX checksum offload. 0 or empty for disabling TX checksum offload,
+ 1 to enable partial TX checksum offload and 2 to enable full TX
+ checksum offload.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ xlnx,rxcsum:
+ description:
+ RX checksum offload. 0 or empty for disabling RX checksum offload,
+ 1 to enable partial RX checksum offload and 2 to enable full RX
+ checksum offload.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ xlnx,switch-x-sgmii:
+ type: boolean
+ description:
+ Indicate the Ethernet core is configured to support both 1000BaseX and
+ SGMII modes. If set, the phy-mode should be set to match the mode
+ selected on core reset (i.e. by the basex_or_sgmii core input line).
+
+ clocks:
+ items:
+ - description: Clock for AXI register slave interface.
+ - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
+ - description: Ethernet reference clock, used by signal delay primitives
+ and transceivers.
+ - description: MGT reference clock (used by optional internal PCS/PMA PHY)
+
+ clock-names:
+ items:
+ - const: s_axi_lite_clk
+ - const: axis_clk
+ - const: ref_clk
+ - const: mgt_clk
+
+ axistream-connected:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle of AXI DMA controller which contains the resources
+ used by this device. If this is specified, the DMA-related resources
+ from that device (DMA registers and DMA TX/RX interrupts) rather than
+ this one will be used.
+
+ mdio:
+ type: object
+
+ pcs-handle:
+ description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
+ modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
+ and "phy-handle" should point to an external PHY if exists.
+
+required:
+ - compatible
+ - interrupts
+ - reg
+ - xlnx,rxmem
+ - phy-handle
+
+allOf:
+ - $ref: /schemas/net/ethernet-controller.yaml#
+ - if:
+ required:
+ - axistream-connected
+
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 3
+
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ axi_ethernet_eth: ethernet@40c00000 {
+ compatible = "xlnx,axi-ethernet-1.00.a";
+ interrupts = <2 0 1>;
+ clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
+ clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
+ phy-mode = "mii";
+ reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
+ xlnx,rxcsum = <0x2>;
+ xlnx,rxmem = <0x800>;
+ xlnx,txcsum = <0x2>;
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@1 {
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2cf9eb43ed8f..0bf527552dc9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22895,6 +22895,7 @@ F: drivers/iio/adc/xilinx-ams.c
XILINX AXI ETHERNET DRIVER
M: Radhey Shyam Pandey <[email protected]>
S: Maintained
+F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
F: drivers/net/ethernet/xilinx/xilinx_axienet*
XILINX CAN DRIVER
--
2.25.1
On Wed, 8 Mar 2023 11:42:23 +0530 Sarath Babu Naidu Gaddam wrote:
> From: Radhey Shyam Pandey <[email protected]>
>
> Convert the bindings document for Xilinx AXI Ethernet Subsystem
> from txt to yaml. No changes to existing binding description.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
Rob, Krzysztof, looks good?
On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
> From: Radhey Shyam Pandey <[email protected]>
>
> Convert the bindings document for Xilinx AXI Ethernet Subsystem
> from txt to yaml. No changes to existing binding description.
>
(...)
> +properties:
> + compatible:
> + enum:
> + - xlnx,axi-ethernet-1.00.a
> + - xlnx,axi-ethernet-1.01.a
> + - xlnx,axi-ethernet-2.01.a
> +
> + reg:
> + description:
> + Address and length of the IO space, as well as the address
> + and length of the AXI DMA controller IO space, unless
> + axistream-connected is specified, in which case the reg
> + attribute of the node referenced by it is used.
Did you test it with axistream-connected? The schema and description
feel contradictory and tests would point the issue.
> + maxItems: 2
> +
> + interrupts:
> + items:
> + - description: Ethernet core interrupt
> + - description: Tx DMA interrupt
> + - description: Rx DMA interrupt
> + description:
> + Ethernet core interrupt is optional. If axistream-connected property is
> + present DMA node should contains TX/RX DMA interrupts else DMA interrupt
> + resources are mentioned on ethernet node.
> + minItems: 1
> +
> + phy-handle: true
> +
> + xlnx,rxmem:
> + description:
> + Set to allocated memory buffer for Rx/Tx in the hardware.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + phy-mode:
> + items:
> + - description: MII
> + - description: GMII
> + - description: RGMII
> + - description: SGMII
> + - description: 1000BaseX
I have doubts you tested it... Since when this is a list? How does it
exactly work and what do you want to show here?
connection type is enum.
> + minItems: 1
> +
> + xlnx,phy-type:
> + description:
> + Do not use, but still accepted in preference to phy-mode.
> + deprecated: true
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + xlnx,txcsum:
> + description:
> + TX checksum offload. 0 or empty for disabling TX checksum offload,
> + 1 to enable partial TX checksum offload and 2 to enable full TX
> + checksum offload.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + xlnx,rxcsum:
> + description:
> + RX checksum offload. 0 or empty for disabling RX checksum offload,
> + 1 to enable partial RX checksum offload and 2 to enable full RX
> + checksum offload.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2]
> +
> + xlnx,switch-x-sgmii:
> + type: boolean
> + description:
> + Indicate the Ethernet core is configured to support both 1000BaseX and
> + SGMII modes. If set, the phy-mode should be set to match the mode
> + selected on core reset (i.e. by the basex_or_sgmii core input line).
> +
> + clocks:
> + items:
> + - description: Clock for AXI register slave interface.
> + - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
> + - description: Ethernet reference clock, used by signal delay primitives
> + and transceivers.
> + - description: MGT reference clock (used by optional internal PCS/PMA PHY)
> +
> + clock-names:
> + items:
> + - const: s_axi_lite_clk
> + - const: axis_clk
> + - const: ref_clk
> + - const: mgt_clk
> +
> + axistream-connected:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Phandle of AXI DMA controller which contains the resources
> + used by this device. If this is specified, the DMA-related resources
> + from that device (DMA registers and DMA TX/RX interrupts) rather than
> + this one will be used.
> +
> + mdio:
> + type: object
> +
> + pcs-handle:
maxItems: 1
> + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
> + modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
> + and "phy-handle" should point to an external PHY if exists.
Best regards,
Krzysztof
On 14/03/2023 00:15, Jakub Kicinski wrote:
> On Wed, 8 Mar 2023 11:42:23 +0530 Sarath Babu Naidu Gaddam wrote:
>> From: Radhey Shyam Pandey <[email protected]>
>>
>> Convert the bindings document for Xilinx AXI Ethernet Subsystem
>> from txt to yaml. No changes to existing binding description.
>>
>> Signed-off-by: Radhey Shyam Pandey <[email protected]>
>> Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
>
> Rob, Krzysztof, looks good?
Thanks for ping, unfortunately needs some changes or clarifications. I
responded with review.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Tuesday, March 14, 2023 9:22 PM
> To: Gaddam, Sarath Babu Naidu
> <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Sarangi,
> Anirudha <[email protected]>; Katakam, Harini
> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> convert bindings document to yaml
>
> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
> > From: Radhey Shyam Pandey <[email protected]>
> >
> > Convert the bindings document for Xilinx AXI Ethernet Subsystem from
> > txt to yaml. No changes to existing binding description.
> >
>
> (...)
>
> > +properties:
> > + compatible:
> > + enum:
> > + - xlnx,axi-ethernet-1.00.a
> > + - xlnx,axi-ethernet-1.01.a
> > + - xlnx,axi-ethernet-2.01.a
> > +
> > + reg:
> > + description:
> > + Address and length of the IO space, as well as the address
> > + and length of the AXI DMA controller IO space, unless
> > + axistream-connected is specified, in which case the reg
> > + attribute of the node referenced by it is used.
>
> Did you test it with axistream-connected? The schema and description
> feel contradictory and tests would point the issue.
Thanks for review comments. We tested with axistream-connected and
did not observe any errors. Do you anticipate any issues/errors ?
will address remaining review comments.
Thanks,
sarath
> > + maxItems: 2
> > +
> > + interrupts:
> > + items:
> > + - description: Ethernet core interrupt
> > + - description: Tx DMA interrupt
> > + - description: Rx DMA interrupt
> > + description:
> > + Ethernet core interrupt is optional. If axistream-connected
> property is
> > + present DMA node should contains TX/RX DMA interrupts else
> DMA interrupt
> > + resources are mentioned on ethernet node.
> > + minItems: 1
> > +
> > + phy-handle: true
> > +
> > + xlnx,rxmem:
> > + description:
> > + Set to allocated memory buffer for Rx/Tx in the hardware.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + phy-mode:
> > + items:
> > + - description: MII
> > + - description: GMII
> > + - description: RGMII
> > + - description: SGMII
> > + - description: 1000BaseX
>
> I have doubts you tested it... Since when this is a list? How does it exactly
> work and what do you want to show here?
>
> connection type is enum.
>
>
> > + minItems: 1
> > +
> > + xlnx,phy-type:
> > + description:
> > + Do not use, but still accepted in preference to phy-mode.
> > + deprecated: true
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + xlnx,txcsum:
> > + description:
> > + TX checksum offload. 0 or empty for disabling TX checksum
> offload,
> > + 1 to enable partial TX checksum offload and 2 to enable full TX
> > + checksum offload.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1, 2]
> > +
> > + xlnx,rxcsum:
> > + description:
> > + RX checksum offload. 0 or empty for disabling RX checksum
> offload,
> > + 1 to enable partial RX checksum offload and 2 to enable full RX
> > + checksum offload.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [0, 1, 2]
> > +
> > + xlnx,switch-x-sgmii:
> > + type: boolean
> > + description:
> > + Indicate the Ethernet core is configured to support both 1000BaseX
> and
> > + SGMII modes. If set, the phy-mode should be set to match the
> mode
> > + selected on core reset (i.e. by the basex_or_sgmii core input line).
> > +
> > + clocks:
> > + items:
> > + - description: Clock for AXI register slave interface.
> > + - description: AXI4-Stream clock for TXD RXD TXC and RXS
> interfaces.
> > + - description: Ethernet reference clock, used by signal delay
> primitives
> > + and transceivers.
> > + - description: MGT reference clock (used by optional internal
> > + PCS/PMA PHY)
> > +
> > + clock-names:
> > + items:
> > + - const: s_axi_lite_clk
> > + - const: axis_clk
> > + - const: ref_clk
> > + - const: mgt_clk
> > +
> > + axistream-connected:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: Phandle of AXI DMA controller which contains the
> resources
> > + used by this device. If this is specified, the DMA-related resources
> > + from that device (DMA registers and DMA TX/RX interrupts) rather
> than
> > + this one will be used.
> > +
> > + mdio:
> > + type: object
> > +
> > + pcs-handle:
>
> maxItems: 1
>
> > + description: Phandle to the internal PCS/PMA PHY in SGMII or
> 1000Base-X
> > + modes, where "pcs-handle" should be used to point to the
> PCS/PMA PHY,
> > + and "phy-handle" should point to an external PHY if exists.
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Gaddam, Sarath Babu Naidu
> <[email protected]>
> Sent: Tuesday, March 28, 2023 6:22 PM
> To: Krzysztof Kozlowski <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Sarangi,
> Anirudha <[email protected]>; Katakam, Harini
> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> convert bindings document to yaml
>
>
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <[email protected]>
> > Sent: Tuesday, March 14, 2023 9:22 PM
> > To: Gaddam, Sarath Babu Naidu
> > <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; [email protected]; Sarangi,
> > Anirudha <[email protected]>; Katakam, Harini
> > <[email protected]>; git (AMD-Xilinx) <[email protected]>
> > Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> > convert bindings document to yaml
> >
> > On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
> > > From: Radhey Shyam Pandey <[email protected]>
> > >
> > > Convert the bindings document for Xilinx AXI Ethernet Subsystem
> from
> > > txt to yaml. No changes to existing binding description.
> > >
> >
> > (...)
> >
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - xlnx,axi-ethernet-1.00.a
> > > + - xlnx,axi-ethernet-1.01.a
> > > + - xlnx,axi-ethernet-2.01.a
> > > +
> > > + reg:
> > > + description:
> > > + Address and length of the IO space, as well as the address
> > > + and length of the AXI DMA controller IO space, unless
> > > + axistream-connected is specified, in which case the reg
> > > + attribute of the node referenced by it is used.
> >
> > Did you test it with axistream-connected? The schema and description
> > feel contradictory and tests would point the issue.
>
> Thanks for review comments. We tested with axistream-connected and
> did not observe any errors. Do you anticipate any issues/errors ?
Just to add more details, we have tested it using below dt node
axienet@0 {
axistream-connected = <&dma>;
reg = <0x00 0x80000000 0x00 0x40000>;
compatible = "xlnx,axi-ethernet-2.01.a";
clock-names = "s_axi_lite_clk\0axis_clk\0ref_clk";
clocks = <0x03 0x47 0x03 0x47 0x18>;
phy-mode = "sgmii";
xlnx,rxcsum = <0x02>;
xlnx,rxmem = <0x1000>;
xlnx,txcsum = <0x02>;
pcs-handle = <0x19>;
phy-handle = <0x78>;
dmas = <0x17 0x00 0x17 0x01>;
dma-names = "tx_chan0\0rx_chan0";
mac-address = [ff ff ff ff ff ff];
managed = "in-band-status";
phandle = <0x79>;
mdio {
#address-cells = <0x01>;
#size-cells = <0x00>;
phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x00>;
phandle = <0x78>;
};
ethernet-phy@2 {
device_type = "ethernet-phy";
reg = <0x02>;
phandle = <0x19>;
};
};
};
This DT node works with our board. "&dma" is the dma DT node and
to test the second case where dma address and length included in
the axienet reg's property as below
"reg = <0x00 0x80000000 0x00 0x40000 0x0 0x80040000 0x0 0x1000>;"
I did not observe any issue with above two cases. Used below command
to validate the yaml using above DT node.
make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
Thanks,
Sarath
> > > + maxItems: 2
> > > +
> > > + interrupts:
> > > + items:
> > > + - description: Ethernet core interrupt
> > > + - description: Tx DMA interrupt
> > > + - description: Rx DMA interrupt
> > > + description:
> > > + Ethernet core interrupt is optional. If axistream-connected
> > property is
> > > + present DMA node should contains TX/RX DMA interrupts else
> > DMA interrupt
> > > + resources are mentioned on ethernet node.
> > > + minItems: 1
> > > +
> > > + phy-handle: true
> > > +
> > > + xlnx,rxmem:
> > > + description:
> > > + Set to allocated memory buffer for Rx/Tx in the hardware.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > + phy-mode:
> > > + items:
> > > + - description: MII
> > > + - description: GMII
> > > + - description: RGMII
> > > + - description: SGMII
> > > + - description: 1000BaseX
> >
> > I have doubts you tested it... Since when this is a list? How does it
> > exactly work and what do you want to show here?
> >
> > connection type is enum.
> >
> >
> > > + minItems: 1
> > > +
> > > + xlnx,phy-type:
> > > + description:
> > > + Do not use, but still accepted in preference to phy-mode.
> > > + deprecated: true
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > + xlnx,txcsum:
> > > + description:
> > > + TX checksum offload. 0 or empty for disabling TX checksum
> > offload,
> > > + 1 to enable partial TX checksum offload and 2 to enable full TX
> > > + checksum offload.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [0, 1, 2]
> > > +
> > > + xlnx,rxcsum:
> > > + description:
> > > + RX checksum offload. 0 or empty for disabling RX checksum
> > offload,
> > > + 1 to enable partial RX checksum offload and 2 to enable full RX
> > > + checksum offload.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [0, 1, 2]
> > > +
> > > + xlnx,switch-x-sgmii:
> > > + type: boolean
> > > + description:
> > > + Indicate the Ethernet core is configured to support both
> > > + 1000BaseX
> > and
> > > + SGMII modes. If set, the phy-mode should be set to match the
> > mode
> > > + selected on core reset (i.e. by the basex_or_sgmii core input
> line).
> > > +
> > > + clocks:
> > > + items:
> > > + - description: Clock for AXI register slave interface.
> > > + - description: AXI4-Stream clock for TXD RXD TXC and RXS
> > interfaces.
> > > + - description: Ethernet reference clock, used by signal delay
> > primitives
> > > + and transceivers.
> > > + - description: MGT reference clock (used by optional internal
> > > + PCS/PMA PHY)
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: s_axi_lite_clk
> > > + - const: axis_clk
> > > + - const: ref_clk
> > > + - const: mgt_clk
> > > +
> > > + axistream-connected:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description: Phandle of AXI DMA controller which contains the
> > resources
> > > + used by this device. If this is specified, the DMA-related
> resources
> > > + from that device (DMA registers and DMA TX/RX interrupts)
> > > + rather
> > than
> > > + this one will be used.
> > > +
> > > + mdio:
> > > + type: object
> > > +
> > > + pcs-handle:
> >
> > maxItems: 1
> >
> > > + description: Phandle to the internal PCS/PMA PHY in SGMII or
> > 1000Base-X
> > > + modes, where "pcs-handle" should be used to point to the
> > PCS/PMA PHY,
> > > + and "phy-handle" should point to an external PHY if exists.
> >
> > Best regards,
> > Krzysztof
> -----Original Message-----
> From: Gaddam, Sarath Babu Naidu
> <[email protected]>
> Sent: Tuesday, March 28, 2023 9:31 PM
> To: Krzysztof Kozlowski <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Sarangi,
> Anirudha <[email protected]>; Katakam, Harini
> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> convert bindings document to yaml
>
>
>
> > -----Original Message-----
> > From: Gaddam, Sarath Babu Naidu
> > <[email protected]>
> > Sent: Tuesday, March 28, 2023 6:22 PM
> > To: Krzysztof Kozlowski <[email protected]>;
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; [email protected]; Sarangi,
> > Anirudha <[email protected]>; Katakam, Harini
> > <[email protected]>; git (AMD-Xilinx) <[email protected]>
> > Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> > convert bindings document to yaml
> >
> >
> >
> > > -----Original Message-----
> > > From: Krzysztof Kozlowski <[email protected]>
> > > Sent: Tuesday, March 14, 2023 9:22 PM
> > > To: Gaddam, Sarath Babu Naidu
> > > <[email protected]>; [email protected];
> > > [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]
> > > Cc: [email protected]; [email protected];
> > > [email protected]; [email protected]; linux-arm-
> > > [email protected]; [email protected]; Sarangi,
> > > Anirudha <[email protected]>; Katakam, Harini
> > > <[email protected]>; git (AMD-Xilinx) <[email protected]>
> > > Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> > > convert bindings document to yaml
> > >
> > > On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
> > > > From: Radhey Shyam Pandey <[email protected]>
> > > >
> > > > Convert the bindings document for Xilinx AXI Ethernet Subsystem
> > from
> > > > txt to yaml. No changes to existing binding description.
> > > >
> > >
> > > (...)
> > >
> > > > +properties:
> > > > + compatible:
> > > > + enum:
> > > > + - xlnx,axi-ethernet-1.00.a
> > > > + - xlnx,axi-ethernet-1.01.a
> > > > + - xlnx,axi-ethernet-2.01.a
> > > > +
> > > > + reg:
> > > > + description:
> > > > + Address and length of the IO space, as well as the address
> > > > + and length of the AXI DMA controller IO space, unless
> > > > + axistream-connected is specified, in which case the reg
> > > > + attribute of the node referenced by it is used.
> > >
> > > Did you test it with axistream-connected? The schema and description
> > > feel contradictory and tests would point the issue.
> >
> > Thanks for review comments. We tested with axistream-connected and
> did
> > not observe any errors. Do you anticipate any issues/errors ?
>
> Just to add more details, we have tested it using below dt node
>
> axienet@0 {
> axistream-connected = <&dma>;
> reg = <0x00 0x80000000 0x00 0x40000>;
> compatible = "xlnx,axi-ethernet-2.01.a";
> clock-names = "s_axi_lite_clk\0axis_clk\0ref_clk";
> clocks = <0x03 0x47 0x03 0x47 0x18>;
> phy-mode = "sgmii";
> xlnx,rxcsum = <0x02>;
> xlnx,rxmem = <0x1000>;
> xlnx,txcsum = <0x02>;
> pcs-handle = <0x19>;
> phy-handle = <0x78>;
> dmas = <0x17 0x00 0x17 0x01>;
> dma-names = "tx_chan0\0rx_chan0";
> mac-address = [ff ff ff ff ff ff];
> managed = "in-band-status";
> phandle = <0x79>;
> mdio {
> #address-cells = <0x01>;
> #size-cells = <0x00>;
>
> phy@0 {
> compatible = "ethernet-phy-ieee802.3-c22";
> reg = <0x00>;
> phandle = <0x78>;
> };
>
> ethernet-phy@2 {
> device_type = "ethernet-phy";
> reg = <0x02>;
> phandle = <0x19>;
> };
> };
> };
> This DT node works with our board. "&dma" is the dma DT node and to
> test the second case where dma address and length included in the
> axienet reg's property as below "reg = <0x00 0x80000000 0x00 0x40000
> 0x0 0x80040000 0x0 0x1000>;"
>
> I did not observe any issue with above two cases. Used below command
> to validate the yaml using above DT node.
> make dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/xlnx,axi-
> ethernet.yaml
>
Hi Krzysztof, Can you please comment If above explanation is acceptable ?
I will address remaining review comments and send the next version.
Thanks,
Sarath
On 28/03/2023 14:52, Gaddam, Sarath Babu Naidu wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <[email protected]>
>> Sent: Tuesday, March 14, 2023 9:22 PM
>> To: Gaddam, Sarath Babu Naidu
>> <[email protected]>; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected]; linux-arm-
>> [email protected]; [email protected]; Sarangi,
>> Anirudha <[email protected]>; Katakam, Harini
>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>> convert bindings document to yaml
>>
>> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
>>> From: Radhey Shyam Pandey <[email protected]>
>>>
>>> Convert the bindings document for Xilinx AXI Ethernet Subsystem from
>>> txt to yaml. No changes to existing binding description.
>>>
>>
>> (...)
>>
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - xlnx,axi-ethernet-1.00.a
>>> + - xlnx,axi-ethernet-1.01.a
>>> + - xlnx,axi-ethernet-2.01.a
>>> +
>>> + reg:
>>> + description:
>>> + Address and length of the IO space, as well as the address
>>> + and length of the AXI DMA controller IO space, unless
>>> + axistream-connected is specified, in which case the reg
>>> + attribute of the node referenced by it is used.
>>
>> Did you test it with axistream-connected? The schema and description
>> feel contradictory and tests would point the issue.
>
> Thanks for review comments. We tested with axistream-connected and
> did not observe any errors. Do you anticipate any issues/errors ?
Yes, I anticipate errors. What you wrote here looks incorrect based on
the schema.
Also, See also my further comments (or you ignored them?).
You can come many months after my review to ask about details, to be
sure I will forget the topic.
Best regards,
Krzysztof
On 02/05/2023 12:09, Gaddam, Sarath Babu Naidu wrote:
>
>
>> -----Original Message-----
>> From: Gaddam, Sarath Babu Naidu
>> <[email protected]>
>> Sent: Tuesday, March 28, 2023 9:31 PM
>> To: Krzysztof Kozlowski <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected]; linux-arm-
>> [email protected]; [email protected]; Sarangi,
>> Anirudha <[email protected]>; Katakam, Harini
>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>> convert bindings document to yaml
>>
>>
>>
>>> -----Original Message-----
>>> From: Gaddam, Sarath Babu Naidu
>>> <[email protected]>
>>> Sent: Tuesday, March 28, 2023 6:22 PM
>>> To: Krzysztof Kozlowski <[email protected]>;
>>> [email protected]; [email protected]; [email protected];
>>> [email protected]; [email protected];
>>> [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; linux-arm-
>>> [email protected]; [email protected]; Sarangi,
>>> Anirudha <[email protected]>; Katakam, Harini
>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>> convert bindings document to yaml
>>>
>>>
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <[email protected]>
>>>> Sent: Tuesday, March 14, 2023 9:22 PM
>>>> To: Gaddam, Sarath Babu Naidu
>>>> <[email protected]>; [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]
>>>> Cc: [email protected]; [email protected];
>>>> [email protected]; [email protected]; linux-arm-
>>>> [email protected]; [email protected]; Sarangi,
>>>> Anirudha <[email protected]>; Katakam, Harini
>>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>>> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>>> convert bindings document to yaml
>>>>
>>>> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
>>>>> From: Radhey Shyam Pandey <[email protected]>
>>>>>
>>>>> Convert the bindings document for Xilinx AXI Ethernet Subsystem
>>> from
>>>>> txt to yaml. No changes to existing binding description.
>>>>>
>>>>
>>>> (...)
>>>>
>>>>> +properties:
>>>>> + compatible:
>>>>> + enum:
>>>>> + - xlnx,axi-ethernet-1.00.a
>>>>> + - xlnx,axi-ethernet-1.01.a
>>>>> + - xlnx,axi-ethernet-2.01.a
>>>>> +
>>>>> + reg:
>>>>> + description:
>>>>> + Address and length of the IO space, as well as the address
>>>>> + and length of the AXI DMA controller IO space, unless
>>>>> + axistream-connected is specified, in which case the reg
>>>>> + attribute of the node referenced by it is used.
>>>>
>>>> Did you test it with axistream-connected? The schema and description
>>>> feel contradictory and tests would point the issue.
>>>
>>> Thanks for review comments. We tested with axistream-connected and
>> did
>>> not observe any errors. Do you anticipate any issues/errors ?
>>
>> Just to add more details, we have tested it using below dt node
>>
>> axienet@0 {
>> axistream-connected = <&dma>;
>> reg = <0x00 0x80000000 0x00 0x40000>;
>> compatible = "xlnx,axi-ethernet-2.01.a";
>> clock-names = "s_axi_lite_clk\0axis_clk\0ref_clk";
>> clocks = <0x03 0x47 0x03 0x47 0x18>;
>> phy-mode = "sgmii";
>> xlnx,rxcsum = <0x02>;
>> xlnx,rxmem = <0x1000>;
>> xlnx,txcsum = <0x02>;
>> pcs-handle = <0x19>;
>> phy-handle = <0x78>;
>> dmas = <0x17 0x00 0x17 0x01>;
>> dma-names = "tx_chan0\0rx_chan0";
>> mac-address = [ff ff ff ff ff ff];
>> managed = "in-band-status";
>> phandle = <0x79>;
>> mdio {
>> #address-cells = <0x01>;
>> #size-cells = <0x00>;
>>
>> phy@0 {
>> compatible = "ethernet-phy-ieee802.3-c22";
>> reg = <0x00>;
>> phandle = <0x78>;
>> };
>>
>> ethernet-phy@2 {
>> device_type = "ethernet-phy";
>> reg = <0x02>;
>> phandle = <0x19>;
>> };
>> };
>> };
>> This DT node works with our board. "&dma" is the dma DT node and to
>> test the second case where dma address and length included in the
>> axienet reg's property as below "reg = <0x00 0x80000000 0x00 0x40000
>> 0x0 0x80040000 0x0 0x1000>;"
>>
>> I did not observe any issue with above two cases. Used below command
>> to validate the yaml using above DT node.
>> make dtbs_check
>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/xlnx,axi-
>> ethernet.yaml
>>
>
> Hi Krzysztof, Can you please comment If above explanation is acceptable ?
> I will address remaining review comments and send the next version.
The DTS you pointed obviously cannot work with the binding - it has
obvious mistakes. Starting with phy-mode. So whatever you did, was not
correct testing. Since nothing from your code is upstream, I cannot
verify it.
Upstream your DTS first.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Tuesday, May 2, 2023 3:56 PM
> To: Gaddam, Sarath Babu Naidu
> <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Sarangi,
> Anirudha <[email protected]>; Katakam, Harini
> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> convert bindings document to yaml
>
> On 28/03/2023 14:52, Gaddam, Sarath Babu Naidu wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <[email protected]>
> >> Sent: Tuesday, March 14, 2023 9:22 PM
> >> To: Gaddam, Sarath Babu Naidu
> >> <[email protected]>; [email protected];
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]
> >> Cc: [email protected]; [email protected];
> >> [email protected]; [email protected]; linux-arm-
> >> [email protected]; [email protected]; Sarangi,
> >> Anirudha <[email protected]>; Katakam, Harini
> >> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> >> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> >> convert bindings document to yaml
> >>
> >> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
> >>> From: Radhey Shyam Pandey <[email protected]>
> >>>
> >>> Convert the bindings document for Xilinx AXI Ethernet Subsystem
> from
> >>> txt to yaml. No changes to existing binding description.
> >>>
> >>
> >> (...)
> >>
> >>> +properties:
> >>> + compatible:
> >>> + enum:
> >>> + - xlnx,axi-ethernet-1.00.a
> >>> + - xlnx,axi-ethernet-1.01.a
> >>> + - xlnx,axi-ethernet-2.01.a
> >>> +
> >>> + reg:
> >>> + description:
> >>> + Address and length of the IO space, as well as the address
> >>> + and length of the AXI DMA controller IO space, unless
> >>> + axistream-connected is specified, in which case the reg
> >>> + attribute of the node referenced by it is used.
> >>
> >> Did you test it with axistream-connected? The schema and description
> >> feel contradictory and tests would point the issue.
> >
> > Thanks for review comments. We tested with axistream-connected and
> did
> > not observe any errors. Do you anticipate any issues/errors ?
>
> Yes, I anticipate errors. What you wrote here looks incorrect based on the
> schema.
>
> Also, See also my further comments (or you ignored them?).
>
> You can come many months after my review to ask about details, to be
> sure I will forget the topic.
Hi Krzysztof, Apologies for miscommunication. I replied to this thread on
March 28 and said that I would address remaining review comments in
the next version.
Lore link:
https://lore.kernel.org/all/MW5PR12MB559880B0E220BDBD64E06D2487889@MW5PR12MB5598.namprd12.prod.outlook.com/
https://lore.kernel.org/all/MW5PR12MB5598678BB9AB6EC2FFC424F487889@MW5PR12MB5598.namprd12.prod.outlook.com/
I planned to send next version with phy-mode and pcs-handle maxItems
fixed.but I wanted to close on the axistream-connected discussion before
doing so.
Related to axistream-connected discussion:
I already ran dt binding check for schema and dts node validation. I assume
this should point any errors on it.
Thanks,
Sarath
> -----Original Message-----
> From: Gaddam, Sarath Babu Naidu
> Sent: Wednesday, May 3, 2023 3:01 PM
> To: Krzysztof Kozlowski <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Sarangi,
> Anirudha <[email protected]>; Katakam, Harini
> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> convert bindings document to yaml
>
>
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <[email protected]>
> > Sent: Tuesday, May 2, 2023 3:56 PM
> > To: Gaddam, Sarath Babu Naidu
> > <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; [email protected]; Sarangi,
> > Anirudha <[email protected]>; Katakam, Harini
> > <[email protected]>; git (AMD-Xilinx) <[email protected]>
> > Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> > convert bindings document to yaml
> >
> > On 28/03/2023 14:52, Gaddam, Sarath Babu Naidu wrote:
> > >
> > >
> > >> -----Original Message-----
> > >> From: Krzysztof Kozlowski <[email protected]>
> > >> Sent: Tuesday, March 14, 2023 9:22 PM
> > >> To: Gaddam, Sarath Babu Naidu
> > >> <[email protected]>; [email protected];
> > >> [email protected]; [email protected]; [email protected];
> > >> [email protected]; [email protected]
> > >> Cc: [email protected]; [email protected];
> > >> [email protected]; [email protected]; linux-arm-
> > >> [email protected]; [email protected]; Sarangi,
> > >> Anirudha <[email protected]>; Katakam, Harini
> > >> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> > >> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
> > >> convert bindings document to yaml
> > >>
> > >> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
> > >>> From: Radhey Shyam Pandey <[email protected]>
> > >>>
> > >>> Convert the bindings document for Xilinx AXI Ethernet Subsystem
> > from
> > >>> txt to yaml. No changes to existing binding description.
> > >>>
> > >>
> > >> (...)
> > >>
> > >>> +properties:
> > >>> + compatible:
> > >>> + enum:
> > >>> + - xlnx,axi-ethernet-1.00.a
> > >>> + - xlnx,axi-ethernet-1.01.a
> > >>> + - xlnx,axi-ethernet-2.01.a
> > >>> +
> > >>> + reg:
> > >>> + description:
> > >>> + Address and length of the IO space, as well as the address
> > >>> + and length of the AXI DMA controller IO space, unless
> > >>> + axistream-connected is specified, in which case the reg
> > >>> + attribute of the node referenced by it is used.
> > >>
> > >> Did you test it with axistream-connected? The schema and
> > >> description feel contradictory and tests would point the issue.
> > >
> > > Thanks for review comments. We tested with axistream-connected
> and
> > did
> > > not observe any errors. Do you anticipate any issues/errors ?
> >
> > Yes, I anticipate errors. What you wrote here looks incorrect based on
> > the schema.
> >
> > Also, See also my further comments (or you ignored them?).
> >
> > You can come many months after my review to ask about details, to be
> > sure I will forget the topic.
>
>
> Hi Krzysztof, Apologies for miscommunication. I replied to this thread on
> March 28 and said that I would address remaining review comments in
> the next version.
>
> Lore link:
> https://lore.kernel.org/all/MW5PR12MB559880B0E220BDBD64E06D24
> [email protected]/
> https://lore.kernel.org/all/MW5PR12MB5598678BB9AB6EC2FFC424F48
> [email protected]/
>
> I planned to send next version with phy-mode and pcs-handle maxItems
> fixed.but I wanted to close on the axistream-connected discussion before
> doing so.
>
> Related to axistream-connected discussion:
> I already ran dt binding check for schema and dts node validation. I
> assume this should point any errors on it.
>
Hi Krzysztof, Could you please comment on this ? Please let me if I missed
any changes or comments.
Thanks,
Sarath
On 18/05/2023 16:34, Krzysztof Kozlowski wrote:
> On 18/05/2023 08:17, Gaddam, Sarath Babu Naidu wrote:
>>
>>
>>> -----Original Message-----
>>> From: Gaddam, Sarath Babu Naidu
>>> Sent: Wednesday, May 3, 2023 3:01 PM
>>> To: Krzysztof Kozlowski <[email protected]>;
>>> [email protected]; [email protected]; [email protected];
>>> [email protected]; [email protected];
>>> [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; linux-arm-
>>> [email protected]; [email protected]; Sarangi,
>>> Anirudha <[email protected]>; Katakam, Harini
>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>> convert bindings document to yaml
>>>
>>>
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <[email protected]>
>>>> Sent: Tuesday, May 2, 2023 3:56 PM
>>>> To: Gaddam, Sarath Babu Naidu
>>>> <[email protected]>; [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]
>>>> Cc: [email protected]; [email protected];
>>>> [email protected]; [email protected]; linux-arm-
>>>> [email protected]; [email protected]; Sarangi,
>>>> Anirudha <[email protected]>; Katakam, Harini
>>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>>> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>>> convert bindings document to yaml
>>>>
>>>> On 28/03/2023 14:52, Gaddam, Sarath Babu Naidu wrote:
>>>>>
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Krzysztof Kozlowski <[email protected]>
>>>>>> Sent: Tuesday, March 14, 2023 9:22 PM
>>>>>> To: Gaddam, Sarath Babu Naidu
>>>>>> <[email protected]>; [email protected];
>>>>>> [email protected]; [email protected]; [email protected];
>>>>>> [email protected]; [email protected]
>>>>>> Cc: [email protected]; [email protected];
>>>>>> [email protected]; [email protected]; linux-arm-
>>>>>> [email protected]; [email protected]; Sarangi,
>>>>>> Anirudha <[email protected]>; Katakam, Harini
>>>>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>>>>> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>>>>> convert bindings document to yaml
>>>>>>
>>>>>> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
>>>>>>> From: Radhey Shyam Pandey <[email protected]>
>>>>>>>
>>>>>>> Convert the bindings document for Xilinx AXI Ethernet Subsystem
>>>> from
>>>>>>> txt to yaml. No changes to existing binding description.
>>>>>>>
>>>>>>
>>>>>> (...)
>>>>>>
>>>>>>> +properties:
>>>>>>> + compatible:
>>>>>>> + enum:
>>>>>>> + - xlnx,axi-ethernet-1.00.a
>>>>>>> + - xlnx,axi-ethernet-1.01.a
>>>>>>> + - xlnx,axi-ethernet-2.01.a
>>>>>>> +
>>>>>>> + reg:
>>>>>>> + description:
>>>>>>> + Address and length of the IO space, as well as the address
>>>>>>> + and length of the AXI DMA controller IO space, unless
>>>>>>> + axistream-connected is specified, in which case the reg
>>>>>>> + attribute of the node referenced by it is used.
>>>>>>
>>>>>> Did you test it with axistream-connected? The schema and
>>>>>> description feel contradictory and tests would point the issue.
>>>>>
>>>>> Thanks for review comments. We tested with axistream-connected
>>> and
>>>> did
>>>>> not observe any errors. Do you anticipate any issues/errors ?
>>>>
>>>> Yes, I anticipate errors. What you wrote here looks incorrect based on
>>>> the schema.
>>>>
>>>> Also, See also my further comments (or you ignored them?).
>>>>
>>>> You can come many months after my review to ask about details, to be
>>>> sure I will forget the topic.
>>>
>>>
>>> Hi Krzysztof, Apologies for miscommunication. I replied to this thread on
>>> March 28 and said that I would address remaining review comments in
>>> the next version.
>>>
>>> Lore link:
>>> https://lore.kernel.org/all/MW5PR12MB559880B0E220BDBD64E06D24
>>> [email protected]/
>>> https://lore.kernel.org/all/MW5PR12MB5598678BB9AB6EC2FFC424F48
>>> [email protected]/
>>>
>>> I planned to send next version with phy-mode and pcs-handle maxItems
>>> fixed.but I wanted to close on the axistream-connected discussion before
>>> doing so.
>>>
>>> Related to axistream-connected discussion:
>>> I already ran dt binding check for schema and dts node validation. I
>>> assume this should point any errors on it.
>
> And how do we know that you tested correct DTS with it?
>
>>>
>>
>> Hi Krzysztof, Could you please comment on this ? Please let me if I missed
>> any changes or comments.
>
> I don't think anything improved in this patchset. The binding has
> incomplete and I believe incorrect constraints for axistream-connected.
> You did not provide DTS to prove me otherwise. If you are not going to
> fix the issue nor provide DTS, what I can say more? Looks wrong.
I think my concerns would be solved if you extend the example with a
correct second possibility - device with axistream-connected. An
example, which will match all your constraints and all your descriptions
(we expect then not having any reg, right?).
Best regards,
Krzysztof
On 18/05/2023 08:17, Gaddam, Sarath Babu Naidu wrote:
>
>
>> -----Original Message-----
>> From: Gaddam, Sarath Babu Naidu
>> Sent: Wednesday, May 3, 2023 3:01 PM
>> To: Krzysztof Kozlowski <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]
>> Cc: [email protected]; [email protected];
>> [email protected]; [email protected]; linux-arm-
>> [email protected]; [email protected]; Sarangi,
>> Anirudha <[email protected]>; Katakam, Harini
>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>> Subject: RE: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>> convert bindings document to yaml
>>
>>
>>
>>> -----Original Message-----
>>> From: Krzysztof Kozlowski <[email protected]>
>>> Sent: Tuesday, May 2, 2023 3:56 PM
>>> To: Gaddam, Sarath Babu Naidu
>>> <[email protected]>; [email protected];
>>> [email protected]; [email protected]; [email protected];
>>> [email protected]; [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; linux-arm-
>>> [email protected]; [email protected]; Sarangi,
>>> Anirudha <[email protected]>; Katakam, Harini
>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>> convert bindings document to yaml
>>>
>>> On 28/03/2023 14:52, Gaddam, Sarath Babu Naidu wrote:
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: Krzysztof Kozlowski <[email protected]>
>>>>> Sent: Tuesday, March 14, 2023 9:22 PM
>>>>> To: Gaddam, Sarath Babu Naidu
>>>>> <[email protected]>; [email protected];
>>>>> [email protected]; [email protected]; [email protected];
>>>>> [email protected]; [email protected]
>>>>> Cc: [email protected]; [email protected];
>>>>> [email protected]; [email protected]; linux-arm-
>>>>> [email protected]; [email protected]; Sarangi,
>>>>> Anirudha <[email protected]>; Katakam, Harini
>>>>> <[email protected]>; git (AMD-Xilinx) <[email protected]>
>>>>> Subject: Re: [PATCH net-next V7] dt-bindings: net: xlnx,axi-ethernet:
>>>>> convert bindings document to yaml
>>>>>
>>>>> On 08/03/2023 07:12, Sarath Babu Naidu Gaddam wrote:
>>>>>> From: Radhey Shyam Pandey <[email protected]>
>>>>>>
>>>>>> Convert the bindings document for Xilinx AXI Ethernet Subsystem
>>> from
>>>>>> txt to yaml. No changes to existing binding description.
>>>>>>
>>>>>
>>>>> (...)
>>>>>
>>>>>> +properties:
>>>>>> + compatible:
>>>>>> + enum:
>>>>>> + - xlnx,axi-ethernet-1.00.a
>>>>>> + - xlnx,axi-ethernet-1.01.a
>>>>>> + - xlnx,axi-ethernet-2.01.a
>>>>>> +
>>>>>> + reg:
>>>>>> + description:
>>>>>> + Address and length of the IO space, as well as the address
>>>>>> + and length of the AXI DMA controller IO space, unless
>>>>>> + axistream-connected is specified, in which case the reg
>>>>>> + attribute of the node referenced by it is used.
>>>>>
>>>>> Did you test it with axistream-connected? The schema and
>>>>> description feel contradictory and tests would point the issue.
>>>>
>>>> Thanks for review comments. We tested with axistream-connected
>> and
>>> did
>>>> not observe any errors. Do you anticipate any issues/errors ?
>>>
>>> Yes, I anticipate errors. What you wrote here looks incorrect based on
>>> the schema.
>>>
>>> Also, See also my further comments (or you ignored them?).
>>>
>>> You can come many months after my review to ask about details, to be
>>> sure I will forget the topic.
>>
>>
>> Hi Krzysztof, Apologies for miscommunication. I replied to this thread on
>> March 28 and said that I would address remaining review comments in
>> the next version.
>>
>> Lore link:
>> https://lore.kernel.org/all/MW5PR12MB559880B0E220BDBD64E06D24
>> [email protected]/
>> https://lore.kernel.org/all/MW5PR12MB5598678BB9AB6EC2FFC424F48
>> [email protected]/
>>
>> I planned to send next version with phy-mode and pcs-handle maxItems
>> fixed.but I wanted to close on the axistream-connected discussion before
>> doing so.
>>
>> Related to axistream-connected discussion:
>> I already ran dt binding check for schema and dts node validation. I
>> assume this should point any errors on it.
And how do we know that you tested correct DTS with it?
>>
>
> Hi Krzysztof, Could you please comment on this ? Please let me if I missed
> any changes or comments.
I don't think anything improved in this patchset. The binding has
incomplete and I believe incorrect constraints for axistream-connected.
You did not provide DTS to prove me otherwise. If you are not going to
fix the issue nor provide DTS, what I can say more? Looks wrong.
Best regards,
Krzysztof