2023-09-22 08:58:02

by Gokul Sriram P

Subject: [PATCH V2 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

Add the APCS, A53 PLL, cpu-opp-table nodes to set
the CPU frequency at 800MHz (idle) or 1.008GHz.

Co-developed-by: Sricharan Ramabadhran <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 9f13d2dcdfd5..a04b2019c779 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
*/

+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
@@ -36,6 +37,8 @@ CPU0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};

CPU1: cpu@1 {
@@ -44,6 +47,8 @@ CPU1: cpu@1 {
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};

L2_0: l2-cache {
@@ -54,6 +59,23 @@ L2_0: l2-cache {
};
};

+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq5018", "qcom,scm";
@@ -181,6 +203,24 @@ v2m1: v2m@1000 {
};
};

+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq5018-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ };
+
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq5018-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
+ #mbox-cells = <1>;
+ };
+
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
--
2.34.1

2023-09-23 21:33:20

by Dmitry Baryshkov

Subject: Re: [PATCH V2 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

On Fri, 22 Sept 2023 at 11:44, Gokul Sriram Palanisamy
<[email protected]> wrote:
>
> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> the CPU frequency at 800MHz (idle) or 1.008GHz.
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 9f13d2dcdfd5..a04b2019c779 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -5,6 +5,7 @@
> * Copyright (c) 2023 The Linux Foundation. All rights reserved.
> */
>
> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
> reg = <0x0>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> + operating-points-v2 = <&cpu_opp_table>;
> };
>
> CPU1: cpu@1 {
> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
> reg = <0x1>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> + operating-points-v2 = <&cpu_opp_table>;
> };
>
> L2_0: l2-cache {
> @@ -54,6 +59,23 @@ L2_0: l2-cache {
> };
> };
>
> + cpu_opp_table: opp-table-cpu {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1008000000 {
> + opp-hz = /bits/ 64 <1008000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> firmware {
> scm {
> compatible = "qcom,scm-ipq5018", "qcom,scm";
> @@ -181,6 +203,24 @@ v2m1: v2m@1000 {
> };
> };
>
> + a53pll: clock@b116000 {
> + compatible = "qcom,ipq5018-a53pll";
> + reg = <0x0b116000 0x40>;
> + #clock-cells = <0>;
> + clocks = <&xo_board_clk>;
> + clock-names = "xo";
> + };
> +
> + apcs_glb: mailbox@b111000 {
> + compatible = "qcom,ipq5018-apcs-apps-global",
> + "qcom,ipq6018-apcs-apps-global";
> + reg = <0x0b111000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
> + clock-names = "pll", "xo", "gpll0";
> + #mbox-cells = <1>;
> + };

Hmm, no, I was too quick to R-B. 0xb111 < 0xb116, please change these two nodes.

> +
> timer@b120000 {
> compatible = "arm,armv7-timer-mem";
> reg = <0x0b120000 0x1000>;
> --
> 2.34.1
>


--
With best wishes
Dmitry

2023-09-24 04:13:54

by Dmitry Baryshkov

Subject: Re: [PATCH V2 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

On Fri, 22 Sept 2023 at 11:44, Gokul Sriram Palanisamy
<[email protected]> wrote:
>
> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> the CPU frequency at 800MHz (idle) or 1.008GHz.
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>


Reviewed-by: Dmitry Baryshkov <[email protected]>


--
With best wishes
Dmitry

2023-09-25 08:47:05

by Gokul Sriram P

Subject: Re: [PATCH V2 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

On 9/24/2023 12:45 AM, Dmitry Baryshkov wrote:
> On Fri, 22 Sept 2023 at 11:44, Gokul Sriram Palanisamy
> <[email protected]> wrote:
>> @@ -181,6 +203,24 @@ v2m1: v2m@1000 {
>> };
>> };
>>
>> + a53pll: clock@b116000 {
>> + compatible = "qcom,ipq5018-a53pll";
>> + reg = <0x0b116000 0x40>;
>> + #clock-cells = <0>;
>> + clocks = <&xo_board_clk>;
>> + clock-names = "xo";
>> + };
>> +
>> + apcs_glb: mailbox@b111000 {
>> + compatible = "qcom,ipq5018-apcs-apps-global",
>> + "qcom,ipq6018-apcs-apps-global";
>> + reg = <0x0b111000 0x1000>;
>> + #clock-cells = <1>;
>> + clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
>> + clock-names = "pll", "xo", "gpll0";
>> + #mbox-cells = <1>;
>> + };
> Hmm, no, I was too quick to R-B. 0xb111 < 0xb116, please change these two nodes.

Sure, will update and resend. Thanks.
Regards,
Gokul