From: Matthew Gerlach <[email protected]>
Add a device tree for the n6000 instantiation of Agilex
Hard Processor System (HPS).
Signed-off-by: Matthew Gerlach <[email protected]>
---
arch/arm64/boot/dts/intel/Makefile | 1 +
.../boot/dts/intel/socfpga_agilex_n6000.dts | 77 +++++++++++++++++++
2 files changed, 78 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 0b5477442263..1425853877cc 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
+ socfpga_agilex_n6000.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
new file mode 100644
index 000000000000..07f5a5983e5c
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2022, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex n6000";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ agilex_hps_bridges: bridge@80000000 {
+ compatible = "simple-bus";
+ reg = <0x80000000 0x60000000>,
+ <0xf9000000 0x00100000>;
+ reg-names = "axi_h2f", "axi_h2f_lw";
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+
+ uio_cp_eng@0xf9000000 {
+ compatible = "generic-uio";
+ reg = <0x00000000 0x00000000 0x00001000>;
+ status = "okay";
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ spidev: spidev@0 {
+ status = "okay";
+ compatible = "linux,spidev";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&fpga_mgr {
+ status = "disabled";
+};
--
2.25.1
On Mon, May 2, 2022 at 11:58 AM <[email protected]> wrote:
>
> From: Matthew Gerlach <[email protected]>
>
> Add a device tree for the n6000 instantiation of Agilex
> Hard Processor System (HPS).
>
> Signed-off-by: Matthew Gerlach <[email protected]>
> ---
> arch/arm64/boot/dts/intel/Makefile | 1 +
> .../boot/dts/intel/socfpga_agilex_n6000.dts | 77 +++++++++++++++++++
> 2 files changed, 78 insertions(+)
> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index 0b5477442263..1425853877cc 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
> socfpga_agilex_socdk_nand.dtb \
> + socfpga_agilex_n6000.dtb \
Alphabetical order.
> socfpga_n5x_socdk.dtb
> dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
> new file mode 100644
> index 000000000000..07f5a5983e5c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021-2022, Intel Corporation
> + */
> +#include "socfpga_agilex.dtsi"
> +
> +/ {
> + model = "SoCFPGA Agilex n6000";
> +
> + aliases {
> + serial0 = &uart1;
> + serial1 = &uart0;
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + ethernet2 = &gmac2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0 0 0>;
> + };
> +
> + soc {
> + clocks {
> + osc1 {
> + clock-frequency = <25000000>;
> + };
> + };
> + agilex_hps_bridges: bridge@80000000 {
> + compatible = "simple-bus";
> + reg = <0x80000000 0x60000000>,
> + <0xf9000000 0x00100000>;
> + reg-names = "axi_h2f", "axi_h2f_lw";
> + #address-cells = <0x2>;
> + #size-cells = <0x1>;
> + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
> +
> + uio_cp_eng@0xf9000000 {
Unit addresses shouldn't have '0x' and the address is wrong as it
should match the child address (0). dtc will tell you this though you
need 'W=1'. Run this and schema checks and don't add new warnings.
> + compatible = "generic-uio";
NAK. Not documented and that's because this is not a h/w device.
> + reg = <0x00000000 0x00000000 0x00001000>;
> + status = "okay";
That's the default.
> + };
> + };
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&spi0 {
> + status = "okay";
> +
> + spidev: spidev@0 {
> + status = "okay";
> + compatible = "linux,spidev";
> + spi-max-frequency = <25000000>;
> + reg = <0>;
> + };
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> +
> +&fpga_mgr {
> + status = "disabled";
> +};
> --
> 2.25.1
>
On 02/05/2022 18:58, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> Add a device tree for the n6000 instantiation of Agilex
> Hard Processor System (HPS).
>
> Signed-off-by: Matthew Gerlach <[email protected]>
> ---
> arch/arm64/boot/dts/intel/Makefile | 1 +
> .../boot/dts/intel/socfpga_agilex_n6000.dts | 77 +++++++++++++++++++
> 2 files changed, 78 insertions(+)
> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index 0b5477442263..1425853877cc 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
> socfpga_agilex_socdk_nand.dtb \
> + socfpga_agilex_n6000.dtb \
> socfpga_n5x_socdk.dtb
> dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
> new file mode 100644
> index 000000000000..07f5a5983e5c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
Except what Rob said: remove the indentation before license.
> +/*
> + * Copyright (C) 2021-2022, Intel Corporation
> + */
> +#include "socfpga_agilex.dtsi"
> +
> +/ {
> + model = "SoCFPGA Agilex n6000";
> +
> + aliases {
> + serial0 = &uart1;
> + serial1 = &uart0;
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac1;
> + ethernet2 = &gmac2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0 0 0>;
> + };
> +
> + soc {
> + clocks {
> + osc1 {
> + clock-frequency = <25000000>;
This does not look like SoC property... If it is part of Soc, why it is
not provided by clock controller? Where compatible?
If you intended to override nodes, override by label, not by path.
Best regards,
Krzysztof
On 02/05/2022 18:58, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> Add a device tree for the n6000 instantiation of Agilex
> Hard Processor System (HPS).
Please also use scripts/get_maintainer.pl to get the addresses. You
cc-ed here several wrong emails, so no one would pick up this patch.
Actually only my email is correct (except lists)...
Best regards,
Krzysztof
On Tue, 3 May 2022, Krzysztof Kozlowski wrote:
> On 02/05/2022 18:58, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> Add a device tree for the n6000 instantiation of Agilex
>> Hard Processor System (HPS).
>>
>> Signed-off-by: Matthew Gerlach <[email protected]>
>> ---
>> arch/arm64/boot/dts/intel/Makefile | 1 +
>> .../boot/dts/intel/socfpga_agilex_n6000.dts | 77 +++++++++++++++++++
>> 2 files changed, 78 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>>
>> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
>> index 0b5477442263..1425853877cc 100644
>> --- a/arch/arm64/boot/dts/intel/Makefile
>> +++ b/arch/arm64/boot/dts/intel/Makefile
>> @@ -1,5 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0-only
>> dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
>> socfpga_agilex_socdk_nand.dtb \
>> + socfpga_agilex_n6000.dtb \
>> socfpga_n5x_socdk.dtb
>> dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>> new file mode 100644
>> index 000000000000..07f5a5983e5c
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>> @@ -0,0 +1,77 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> Except what Rob said: remove the indentation before license.
Indentation will be removed. I noticed my checkpatch.pl execution was
failing due to missing python module, git. I installed the git module,
but the script didn't report an error.
>
>> +/*
>> + * Copyright (C) 2021-2022, Intel Corporation
>> + */
>> +#include "socfpga_agilex.dtsi"
>> +
>> +/ {
>> + model = "SoCFPGA Agilex n6000";
>> +
>> + aliases {
>> + serial0 = &uart1;
>> + serial1 = &uart0;
>> + ethernet0 = &gmac0;
>> + ethernet1 = &gmac1;
>> + ethernet2 = &gmac2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the reg */
>> + reg = <0 0 0 0>;
>> + };
>> +
>> + soc {
>> + clocks {
>> + osc1 {
>> + clock-frequency = <25000000>;
>
> This does not look like SoC property... If it is part of Soc, why it is
> not provided by clock controller? Where compatible?
>
> If you intended to override nodes, override by label, not by path.
I will make this change.
>
> Best regards,
> Krzysztof
>
Thank you for the review.
Matthew
On 02/05/2022 18:58, [email protected] wrote:
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021-2022, Intel Corporation
> + */
> +#include "socfpga_agilex.dtsi"
> +
> +/ {
> + model = "SoCFPGA Agilex n6000";
Where is the compatible?
Best regards,
Krzysztof
On Tue, 3 May 2022, Krzysztof Kozlowski wrote:
> On 02/05/2022 18:58, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> Add a device tree for the n6000 instantiation of Agilex
>> Hard Processor System (HPS).
>
> Please also use scripts/get_maintainer.pl to get the addresses. You
> cc-ed here several wrong emails, so no one would pick up this patch.
>
> Actually only my email is correct (except lists)...
I did run scripts/get_maintain.pl, but I still managed to mangle Dinh's
and Rob's email addresses. I will be extra, extra careful on the v2
submission.
Matthew
>
> Best regards,
> Krzysztof
>