---------- Forwarded message ----------
Date: Sun, 21 Jan 2024 00:55:25 +0800
From: kernel test robot <[email protected]>
To: [email protected]
Cc: [email protected], Julia Lawall <[email protected]>
Subject: drivers/clk/rockchip/clk-pll.c:912:2-8: WARNING: do_div() does a
64-by-32 division, please consider using div64_u64 instead.
BCC: [email protected]
CC: [email protected]
CC: [email protected]
TO: Elaine Zhang <[email protected]>
CC: Heiko Stuebner <[email protected]>
CC: Sebastian Reichel <[email protected]>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 9d64bf433c53cab2f48a3fff7a1f2a696bc5229a
commit: 8f6594494b1cb0ad14493795b436413cfe64a0f8 clk: rockchip: add pll type for RK3588
date: 1 year, 2 months ago
:::::: branch date: 18 hours ago
:::::: commit date: 1 year, 2 months ago
config: arm-randconfig-r062-20240117 (https://download.01.org/0day-ci/archive/20240121/[email protected]/config)
compiler: clang version 18.0.0git (https://github.com/llvm/llvm-project 9bde5becb44ea071f5e1fa1f5d4071dc8788b18c)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Reported-by: Julia Lawall <[email protected]>
| Closes: https://lore.kernel.org/r/[email protected]/
cocci warnings: (new ones prefixed by >>)
>> drivers/clk/rockchip/clk-pll.c:912:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
vim +912 drivers/clk/rockchip/clk-pll.c
8f6594494b1cb0 Elaine Zhang 2022-10-18 895
8f6594494b1cb0 Elaine Zhang 2022-10-18 896 static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
8f6594494b1cb0 Elaine Zhang 2022-10-18 897 {
8f6594494b1cb0 Elaine Zhang 2022-10-18 898 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
8f6594494b1cb0 Elaine Zhang 2022-10-18 899 struct rockchip_pll_rate_table cur;
8f6594494b1cb0 Elaine Zhang 2022-10-18 900 u64 rate64 = prate, postdiv;
8f6594494b1cb0 Elaine Zhang 2022-10-18 901
8f6594494b1cb0 Elaine Zhang 2022-10-18 902 rockchip_rk3588_pll_get_params(pll, &cur);
8f6594494b1cb0 Elaine Zhang 2022-10-18 903
8f6594494b1cb0 Elaine Zhang 2022-10-18 904 rate64 *= cur.m;
8f6594494b1cb0 Elaine Zhang 2022-10-18 905 do_div(rate64, cur.p);
8f6594494b1cb0 Elaine Zhang 2022-10-18 906
8f6594494b1cb0 Elaine Zhang 2022-10-18 907 if (cur.k) {
8f6594494b1cb0 Elaine Zhang 2022-10-18 908 /* fractional mode */
8f6594494b1cb0 Elaine Zhang 2022-10-18 909 u64 frac_rate64 = prate * cur.k;
8f6594494b1cb0 Elaine Zhang 2022-10-18 910
8f6594494b1cb0 Elaine Zhang 2022-10-18 911 postdiv = cur.p * 65535;
8f6594494b1cb0 Elaine Zhang 2022-10-18 @912 do_div(frac_rate64, postdiv);
8f6594494b1cb0 Elaine Zhang 2022-10-18 913 rate64 += frac_rate64;
8f6594494b1cb0 Elaine Zhang 2022-10-18 914 }
8f6594494b1cb0 Elaine Zhang 2022-10-18 915 rate64 = rate64 >> cur.s;
8f6594494b1cb0 Elaine Zhang 2022-10-18 916
8f6594494b1cb0 Elaine Zhang 2022-10-18 917 return (unsigned long)rate64;
8f6594494b1cb0 Elaine Zhang 2022-10-18 918 }
8f6594494b1cb0 Elaine Zhang 2022-10-18 919
--
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