Adds device tree and correspondent binding for ARM Corstone500 reference
solution.
Thanks for the comments, and sorry for the late reply. Most of the comments are
addressed except one.
@Krzysztof Kozlowski: Thanks a lot for the comments. I've tried to fixed all of
them. Just have one question regarding having no dtsi or compatible platform.
Corstone500 is a reference hardware design, however there is no silicon solution
from it yet. And from device tree perspective, both FPGA and FVP (virtual
platform) implementations are identical(same addresses and same nodes, etc.).
So we didn't want to create a seperate dtsi file. What would you recommend here
? Can you point me to a device tree from a similar platform?
Cheers,
Emek
Emekcan Aras (2):
arm: dts: arm: add arm corstone500 device tree
dt-bindings: Add Arm corstone500 platform
.../bindings/arm/arm,corstone500.yaml | 30 +++
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++
3 files changed, 214 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone500.yaml
create mode 100644 arch/arm/boot/dts/corstone500.dts
--
2.25.1
Add bindings to describe implementation of
the ARM Corstone500 platform.
Signed-off-by: Emekcan Aras <[email protected]>
---
.../bindings/arm/arm,corstone500.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone500.yaml
diff --git a/Documentation/devicetree/bindings/arm/arm,corstone500.yaml b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml
new file mode 100644
index 000000000000..cfe41f7760fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,corstone500.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Corstone500
+
+maintainers:
+ - Emekcan Aras <[email protected]>
+ - Rui Miguel Silva <[email protected]>
+
+description: |+
+ Corstone-500 is an ideal starting point for feature rich System on Chip
+ (SoC) designs based on the Cortex-A5 core. These designs can be used in
+ Internet of Things (IoT) and embedded products.
+
+ Corstone-500 includes most of the Arm IP in the SSE-500 subsystem and
+ example integration layer, an FPGA, and access to modelling options.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ items:
+ - const: arm,corstone500
+
+additionalProperties: true
+
+...
--
2.25.1
Corstone500[0] is a platform from arm, which includes Cortex-A cores and
ideal starting point for feature rich System on Chip (SoC) designs
based on the Cortex-A5 core.
These device trees contains the necessary bits to support the
Corstone 500 FVP (Fixed Virtual Platform) and the
FPGA MPS3 board.
0: https://developer.arm.com/documentation/102262/0000
Signed-off-by: Emekcan Aras <[email protected]>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++++++++++++++
2 files changed, 184 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/corstone500.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6aa7dc4db2fc..4dc4df0707dc 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1465,7 +1465,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca9.dtb \
vexpress-v2p-ca15-tc1.dtb \
- vexpress-v2p-ca15_a7.dtb
+ vexpress-v2p-ca15_a7.dtb \
+ corstone500.dtb
dtb-$(CONFIG_ARCH_VIRT) += \
xenvm-4.2.dtb
dtb-$(CONFIG_ARCH_VT8500) += \
diff --git a/arch/arm/boot/dts/corstone500.dts b/arch/arm/boot/dts/corstone500.dts
new file mode 100644
index 000000000000..bcca7d736c85
--- /dev/null
+++ b/arch/arm/boot/dts/corstone500.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ */
+
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "ARM Corstone500";
+ compatible = "arm,corstone500";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_on = <0x84000003>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "psci";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <2>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a5";
+ reg = <3>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x7f000000>;
+ };
+
+ L2: cache-controller@1c010000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1c010000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ cache-level = <2>;
+ cache-unified;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ };
+
+ refclk7500khz: clock-refclk7500khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <7500000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ refclk24mhz: clock-refclk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ smbclk: clock-refclk24mhzx2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ clock-output-names = "smclk";
+ };
+
+
+ gic: interrupt-controller@1c001000 {
+ compatible = "arm,cortex-a5-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1c001000 0x1000>,
+ <0x1c000100 0x100>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc{
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock_frequency = <50000000>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ uart0: serial@1a200000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a200000 0x1000>;
+ interrupts = <GIC_SPI 8 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&refclk7500khz>;
+ clock-names = "apb_pclk";
+ };
+
+ uart1: serial@1a210000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x1a210000 0x1000>;
+ interrupts = <GIC_SPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&refclk7500khz>;
+ clock-names = "apb_pclk";
+ };
+
+ timer0: timer@1a040000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x1a040000 0x1000>;
+ clock-frequency = <7500000>;
+
+ frame@1a050000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 2 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1a050000 0x1000>;
+ };
+ };
+
+ smsc: ethernet@4020000 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <0x40200000 0x10000>;
+ interrupts = <GIC_SPI 43 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ reg-io-width = <4>;
+ phy-mode = "mii";
+ smsc,irq-active-high;
+ vdd33a-supply = <&v2m_fixed_3v3>;
+ vddvario-supply = <&v2m_fixed_3v3>;
+ };
+
+ rtc@1a220000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x1a220000 0x1000>;
+ clocks = <&refclk24mhz>;
+ interrupts = <GIC_SPI 6 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ v2m_fixed_3v3: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
--
2.25.1
On 22/12/2022 13:32, Emekcan Aras wrote:
> Add bindings to describe implementation of
> the ARM Corstone500 platform.
>
> Signed-off-by: Emekcan Aras <[email protected]>
> ---
> .../bindings/arm/arm,corstone500.yaml | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone500.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,corstone500.yaml b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml
> new file mode 100644
> index 000000000000..cfe41f7760fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml
I don't think you solved my comments. Otherwise please point me how did
you solve this one:
"OK, so similar as Corstone 1000, but please tell me - any reason why
you keep them separate in the bindings? Next time new file for Corstone
1001, 1002, 2000, 2221 etc.?"
Best regards,
Krzysztof
On 22/12/2022 13:32, Emekcan Aras wrote:
> Adds device tree and correspondent binding for ARM Corstone500 reference
> solution.
>
> Thanks for the comments, and sorry for the late reply. Most of the comments are
> addressed except one.
>
> @Krzysztof Kozlowski: Thanks a lot for the comments. I've tried to fixed all of
> them. Just have one question regarding having no dtsi or compatible platform.
> Corstone500 is a reference hardware design, however there is no silicon solution
> from it yet. And from device tree perspective, both FPGA and FVP (virtual
> platform) implementations are identical(same addresses and same nodes, etc.).
> So we didn't want to create a seperate dtsi file. What would you recommend here
> ? Can you point me to a device tree from a similar platform?
Corstone1000 was accepted that way, so it is fine. I am just surprised
that if you are going to have silicons with it, there is no common
compatible and no shared DTSI.
What do you expect from customer? Re-implement and copy most of your DTS?
Best regards,
Krzysztof
On 22/12/2022 13:32, Emekcan Aras wrote:
> Corstone500[0] is a platform from arm, which includes Cortex-A cores and
> ideal starting point for feature rich System on Chip (SoC) designs
> based on the Cortex-A5 core.
Use subject prefixes matching the subsystem (git log --oneline -- ...).
You got this comment already and you did not follow it.
>
> These device trees contains the necessary bits to support the
> Corstone 500 FVP (Fixed Virtual Platform) and the
> FPGA MPS3 board.
>
> 0: https://developer.arm.com/documentation/102262/0000
>
> Signed-off-by: Emekcan Aras <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++++++++++++++
> 2 files changed, 184 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/corstone500.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6aa7dc4db2fc..4dc4df0707dc 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1465,7 +1465,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
> vexpress-v2p-ca5s.dtb \
> vexpress-v2p-ca9.dtb \
> vexpress-v2p-ca15-tc1.dtb \
> - vexpress-v2p-ca15_a7.dtb
> + vexpress-v2p-ca15_a7.dtb \
> + corstone500.dtb
Wrong order. v is not before c.
> dtb-$(CONFIG_ARCH_VIRT) += \
> xenvm-4.2.dtb
> dtb-$(CONFIG_ARCH_VT8500) += \
> diff --git a/arch/arm/boot/dts/corstone500.dts b/arch/arm/boot/dts/corstone500.dts
> new file mode 100644
> index 000000000000..bcca7d736c85
> --- /dev/null
> +++ b/arch/arm/boot/dts/corstone500.dts
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +/*
> + * Copyright (c) 2022, Arm Limited. All rights reserved.
> + *
> + */
> +
> +
Second ignored comment. I'll stop review.
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
On 22/12/2022 13:32, Emekcan Aras wrote:
> Adds device tree and correspondent binding for ARM Corstone500 reference
> solution.
>
> Thanks for the comments, and sorry for the late reply. Most of the comments are
> addressed except one.
>
> @Krzysztof Kozlowski: Thanks a lot for the comments. I've tried to fixed all of
> them. Just have one question regarding having no dtsi or compatible platform.
You still CC wrong addresses - at least mine, which suggests you base
your work on some old kernel.
Don't.
Please base on newest master, newest maintainer's tree or linux-next.
>
Best regards,
Krzysztof
On 22/12/2022 15:57, Emekcan Aras wrote:
> On 22/12/2022 13:32, Emekcan Aras wrote:
>> Corstone500[0] is a platform from arm, which includes Cortex-A cores and
>> ideal starting point for feature rich System on Chip (SoC) designs
>> based on the Cortex-A5 core.
>
> Use subject prefixes matching the subsystem (git log --oneline -- ...).
>
>
> You got this comment already and you did not follow it.
>
> Sorry, I'm new to kernel upstreaming. I thought I fixed this. Isn't this the correct subsystem prefixes:
> arm: dts: arm? Can you elaborate more? (git log --oneline -- ...) is not very clear for me.
Using git is nothing related to kernel upstreaming. Every other
development using Git... is using Git, so commands stay the same, right?
This is generic SW development. I gave you command to figure out proper
prefix, what else do you need from me? Link to manual on git log? (it's
`git help log`, BTW)
Best regards,
Krzysztof
On Thu, Dec 22, 2022 at 12:32:44PM +0000, Emekcan Aras wrote:
> Add bindings to describe implementation of
> the ARM Corstone500 platform.
>
> Signed-off-by: Emekcan Aras <[email protected]>
> ---
> .../bindings/arm/arm,corstone500.yaml | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone500.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,corstone500.yaml b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml
> new file mode 100644
> index 000000000000..cfe41f7760fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/arm,corstone500.yaml
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/arm,corstone500.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM Corstone500
It's 'Arm' now. :)
> +
> +maintainers:
> + - Emekcan Aras <[email protected]>
> + - Rui Miguel Silva <[email protected]>
> +
> +description: |+
> + Corstone-500 is an ideal starting point for feature rich System on Chip
> + (SoC) designs based on the Cortex-A5 core. These designs can be used in
> + Internet of Things (IoT) and embedded products.
> +
> + Corstone-500 includes most of the Arm IP in the SSE-500 subsystem and
> + example integration layer, an FPGA, and access to modelling options.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + items:
> + - const: arm,corstone500
> +
> +additionalProperties: true
> +
> +...
> --
> 2.25.1
>
>
On Thu, Dec 22, 2022 at 12:32:42PM +0000, Emekcan Aras wrote:
> Adds device tree and correspondent binding for ARM Corstone500 reference
> solution.
>
> Thanks for the comments, and sorry for the late reply. Most of the comments are
> addressed except one.
>
> @Krzysztof Kozlowski: Thanks a lot for the comments. I've tried to fixed all of
> them. Just have one question regarding having no dtsi or compatible platform.
> Corstone500 is a reference hardware design, however there is no silicon solution
> from it yet. And from device tree perspective, both FPGA and FVP (virtual
> platform) implementations are identical(same addresses and same nodes, etc.).
Does the FVP support virtio devices? Other FVP models do.
> So we didn't want to create a seperate dtsi file. What would you recommend here
> ? Can you point me to a device tree from a similar platform?
>
> Cheers,
> Emek
>
> Emekcan Aras (2):
> arm: dts: arm: add arm corstone500 device tree
> dt-bindings: Add Arm corstone500 platform
>
> .../bindings/arm/arm,corstone500.yaml | 30 +++
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++
> 3 files changed, 214 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,corstone500.yaml
> create mode 100644 arch/arm/boot/dts/corstone500.dts
>
> --
> 2.25.1
>
>
Hi Emekcan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on soc/for-next linus/master v6.1 next-20221220]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Emekcan-Aras/arm-dts-arm-add-arm-corstone500-device-tree/20221222-203639
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20221222123244.147238-2-emekcan.aras%40arm.com
patch subject: [PATCH v3 1/2] arm: dts: arm: add arm corstone500 device tree
config: arm-defconfig
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/4781faa7e3ce41843349d03c33e717d1b0e685e5
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Emekcan-Aras/arm-dts-arm-add-arm-corstone500-device-tree/20221222-203639
git checkout 4781faa7e3ce41843349d03c33e717d1b0e685e5
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/corstone500.dts:10.1-2 syntax error
FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi Emekcan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on soc/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.1 next-20221220]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Emekcan-Aras/arm-dts-arm-add-arm-corstone500-device-tree/20221222-203639
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20221222123244.147238-2-emekcan.aras%40arm.com
patch subject: [PATCH v3 1/2] arm: dts: arm: add arm corstone500 device tree
config: arm-randconfig-r046-20221218
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project 98b13979fb05f3ed288a900deb843e7b27589e58)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
# https://github.com/intel-lab-lkp/linux/commit/4781faa7e3ce41843349d03c33e717d1b0e685e5
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Emekcan-Aras/arm-dts-arm-add-arm-corstone500-device-tree/20221222-203639
git checkout 4781faa7e3ce41843349d03c33e717d1b0e685e5
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/corstone500.dts:10.1-2 syntax error
FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
On 22/12/2022 13:32, Emekcan Aras wrote:
> Corstone500[0] is a platform from arm, which includes Cortex-A cores and
> ideal starting point for feature rich System on Chip (SoC) designs
> based on the Cortex-A5 core.
>
> These device trees contains the necessary bits to support the
> Corstone 500 FVP (Fixed Virtual Platform) and the
> FPGA MPS3 board.
>
> 0: https://developer.arm.com/documentation/102262/0000
>
> Signed-off-by: Emekcan Aras <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++++++++++++++
> 2 files changed, 184 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/corstone500.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6aa7dc4db2fc..4dc4df0707dc 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1465,7 +1465,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
> vexpress-v2p-ca5s.dtb \
> vexpress-v2p-ca9.dtb \
> vexpress-v2p-ca15-tc1.dtb \
> - vexpress-v2p-ca15_a7.dtb
> + vexpress-v2p-ca15_a7.dtb \
> + corstone500.dtb
Why this is vexpress platform? If it is true, then add it to vexpress
bindings... It's confusingi and looks disorganized - some bindings here,
some platform there. Who is overseeing it? Who is maintaining? Who keeps
it consistent with other Arm platforms?
> dtb-$(CONFIG_ARCH_VIRT) += \
> xenvm-4.2.dtb
> dtb-$(CONFIG_ARCH_VT8500) += \
> diff --git a/arch/arm/boot/dts/corstone500.dts b/arch/arm/boot/dts/corstone500.dts
> new file mode 100644
> index 000000000000..bcca7d736c85
> --- /dev/null
> +++ b/arch/arm/boot/dts/corstone500.dts
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: GPL-2.0 or MIT
> +/*
> + * Copyright (c) 2022, Arm Limited. All rights reserved.
> + *
> + */
> +
> +
kbuild reports that patch does not build. :(
Except that other topics which you did not solve from previous case:
1. Missing maintainers entry
2. One binding file for your Corstone platforms, not for each of it.
3. failing `dtbs_check` (at least failing due to non-compiling DTS).
4. Subject prefix not matching other arm platforms.
Best regards,
Krzysztof
On Fri, Dec 23, 2022 at 09:26:54AM +0100, Krzysztof Kozlowski wrote:
> On 22/12/2022 13:32, Emekcan Aras wrote:
> > Corstone500[0] is a platform from arm, which includes Cortex-A cores and
> > ideal starting point for feature rich System on Chip (SoC) designs
> > based on the Cortex-A5 core.
> >
> > These device trees contains the necessary bits to support the
> > Corstone 500 FVP (Fixed Virtual Platform) and the
> > FPGA MPS3 board.
> >
> > 0: https://developer.arm.com/documentation/102262/0000
> >
> > Signed-off-by: Emekcan Aras <[email protected]>
> > ---
> > arch/arm/boot/dts/Makefile | 3 +-
> > arch/arm/boot/dts/corstone500.dts | 182 ++++++++++++++++++++++++++++++
> > 2 files changed, 184 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/boot/dts/corstone500.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 6aa7dc4db2fc..4dc4df0707dc 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -1465,7 +1465,8 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \
> > vexpress-v2p-ca5s.dtb \
> > vexpress-v2p-ca9.dtb \
> > vexpress-v2p-ca15-tc1.dtb \
> > - vexpress-v2p-ca15_a7.dtb
> > + vexpress-v2p-ca15_a7.dtb \
> > + corstone500.dtb
>
> Why this is vexpress platform? If it is true, then add it to vexpress
> bindings... It's confusingi and looks disorganized - some bindings here,
> some platform there. Who is overseeing it? Who is maintaining? Who keeps
> it consistent with other Arm platforms?
>
> > dtb-$(CONFIG_ARCH_VIRT) += \
> > xenvm-4.2.dtb
> > dtb-$(CONFIG_ARCH_VT8500) += \
> > diff --git a/arch/arm/boot/dts/corstone500.dts b/arch/arm/boot/dts/corstone500.dts
> > new file mode 100644
> > index 000000000000..bcca7d736c85
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/corstone500.dts
> > @@ -0,0 +1,182 @@
> > +// SPDX-License-Identifier: GPL-2.0 or MIT
> > +/*
> > + * Copyright (c) 2022, Arm Limited. All rights reserved.
> > + *
> > + */
> > +
> > +
>
> kbuild reports that patch does not build. :(
>
> Except that other topics which you did not solve from previous case:
> 1. Missing maintainers entry
> 2. One binding file for your Corstone platforms, not for each of it.
> 3. failing `dtbs_check` (at least failing due to non-compiling DTS).
> 4. Subject prefix not matching other arm platforms.
>
>
> Best regards,
> Krzysztof
>
Hi Krzysztof, sorry for the late reply. My mail client had an issue, and that's�
also the reason why I missed some of your comments before. Anyway, thanks for �
the comments. Ccorstone500 is currently in maintainance mode, and mostly used �
internally nowadays. I don't expect to see any corstone500 variance in the �
future. We just wanted to upstream few remaing patches on u-boot and kernel so �
that we don't need to keep rebasing the out-of-tree patches for never version �
upgrades. Also corstone500 normally uses device-tree in u-boot, however as you�
know we need to first upstream kernel device tree to be able upstream to u-boot�
device tree. Long story short, let me build this and test it throughly, to make�
sure everything is passing and make sure all your comments are addressed. Sorry�
for inconvience.�
�
Cheers,�
Emek�
Hi Emekcan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on soc/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.2-rc1 next-20221226]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Emekcan-Aras/arm-dts-arm-add-arm-corstone500-device-tree/20221222-203639
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20221222123244.147238-2-emekcan.aras%40arm.com
patch subject: [PATCH v3 1/2] arm: dts: arm: add arm corstone500 device tree
config: arm-defconfig
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/4781faa7e3ce41843349d03c33e717d1b0e685e5
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Emekcan-Aras/arm-dts-arm-add-arm-corstone500-device-tree/20221222-203639
git checkout 4781faa7e3ce41843349d03c33e717d1b0e685e5
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> Error: arch/arm/boot/dts/corstone500.dts:10.1-2 syntax error
>> FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp