Reading the DMA registers immediately after the reset causes
Data Bus Error. Adding a small delay fixes this issue.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
arch/mips/lantiq/xway/dma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 63dccb2ed08b..2784715933d1 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -11,6 +11,7 @@
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/of.h>
@@ -222,6 +223,8 @@ ltq_dma_init(struct platform_device *pdev)
clk_enable(clk);
ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
+ usleep_range(1, 10);
+
/* disable all interrupts */
ltq_dma_w32(0, LTQ_DMA_IRNEN);
--
2.30.2
The current definition of 2W burst length is invalid.
This patch fixes it. Current downstream DEU driver doesn't
use DMA. An incorrect burst length value doesn't cause any
errors. This patch also adds other burst length values.
Fixes: dfec1a827d2b ("MIPS: Lantiq: Add DMA support")
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
arch/mips/lantiq/xway/dma.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 364ab39eb8a4..53fcc672a294 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -41,7 +41,11 @@
#define DMA_IRQ_ACK 0x7e /* IRQ status register */
#define DMA_POLL BIT(31) /* turn on channel polling */
#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
-#define DMA_2W_BURST BIT(1) /* 2 word burst length */
+#define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
+#define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
+#define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
+#define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
+#define DMA_RX_BURST_SHIFT 2 /* rx burst shift */
#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
@@ -192,7 +196,8 @@ ltq_dma_init_port(int p)
break;
case DMA_PORT_DEU:
- ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
+ ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
+ (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
LTQ_DMA_PCTRL);
break;
--
2.30.2
Different SoCs have a different number of channels, e.g .:
* amazon-se has 10 channels,
* danube+ar9 have 20 channels,
* vr9 has 28 channels,
* ar10 has 24 channels.
We can read the ID register and, depending on the reported
number of channels, reset the appropriate number of channels.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
arch/mips/lantiq/xway/dma.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 2784715933d1..364ab39eb8a4 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -31,6 +31,7 @@
#define LTQ_DMA_PCTRL 0x44
#define LTQ_DMA_IRNEN 0xf4
+#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
#define DMA_DESCPT BIT(3) /* descriptor complete irq */
#define DMA_TX BIT(8) /* TX channel direction */
#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
@@ -41,7 +42,6 @@
#define DMA_POLL BIT(31) /* turn on channel polling */
#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
#define DMA_2W_BURST BIT(1) /* 2 word burst length */
-#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
@@ -207,7 +207,7 @@ ltq_dma_init(struct platform_device *pdev)
{
struct clk *clk;
struct resource *res;
- unsigned id;
+ unsigned int id, nchannels;
int i;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -229,17 +229,18 @@ ltq_dma_init(struct platform_device *pdev)
ltq_dma_w32(0, LTQ_DMA_IRNEN);
/* reset/configure each channel */
- for (i = 0; i < DMA_MAX_CHANNEL; i++) {
+ id = ltq_dma_r32(LTQ_DMA_ID);
+ nchannels = ((id & DMA_ID_CHNR) >> 20);
+ for (i = 0; i < nchannels; i++) {
ltq_dma_w32(i, LTQ_DMA_CS);
ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
}
- id = ltq_dma_r32(LTQ_DMA_ID);
dev_info(&pdev->dev,
"Init done - hw rev: %X, ports: %d, channels: %d\n",
- id & 0x1f, (id >> 16) & 0xf, id >> 20);
+ id & 0x1f, (id >> 16) & 0xf, nchannels);
return 0;
}
--
2.30.2
Make the burst length configurable by the drivers.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
.../include/asm/mach-lantiq/xway/xway_dma.h | 2 +-
arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++---
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
index 8218a1356bd8..31ca9151b539 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma_channel *ch);
extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
extern void ltq_dma_free(struct ltq_dma_channel *ch);
-extern void ltq_dma_init_port(int p);
+extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
#endif
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 53fcc672a294..f8eedeb15f18 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -182,7 +182,7 @@ ltq_dma_free(struct ltq_dma_channel *ch)
EXPORT_SYMBOL_GPL(ltq_dma_free);
void
-ltq_dma_init_port(int p)
+ltq_dma_init_port(int p, int tx_burst, int rx_burst)
{
ltq_dma_w32(p, LTQ_DMA_PS);
switch (p) {
@@ -191,16 +191,44 @@ ltq_dma_init_port(int p)
* Tell the DMA engine to swap the endianness of data frames and
* drop packets if the channel arbitration fails.
*/
- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
+ ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),
LTQ_DMA_PCTRL);
break;
- case DMA_PORT_DEU:
- ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
- (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
+ default:
+ break;
+ }
+
+ switch (rx_burst) {
+ case 8:
+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),
LTQ_DMA_PCTRL);
break;
+ case 4:
+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),
+ LTQ_DMA_PCTRL);
+ break;
+ case 2:
+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
+ LTQ_DMA_PCTRL);
+ break;
+ default:
+ break;
+ }
+ switch (tx_burst) {
+ case 8:
+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),
+ LTQ_DMA_PCTRL);
+ break;
+ case 4:
+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),
+ LTQ_DMA_PCTRL);
+ break;
+ case 2:
+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),
+ LTQ_DMA_PCTRL);
+ break;
default:
break;
}
--
2.30.2
Convert the Lantiq PMAC Device Tree binding documentation to json-schema.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
.../bindings/net/lantiq,xrx200-net.txt | 21 -------
.../bindings/net/lantiq,xrx200-net.yaml | 59 +++++++++++++++++++
2 files changed, 59 insertions(+), 21 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt
create mode 100644 Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
diff --git a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt
deleted file mode 100644
index 5ff5e68bbbb6..000000000000
--- a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Lantiq xRX200 GSWIP PMAC Ethernet driver
-==================================
-
-Required properties:
-
-- compatible : "lantiq,xrx200-net" for the PMAC of the embedded
- : GSWIP in the xXR200
-- reg : memory range of the PMAC core inside of the GSWIP core
-- interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for
- : the TX interrupt and "rx" for the RX interrupt.
-
-Example:
-
-ethernet@e10b308 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "lantiq,xrx200-net";
- reg = <0xe10b308 0xcf8>;
- interrupts = <73>, <72>;
- interrupt-names = "tx", "rx";
-};
diff --git a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
new file mode 100644
index 000000000000..7bc074a42369
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/lantiq,xrx200-net.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq xRX200 GSWIP PMAC Ethernet driver
+
+maintainers:
+ - Hauke Mehrtens <[email protected]>
+
+properties:
+ $nodename:
+ pattern: "^ethernet@[0-9a-f]+$"
+
+ compatible:
+ const: lantiq,xrx200-net
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: TX interrupt
+ - description: RX interrupt
+
+ interrupt-names:
+ items:
+ - const: tx
+ - const: rx
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupt-parent
+ - interrupts
+ - interrupt-names
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ ethernet@e10b308 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "lantiq,xrx200-net";
+ reg = <0xe10b308 0xcf8>;
+ interrupt-parent = <&icu0>;
+ interrupts = <73>, <72>;
+ interrupt-names = "tx", "rx";
+ };
--
2.30.2
Configure the burst length in Ethernet drivers. This improves
Ethernet performance by 58%. According to the vendor BSP,
8W burst length is supported by ar9 and newer SoCs.
The NAT benchmark results on xRX200 (Down/Up):
* 2W: 330 Mb/s
* 4W: 432 Mb/s 372 Mb/s
* 8W: 520 Mb/s 389 Mb/s
Tested on xRX200 and xRX330.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++---
drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++---
2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 62f8c5212182..2258e3f19161 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -96,6 +96,9 @@ struct ltq_etop_priv {
struct ltq_etop_chan ch[MAX_DMA_CHAN];
int tx_free[MAX_DMA_CHAN >> 1];
+ int tx_burst_len;
+ int rx_burst_len;
+
spinlock_t lock;
};
@@ -259,7 +262,7 @@ ltq_etop_hw_init(struct net_device *dev)
/* enable crc generation */
ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
- ltq_dma_init_port(DMA_PORT_ETOP);
+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);
for (i = 0; i < MAX_DMA_CHAN; i++) {
int irq = LTQ_DMA_CH0_INT + i;
@@ -472,8 +475,8 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
return NETDEV_TX_BUSY;
}
- /* dma needs to start on a 16 byte aligned address */
- byte_offset = CPHYSADDR(skb->data) % 16;
+ /* dma needs to start on a burst length value aligned address */
+ byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
ch->skb[ch->dma.desc] = skb;
netif_trans_update(dev);
@@ -667,6 +670,18 @@ ltq_etop_probe(struct platform_device *pdev)
spin_lock_init(&priv->lock);
SET_NETDEV_DEV(dev, &pdev->dev);
+ err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
+ if (err < 0) {
+ dev_err(&pdev->dev, "unable to read tx-burst-length property\n");
+ return err;
+ }
+
+ err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
+ if (err < 0) {
+ dev_err(&pdev->dev, "unable to read rx-burst-length property\n");
+ return err;
+ }
+
for (i = 0; i < MAX_DMA_CHAN; i++) {
if (IS_TX(i))
netif_napi_add(dev, &priv->ch[i].napi,
diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
index fb78f17d734f..5d96248ce83b 100644
--- a/drivers/net/ethernet/lantiq_xrx200.c
+++ b/drivers/net/ethernet/lantiq_xrx200.c
@@ -71,6 +71,9 @@ struct xrx200_priv {
struct net_device *net_dev;
struct device *dev;
+ int tx_burst_len;
+ int rx_burst_len;
+
__iomem void *pmac_reg;
};
@@ -316,8 +319,8 @@ static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
if (unlikely(dma_mapping_error(priv->dev, mapping)))
goto err_drop;
- /* dma needs to start on a 16 byte aligned address */
- byte_offset = mapping % 16;
+ /* dma needs to start on a burst length value aligned address */
+ byte_offset = mapping % (priv->tx_burst_len * 4);
desc->addr = mapping - byte_offset;
/* Make sure the address is written before we give it to HW */
@@ -369,7 +372,7 @@ static int xrx200_dma_init(struct xrx200_priv *priv)
int ret = 0;
int i;
- ltq_dma_init_port(DMA_PORT_ETOP);
+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);
ch_rx->dma.nr = XRX200_DMA_RX;
ch_rx->dma.dev = priv->dev;
@@ -478,6 +481,18 @@ static int xrx200_probe(struct platform_device *pdev)
if (err)
eth_hw_addr_random(net_dev);
+ err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
+ if (err < 0) {
+ dev_err(dev, "unable to read tx-burst-length property\n");
+ return err;
+ }
+
+ err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
+ if (err < 0) {
+ dev_err(dev, "unable to read rx-burst-length property\n");
+ return err;
+ }
+
/* bring up the dma engine and IP core */
err = xrx200_dma_init(priv);
if (err)
--
2.30.2
Document the Lantiq Xway SoC series External Bus Unit (ETOP) bindings.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
.../bindings/net/lantiq,etop-xway.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
diff --git a/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml b/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
new file mode 100644
index 000000000000..4412abfb4987
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq Xway ETOP Ethernet driver
+
+maintainers:
+ - John Crispin <[email protected]>
+
+properties:
+ $nodename:
+ pattern: "^ethernet@[0-9a-f]+$"
+
+ compatible:
+ const: lantiq,etop-xway
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: TX interrupt
+ - description: RX interrupt
+
+ interrupt-names:
+ items:
+ - const: tx
+ - const: rx
+
+ phy-mode: true
+
+required:
+ - compatible
+ - reg
+ - interrupt-parent
+ - interrupts
+ - interrupt-names
+ - phy-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ ethernet@e180000 {
+ compatible = "lantiq,etop-xway";
+ reg = <0xe180000 0x40000>;
+ interrupt-parent = <&icu0>;
+ interrupts = <73>, <78>;
+ interrupt-names = "tx", "rx";
+ phy-mode = "rmii";
+ };
--
2.30.2
The new added properties are used for configuring burst length.
Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
---
.../bindings/net/lantiq,etop-xway.yaml | 16 ++++++++++++++++
.../bindings/net/lantiq,xrx200-net.yaml | 16 ++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml b/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
index 4412abfb4987..437502c5ca96 100644
--- a/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
+++ b/Documentation/devicetree/bindings/net/lantiq,etop-xway.yaml
@@ -29,6 +29,18 @@ properties:
- const: tx
- const: rx
+ lantiq,tx-burst-length:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ TX programmable burst length.
+ enum: [2, 4, 8]
+
+ lantiq,rx-burst-length:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ RX programmable burst length.
+ enum: [2, 4, 8]
+
phy-mode: true
required:
@@ -37,6 +49,8 @@ required:
- interrupt-parent
- interrupts
- interrupt-names
+ - lantiq,tx-burst-length
+ - lantiq,rx-burst-length
- phy-mode
additionalProperties: false
@@ -49,5 +63,7 @@ examples:
interrupt-parent = <&icu0>;
interrupts = <73>, <78>;
interrupt-names = "tx", "rx";
+ lantiq,tx-burst-length = <8>;
+ lantiq,rx-burst-length = <8>;
phy-mode = "rmii";
};
diff --git a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
index 7bc074a42369..16d831f22063 100644
--- a/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
+++ b/Documentation/devicetree/bindings/net/lantiq,xrx200-net.yaml
@@ -29,6 +29,18 @@ properties:
- const: tx
- const: rx
+ lantiq,tx-burst-length:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ TX programmable burst length.
+ enum: [2, 4, 8]
+
+ lantiq,rx-burst-length:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ RX programmable burst length.
+ enum: [2, 4, 8]
+
'#address-cells':
const: 1
@@ -41,6 +53,8 @@ required:
- interrupt-parent
- interrupts
- interrupt-names
+ - lantiq,tx-burst-length
+ - lantiq,rx-burst-length
- "#address-cells"
- "#size-cells"
@@ -56,4 +70,6 @@ examples:
interrupt-parent = <&icu0>;
interrupts = <73>, <72>;
interrupt-names = "tx", "rx";
+ lantiq,tx-burst-length = <8>;
+ lantiq,rx-burst-length = <8>;
};
--
2.30.2
On 9/14/21 11:21 PM, Aleksander Jan Bajkowski wrote:
> Configure the burst length in Ethernet drivers. This improves
> Ethernet performance by 58%. According to the vendor BSP,
> 8W burst length is supported by ar9 and newer SoCs.
>
> The NAT benchmark results on xRX200 (Down/Up):
> * 2W: 330 Mb/s
> * 4W: 432 Mb/s 372 Mb/s
> * 8W: 520 Mb/s 389 Mb/s
>
> Tested on xRX200 and xRX330.
>
> Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
> ---
> drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++---
> drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++---
> 2 files changed, 36 insertions(+), 6 deletions(-)
>
.....
> diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
> index fb78f17d734f..5d96248ce83b 100644
> --- a/drivers/net/ethernet/lantiq_xrx200.c
> +++ b/drivers/net/ethernet/lantiq_xrx200.c
> @@ -71,6 +71,9 @@ struct xrx200_priv {
> struct net_device *net_dev;
> struct device *dev;
>
> + int tx_burst_len;
> + int rx_burst_len;
> +
> __iomem void *pmac_reg;
> };
>
> @@ -316,8 +319,8 @@ static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
> if (unlikely(dma_mapping_error(priv->dev, mapping)))
> goto err_drop;
>
> - /* dma needs to start on a 16 byte aligned address */
> - byte_offset = mapping % 16;
> + /* dma needs to start on a burst length value aligned address */
> + byte_offset = mapping % (priv->tx_burst_len * 4);
>
> desc->addr = mapping - byte_offset;
> /* Make sure the address is written before we give it to HW */
> @@ -369,7 +372,7 @@ static int xrx200_dma_init(struct xrx200_priv *priv)
> int ret = 0;
> int i;
>
> - ltq_dma_init_port(DMA_PORT_ETOP);
> + ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);
>
> ch_rx->dma.nr = XRX200_DMA_RX;
> ch_rx->dma.dev = priv->dev;
> @@ -478,6 +481,18 @@ static int xrx200_probe(struct platform_device *pdev)
> if (err)
> eth_hw_addr_random(net_dev);
>
> + err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
> + if (err < 0) {
> + dev_err(dev, "unable to read tx-burst-length property\n");
> + return err;
> + }
> +
> + err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
> + if (err < 0) {
> + dev_err(dev, "unable to read rx-burst-length property\n");
> + return err;
> + }
> +
I would prefer if you would hard code these values to 8 for the xrx200
driver. All SoCs with this IP block should support this.
> /* bring up the dma engine and IP core */
> err = xrx200_dma_init(priv);
> if (err)
>
Hauke
On 9/14/21 11:21 PM, Aleksander Jan Bajkowski wrote:
> Make the burst length configurable by the drivers.
>
> Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
Acked-by: Hauke Mehrtens <[email protected]>
For all 4 "MIPS: lantiq: dma:" changes.
> ---
> .../include/asm/mach-lantiq/xway/xway_dma.h | 2 +-
> arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++---
> 2 files changed, 34 insertions(+), 6 deletions(-)
>
The DMA changes are looking good.
There is also a DMA API driver for this IP core now:
https://elixir.bootlin.com/linux/v5.15-rc1/source/drivers/dma/lgm/lgm-dma.c
I do not know if it works fully with these older MIPS SoCs.
Changing the drivers to use the standard DMA API is a bigger change,
which could be done later.
Hauke
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Tue, 14 Sep 2021 23:20:58 +0200 you wrote:
> Reading the DMA registers immediately after the reset causes
> Data Bus Error. Adding a small delay fixes this issue.
>
> Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
> ---
> arch/mips/lantiq/xway/dma.c | 3 +++
> 1 file changed, 3 insertions(+)
Here is the summary with links:
- [net-next,1/8] MIPS: lantiq: dma: add small delay after reset
https://git.kernel.org/netdev/net-next/c/c12aa581f6d5
- [net-next,2/8] MIPS: lantiq: dma: reset correct number of channel
https://git.kernel.org/netdev/net-next/c/5ca9ce2ba4d5
- [net-next,3/8] MIPS: lantiq: dma: fix burst length for DEU
https://git.kernel.org/netdev/net-next/c/5ad74d39c51d
- [net-next,4/8] MIPS: lantiq: dma: make the burst length configurable by the drivers
https://git.kernel.org/netdev/net-next/c/49293bbc50cb
- [net-next,5/8] net: lantiq: configure the burst length in ethernet drivers
https://git.kernel.org/netdev/net-next/c/14d4e308e0aa
- [net-next,6/8] dt-bindings: net: lantiq-xrx200-net: convert to the json-schema
https://git.kernel.org/netdev/net-next/c/5535bcfa725a
- [net-next,7/8] dt-bindings: net: lantiq,etop-xway: Document Lantiq Xway ETOP bindings
https://git.kernel.org/netdev/net-next/c/dac0bad93741
- [net-next,8/8] dt-bindings: net: lantiq: Add the burst length properties
https://git.kernel.org/netdev/net-next/c/c68872146489
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
Hi Hauke,
On 9/15/21 12:36 AM, Hauke Mehrtens wrote:
> On 9/14/21 11:21 PM, Aleksander Jan Bajkowski wrote:
>> Configure the burst length in Ethernet drivers. This improves
>> Ethernet performance by 58%. According to the vendor BSP,
>> 8W burst length is supported by ar9 and newer SoCs.
>>
>> The NAT benchmark results on xRX200 (Down/Up):
>> * 2W: 330 Mb/s
>> * 4W: 432 Mb/s 372 Mb/s
>> * 8W: 520 Mb/s 389 Mb/s
>>
>> Tested on xRX200 and xRX330.
>>
>> Signed-off-by: Aleksander Jan Bajkowski <[email protected]>
>> ---
>> drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++---
>> drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++---
>> 2 files changed, 36 insertions(+), 6 deletions(-)
>>
> .....
>> diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
>> index fb78f17d734f..5d96248ce83b 100644
>> --- a/drivers/net/ethernet/lantiq_xrx200.c
>> +++ b/drivers/net/ethernet/lantiq_xrx200.c
>> @@ -71,6 +71,9 @@ struct xrx200_priv {
>> struct net_device *net_dev;
>> struct device *dev;
>> + int tx_burst_len;
>> + int rx_burst_len;
>> +
>> __iomem void *pmac_reg;
>> };
>> @@ -316,8 +319,8 @@ static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
>> if (unlikely(dma_mapping_error(priv->dev, mapping)))
>> goto err_drop;
>> - /* dma needs to start on a 16 byte aligned address */
>> - byte_offset = mapping % 16;
>> + /* dma needs to start on a burst length value aligned address */
>> + byte_offset = mapping % (priv->tx_burst_len * 4);
>> desc->addr = mapping - byte_offset;
>> /* Make sure the address is written before we give it to HW */
>> @@ -369,7 +372,7 @@ static int xrx200_dma_init(struct xrx200_priv *priv)
>> int ret = 0;
>> int i;
>> - ltq_dma_init_port(DMA_PORT_ETOP);
>> + ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);
>> ch_rx->dma.nr = XRX200_DMA_RX;
>> ch_rx->dma.dev = priv->dev;
>> @@ -478,6 +481,18 @@ static int xrx200_probe(struct platform_device *pdev)
>> if (err)
>> eth_hw_addr_random(net_dev);
>> + err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
>> + if (err < 0) {
>> + dev_err(dev, "unable to read tx-burst-length property\n");
>> + return err;
>> + }
>> +
>> + err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
>> + if (err < 0) {
>> + dev_err(dev, "unable to read rx-burst-length property\n");
>> + return err;
>> + }
>> +
>
> I would prefer if you would hard code these values to 8 for the xrx200 driver. All SoCs with this IP block should support this.
OK. I can hard code 8W burst length in the driver for xrx200. Burst length as a configurable parameter is really only needed in the lantiq_etop driver.
>
>> /* bring up the dma engine and IP core */
>> err = xrx200_dma_init(priv);
>> if (err)
>>
>
> Hauke
Aleksander