This series attempts to add devfreq support for imx8mm, covering dynamic
scaling of internal buses and dram.
Actual scaling is performed through the clk framework: The NOC and main
NICs are driven by composite clks and a new 'imx8m-dram' clk is used for
scaling dram using firmware calls.
Frequency target is set via "clk_set_min_rate", this allows an unrelated
subsystem (for example interconnect) to also request minimum rates as a
form for proactive scaling.
The dram controller (DDRC) has a performance monitoring block attached
for which a perf driver already exists. Instead of reimplementing that
as devfreq-events the perf in-kernel API is used.
Changes since v2:
* Solve review comments
* Add yaml binding doc
* Add perf event support
Link to v2: https://patchwork.kernel.org/patch/11021571/
DRAM frequency switching through clk framework is here:
* https://patchwork.kernel.org/patch/11049429/
That part might not be accepted in clk and it might have to be moved to
devfreq also.
Leonard Crestez (3):
dt-bindings: devfreq: Add initial bindings for i.MX
PM / devfreq: Add imx driver
PM / devfreq: Add imx perf event support
.../devicetree/bindings/devfreq/imx.yaml | 59 ++++
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/imx-devfreq.c | 278 ++++++++++++++++++
4 files changed, 348 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
create mode 100644 drivers/devfreq/imx-devfreq.c
--
2.17.1
Add initial dt bindings for the interconnects inside i.MX chips.
Multiple external IPs are involved but SOC integration means the
software controllable interfaces are very similar.
This is initially only for imx8mm but add an "fsl,imx-bus" fallback
similar to exynos-bus.
Signed-off-by: Leonard Crestez <[email protected]>
---
.../devicetree/bindings/devfreq/imx.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml
new file mode 100644
index 000000000000..87f90cddfd29
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/imx.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/imx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic i.MX bus frequency device
+
+maintainers:
+ - Leonard Crestez <[email protected]>
+
+description: |
+ The i.MX SoC family has multiple buses for which clock frequency (and sometimes
+ voltage) can be adjusted.
+
+ Some of those buses expose register areas mentioned in the memory maps as GPV
+ ("Global Programmers View") but not all. Access to this area might be denied for
+ normal world.
+
+ The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris
+ FlexNOC but DT bindings are specific to the integration of these bus
+ interconnect IPs into imx SOCs.
+
+properties:
+ reg:
+ maxItems: 1
+ description: GPV area
+
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8m-noc
+ - fsl,imx8m-nic
+ - fsl,imx8m-ddrc
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ ddrc: dram-controller@3d400000 {
+ compatible = "fsl,imx8mm-ddrc";
+ reg = <0x3d400000 0x400000>;
+ clocks = <&clk IMX8MM_CLK_DRAM>;
+ operating-points-v2 = <&ddrc_opp_table>;
+ };
+
+ - |
+ noc: noc@32700000 {
+ compatible = "fsl,imx8mm-noc";
+ reg = <0x32700000 0x100000>;
+ clocks = <&clk IMX8MM_CLK_NOC>;
+ operating-points-v2 = <&noc_opp_table>;
+ };
--
2.17.1
Hi,
2019년 7월 24일 (수) 오후 10:36, Leonard Crestez <[email protected]>님이 작성:
>
> Add initial dt bindings for the interconnects inside i.MX chips.
> Multiple external IPs are involved but SOC integration means the
> software controllable interfaces are very similar.
>
> This is initially only for imx8mm but add an "fsl,imx-bus" fallback
> similar to exynos-bus.
>
> Signed-off-by: Leonard Crestez <[email protected]>
> ---
> .../devicetree/bindings/devfreq/imx.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
>
> diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml
> new file mode 100644
> index 000000000000..87f90cddfd29
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/imx.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/devfreq/imx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Generic i.MX bus frequency device
> +
> +maintainers:
> + - Leonard Crestez <[email protected]>
> +
> +description: |
> + The i.MX SoC family has multiple buses for which clock frequency (and sometimes
> + voltage) can be adjusted.
> +
> + Some of those buses expose register areas mentioned in the memory maps as GPV
> + ("Global Programmers View") but not all. Access to this area might be denied for
> + normal world.
> +
> + The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris
> + FlexNOC but DT bindings are specific to the integration of these bus
> + interconnect IPs into imx SOCs.
> +
> +properties:
> + reg:
> + maxItems: 1
> + description: GPV area
> +
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8m-noc
> + - fsl,imx8m-nic
> + - fsl,imx8m-ddrc
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - clocks
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + ddrc: dram-controller@3d400000 {
> + compatible = "fsl,imx8mm-ddrc";
s/imx8mm/imx8m
> + reg = <0x3d400000 0x400000>;
> + clocks = <&clk IMX8MM_CLK_DRAM>;
> + operating-points-v2 = <&ddrc_opp_table>;
> + };
> +
> + - |
> + noc: noc@32700000 {
> + compatible = "fsl,imx8mm-noc";
s/imx8mm/imx8m
> + reg = <0x32700000 0x100000>;
> + clocks = <&clk IMX8MM_CLK_NOC>;
> + operating-points-v2 = <&noc_opp_table>;
> + };
> --
> 2.17.1
>
--
Best Regards,
Chanwoo Choi