This patchset adds aon power domain driver for the StarFive JH7110 SoC.
It is used to turn on/off dphy rx/tx power switch. The series has been
tested on the VisionFive 2 board.
This patchset should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/[email protected]/
changes since v1:
- Updated commit message.
- Changed "starfive,jh7110-pmu-dphy" to "starfive,jh7110-aon-pmu".
- Put if condition under allOf in .yaml file.
- Updated spelling error.
- Dropped patch 4: Add pmu type operation.
- Changed "jh71xx_pmu_general_set_state" to "jh7110_pmu_set_state" and moved it in call back.
- Changed "jh7110_pmu_general_parse_dt" to "jh7110_pmu_parse_dt" and moved it in call back.
- Used pmu_status save the pmu status offset.
- Changed "JH71XX_PMU_DPHY_SWITCH" to "JH71XX_AON_PMU_SWITCH"
- Changed copyright to "2022-2023"
v1: https://lore.kernel.org/all/[email protected]/
Changhuang Liang (6):
dt-bindings: power: Add JH7110 AON PMU support
soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
soc: starfive: Modify ioremap to regmap
soc: starfive: Extract JH7110 pmu private operations
soc: starfive: Add JH7110 AON PMU support
riscv: dts: starfive: jh7110: Add AON PMU node
.../bindings/power/starfive,jh7110-pmu.yaml | 15 +-
MAINTAINERS | 1 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +
drivers/soc/starfive/Kconfig | 4 +-
drivers/soc/starfive/jh71xx_pmu.c | 200 +++++++++++++-----
.../dt-bindings/power/starfive,jh7110-pmu.h | 3 +
6 files changed, 174 insertions(+), 54 deletions(-)
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
prerequisite-patch-id: 388b8adbb0fe2daf4d07a21eafd4f1bd50ce2403
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: b00c6b21fbd0353d88b7c9b09093ba30b765f45b
prerequisite-patch-id: 08ec9027e8a5c6fdf201726833168c7464a9b94d
prerequisite-patch-id: fb5120248e48fe1faf053ae0b490c92507ec2b44
prerequisite-patch-id: 4b93d8d590b0a2abe7b4be5287232c494c35be4a
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: c09c4c68af017b8e5c97b515cb50b70c18a2e705
prerequisite-patch-id: 0df8ccb0e848c2df4c2da95026494bebecede92d
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: d57cc467fb036241b9276320ff076c4a30d376d6
prerequisite-patch-id: 6e563d68bc5dbf951d4ced17897f9cc4d56169fe
prerequisite-patch-id: 61ec2caa21fd0fc60e57977f7d16d3f72b135745
prerequisite-patch-id: 1387a7e87b446329dfc21f3e575ceae7ebcf954c
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: 9007c8610fdcd387592475949864edde874c20a2
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
prerequisite-patch-id: c9bb2bf387954769731a627a195a2e957506d7c0
prerequisite-patch-id: 3b13e6bd0cb1fede74841bada2a50d30c8049198
prerequisite-patch-id: 3dc2fe994cb83e5bd1faac17b9e40e4d9adf9863
prerequisite-patch-id: 4c4d536c34d6cb607d4d00d4c982175d217832be
prerequisite-patch-id: dd12678b9cdcd6dccdb900c45fe1f6ce11d67fd5
prerequisite-patch-id: 284b5d1b95c6d68bca08db1e82ed14930c98b777
prerequisite-patch-id: 2c2daec388f036ebc8decfaeaa216d979d792c58
--
2.25.1
Move JH7110 private operation into private data of compatible.
Convenient to expand different compatible.
Signed-off-by: Changhuang Liang <[email protected]>
---
drivers/soc/starfive/jh71xx_pmu.c | 98 +++++++++++++++++++++----------
1 file changed, 67 insertions(+), 31 deletions(-)
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 306218c83691..bb44cc93e822 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -51,9 +51,17 @@ struct jh71xx_domain_info {
u8 bit;
};
+struct jh71xx_pmu;
+struct jh71xx_pmu_dev;
+
struct jh71xx_pmu_match_data {
const struct jh71xx_domain_info *domain_info;
int num_domains;
+ unsigned int pmu_status;
+ int (*pmu_parse_dt)(struct platform_device *pdev,
+ struct jh71xx_pmu *pmu);
+ int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd,
+ u32 mask, bool on);
};
struct jh71xx_pmu {
@@ -80,14 +88,14 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o
if (!mask)
return -EINVAL;
- regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val);
+ regmap_read(pmu->base, pmu->match_data->pmu_status, &val);
*is_on = val & mask;
return 0;
}
-static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
unsigned long flags;
@@ -95,22 +103,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
u32 mode;
u32 encourage_lo;
u32 encourage_hi;
- bool is_on;
int ret;
- ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
- if (ret) {
- dev_dbg(pmu->dev, "unable to get current state for %s\n",
- pmd->genpd.name);
- return ret;
- }
-
- if (is_on == on) {
- dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
- pmd->genpd.name, on ? "en" : "dis");
- return 0;
- }
-
spin_lock_irqsave(&pmu->lock, flags);
/*
@@ -169,6 +163,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}
+static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ const struct jh71xx_pmu_match_data *match_data = pmu->match_data;
+ bool is_on;
+ int ret;
+
+ ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
+ if (ret) {
+ dev_dbg(pmu->dev, "unable to get current state for %s\n",
+ pmd->genpd.name);
+ return ret;
+ }
+
+ if (is_on == on) {
+ dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
+ pmd->genpd.name, on ? "en" : "dis");
+ return 0;
+ }
+
+ return match_data->pmu_set_state(pmd, mask, on);
+}
+
static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
{
struct jh71xx_pmu_dev *pmd = container_of(genpd,
@@ -229,6 +246,30 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
return IRQ_HANDLED;
}
+static int jh7110_pmu_parse_dt(struct platform_device *pdev, struct jh71xx_pmu *pmu)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ pmu->base = device_node_to_regmap(np);
+ if (IS_ERR(pmu->base))
+ return PTR_ERR(pmu->base);
+
+ pmu->irq = platform_get_irq(pdev, 0);
+ if (pmu->irq < 0)
+ return pmu->irq;
+
+ ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
+ 0, pdev->name, pmu);
+ if (ret)
+ dev_err(dev, "failed to request irq\n");
+
+ jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
+
+ return 0;
+}
+
static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
{
struct jh71xx_pmu_dev *pmd;
@@ -274,23 +315,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
if (!pmu)
return -ENOMEM;
- pmu->base = device_node_to_regmap(np);
- if (IS_ERR(pmu->base))
- return PTR_ERR(pmu->base);
-
- pmu->irq = platform_get_irq(pdev, 0);
- if (pmu->irq < 0)
- return pmu->irq;
-
- ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
- 0, pdev->name, pmu);
- if (ret)
- dev_err(dev, "failed to request irq\n");
+ spin_lock_init(&pmu->lock);
match_data = of_device_get_match_data(dev);
if (!match_data)
return -EINVAL;
+ ret = match_data->pmu_parse_dt(pdev, pmu);
+ if (ret) {
+ dev_err(dev, "failed to parse dt\n");
+ return ret;
+ }
+
pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
sizeof(struct generic_pm_domain *),
GFP_KERNEL);
@@ -310,9 +346,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
}
}
- spin_lock_init(&pmu->lock);
- jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
-
ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
if (ret) {
dev_err(dev, "failed to register genpd driver: %d\n", ret);
@@ -360,6 +393,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = {
static const struct jh71xx_pmu_match_data jh7110_pmu = {
.num_domains = ARRAY_SIZE(jh7110_power_domains),
.domain_info = jh7110_power_domains,
+ .pmu_status = JH71XX_PMU_CURR_POWER_MODE,
+ .pmu_parse_dt = jh7110_pmu_parse_dt,
+ .pmu_set_state = jh7110_pmu_set_state,
};
static const struct of_device_id jh71xx_pmu_of_match[] = {
--
2.25.1
Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY
rx/tx power switch, and it don't need the properties of reg and
interrupts.
Signed-off-by: Changhuang Liang <[email protected]>
---
.../bindings/power/starfive,jh7110-pmu.yaml | 15 +++++++++++++--
include/dt-bindings/power/starfive,jh7110-pmu.h | 3 +++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
index 98eb8b4110e7..c50507c38e14 100644
--- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
+++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml
@@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit
maintainers:
- Walker Chen <[email protected]>
+ - Changhuang Liang <[email protected]>
description: |
StarFive JH7110 SoC includes support for multiple power domains which can be
@@ -17,6 +18,7 @@ properties:
compatible:
enum:
- starfive,jh7110-pmu
+ - starfive,jh7110-aon-pmu
reg:
maxItems: 1
@@ -29,10 +31,19 @@ properties:
required:
- compatible
- - reg
- - interrupts
- "#power-domain-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-pmu
+ then:
+ required:
+ - reg
+ - interrupts
+
additionalProperties: false
examples:
diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h
index 132bfe401fc8..0bfd6700c144 100644
--- a/include/dt-bindings/power/starfive,jh7110-pmu.h
+++ b/include/dt-bindings/power/starfive,jh7110-pmu.h
@@ -14,4 +14,7 @@
#define JH7110_PD_ISP 5
#define JH7110_PD_VENC 6
+#define JH7110_PD_DPHY_TX 0
+#define JH7110_PD_DPHY_RX 1
+
#endif
--
2.25.1
Add starfive,jh7110-aon-pmu node to configure power. It can be used to
turn on/off dphy rx/tx power switch.
Reviewed-by: Walker Chen <[email protected]>
Signed-off-by: Changhuang Liang <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index f271c3184d3a..b72cb54f0373 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -499,6 +499,11 @@ aoncrg: clock-controller@17000000 {
aon_syscon: syscon@17010000 {
compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
reg = <0x0 0x17010000 0x0 0x1000>;
+
+ aon_pwrc: power-controller {
+ compatible = "starfive,jh7110-aon-pmu";
+ #power-domain-cells = <1>;
+ };
};
aongpio: pinctrl@17020000 {
--
2.25.1
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
dphy rx/tx power switch.
Reviewed-by: Walker Chen <[email protected]>
Signed-off-by: Changhuang Liang <[email protected]>
---
MAINTAINERS | 1 +
drivers/soc/starfive/jh71xx_pmu.c | 63 ++++++++++++++++++++++++++++++-
2 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fafeea8ebdb..8f32d43a9b67 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19950,6 +19950,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h
STARFIVE JH71XX PMU CONTROLLER DRIVER
M: Walker Chen <[email protected]>
+M: Changhuang Liang <[email protected]>
S: Supported
F: Documentation/devicetree/bindings/power/starfive*
F: drivers/soc/starfive/jh71xx_pmu.c
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index bb44cc93e822..1303826aa7b5 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -2,7 +2,7 @@
/*
* StarFive JH71XX PMU (Power Management Unit) Controller Driver
*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
*/
#include <linux/interrupt.h>
@@ -24,6 +24,9 @@
#define JH71XX_PMU_EVENT_STATUS 0x88
#define JH71XX_PMU_INT_STATUS 0x8C
+/* aon pmu register offset */
+#define JH71XX_AON_PMU_SWITCH 0x00
+
/* sw encourage cfg */
#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
@@ -163,6 +166,23 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
return 0;
}
+static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+{
+ struct jh71xx_pmu *pmu = pmd->pmu;
+ unsigned long flags;
+
+ spin_lock_irqsave(&pmu->lock, flags);
+
+ if (on)
+ regmap_update_bits(pmu->base, JH71XX_AON_PMU_SWITCH, mask, mask);
+ else
+ regmap_update_bits(pmu->base, JH71XX_AON_PMU_SWITCH, mask, 0);
+
+ spin_unlock_irqrestore(&pmu->lock, flags);
+
+ return 0;
+}
+
static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
@@ -270,6 +290,24 @@ static int jh7110_pmu_parse_dt(struct platform_device *pdev, struct jh71xx_pmu *
return 0;
}
+static int jh7110_aon_pmu_parse_dt(struct platform_device *pdev, struct jh71xx_pmu *pmu)
+{
+ struct device *parent;
+ struct device *dev = &pdev->dev;
+
+ parent = pdev->dev.parent;
+ if (!parent) {
+ dev_err(dev, "No parent for syscon pmu\n");
+ return -ENODEV;
+ }
+
+ pmu->base = syscon_node_to_regmap(parent->of_node);
+ if (IS_ERR(pmu->base))
+ return PTR_ERR(pmu->base);
+
+ return 0;
+}
+
static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
{
struct jh71xx_pmu_dev *pmd;
@@ -398,10 +436,32 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = {
.pmu_set_state = jh7110_pmu_set_state,
};
+static const struct jh71xx_domain_info jh7110_aon_power_domains[] = {
+ [JH7110_PD_DPHY_TX] = {
+ .name = "DPHY-TX",
+ .bit = 30,
+ },
+ [JH7110_PD_DPHY_RX] = {
+ .name = "DPHY-RX",
+ .bit = 31,
+ },
+};
+
+static const struct jh71xx_pmu_match_data jh7110_aon_pmu = {
+ .num_domains = ARRAY_SIZE(jh7110_aon_power_domains),
+ .domain_info = jh7110_aon_power_domains,
+ .pmu_status = JH71XX_AON_PMU_SWITCH,
+ .pmu_parse_dt = jh7110_aon_pmu_parse_dt,
+ .pmu_set_state = jh7110_aon_pmu_set_state,
+};
+
static const struct of_device_id jh71xx_pmu_of_match[] = {
{
.compatible = "starfive,jh7110-pmu",
.data = (void *)&jh7110_pmu,
+ }, {
+ .compatible = "starfive,jh7110-aon-pmu",
+ .data = (void *)&jh7110_aon_pmu,
}, {
/* sentinel */
}
@@ -418,5 +478,6 @@ static struct platform_driver jh71xx_pmu_driver = {
builtin_platform_driver(jh71xx_pmu_driver);
MODULE_AUTHOR("Walker Chen <[email protected]>");
+MODULE_AUTHOR("Changhuang Liang <[email protected]>");
MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
MODULE_LICENSE("GPL");
--
2.25.1
Modify ioremap to regmap which can be compatible with the syscon
interface, such as:
struct regmap *syscon_node_to_regmap(struct device_node *np)
Convenient introduction of syscon operation.
Signed-off-by: Changhuang Liang <[email protected]>
---
drivers/soc/starfive/jh71xx_pmu.c | 43 +++++++++++++++++--------------
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c
index 7d5f50d71c0d..306218c83691 100644
--- a/drivers/soc/starfive/jh71xx_pmu.c
+++ b/drivers/soc/starfive/jh71xx_pmu.c
@@ -6,13 +6,13 @@
*/
#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
+#include <linux/regmap.h>
#include <dt-bindings/power/starfive,jh7110-pmu.h>
/* register offset */
@@ -59,7 +59,7 @@ struct jh71xx_pmu_match_data {
struct jh71xx_pmu {
struct device *dev;
const struct jh71xx_pmu_match_data *match_data;
- void __iomem *base;
+ struct regmap *base;
struct generic_pm_domain **genpd;
struct genpd_onecell_data genpd_data;
int irq;
@@ -75,11 +75,14 @@ struct jh71xx_pmu_dev {
static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
{
struct jh71xx_pmu *pmu = pmd->pmu;
+ unsigned int val;
if (!mask)
return -EINVAL;
- *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
+ regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val);
+
+ *is_on = val & mask;
return 0;
}
@@ -130,7 +133,7 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI;
}
- writel(mask, pmu->base + mode);
+ regmap_write(pmu->base, mode, mask);
/*
* 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44)
@@ -140,21 +143,21 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
* Then write the lower bits of the command sequence, followed by the upper
* bits. The sequence differs between powering on & off a domain.
*/
- writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
- writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
- writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
+ regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, JH71XX_PMU_SW_ENCOURAGE_ON);
+ regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_lo);
+ regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_hi);
spin_unlock_irqrestore(&pmu->lock, flags);
/* Wait for the power domain bit to be enabled / disabled */
if (on) {
- ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
- val, val & mask,
- 1, JH71XX_PMU_TIMEOUT_US);
+ ret = regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER_MODE,
+ val, val & mask,
+ 1, JH71XX_PMU_TIMEOUT_US);
} else {
- ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
- val, !(val & mask),
- 1, JH71XX_PMU_TIMEOUT_US);
+ ret = regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER_MODE,
+ val, !(val & mask),
+ 1, JH71XX_PMU_TIMEOUT_US);
}
if (ret) {
@@ -190,14 +193,14 @@ static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
unsigned long flags;
spin_lock_irqsave(&pmu->lock, flags);
- val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK);
+ regmap_read(pmu->base, JH71XX_PMU_TIMER_INT_MASK, &val);
if (enable)
val &= ~mask;
else
val |= mask;
- writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
+ regmap_write(pmu->base, JH71XX_PMU_TIMER_INT_MASK, val);
spin_unlock_irqrestore(&pmu->lock, flags);
}
@@ -206,7 +209,7 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
struct jh71xx_pmu *pmu = data;
u32 val;
- val = readl(pmu->base + JH71XX_PMU_INT_STATUS);
+ regmap_read(pmu->base, JH71XX_PMU_INT_STATUS, &val);
if (val & JH71XX_PMU_INT_SEQ_DONE)
dev_dbg(pmu->dev, "sequence done.\n");
@@ -220,8 +223,8 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
dev_err(pmu->dev, "p-channel fail event.\n");
/* clear interrupts */
- writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
- writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
+ regmap_write(pmu->base, JH71XX_PMU_INT_STATUS, val);
+ regmap_write(pmu->base, JH71XX_PMU_EVENT_STATUS, val);
return IRQ_HANDLED;
}
@@ -271,7 +274,7 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
if (!pmu)
return -ENOMEM;
- pmu->base = devm_platform_ioremap_resource(pdev, 0);
+ pmu->base = device_node_to_regmap(np);
if (IS_ERR(pmu->base))
return PTR_ERR(pmu->base);
--
2.25.1
Using ARCH_FOO symbol is preferred than SOC_FOO.
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Walker Chen <[email protected]>
Signed-off-by: Changhuang Liang <[email protected]>
---
drivers/soc/starfive/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
index bdb96dc4c989..1e9b0c414fec 100644
--- a/drivers/soc/starfive/Kconfig
+++ b/drivers/soc/starfive/Kconfig
@@ -3,8 +3,8 @@
config JH71XX_PMU
bool "Support PMU for StarFive JH71XX Soc"
depends on PM
- depends on SOC_STARFIVE || COMPILE_TEST
- default SOC_STARFIVE
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ default ARCH_STARFIVE
select PM_GENERIC_DOMAINS
help
Say 'y' here to enable support power domain support.
--
2.25.1
On 19/04/2023 05:48, Changhuang Liang wrote:
> Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY
> rx/tx power switch, and it don't need the properties of reg and
> interrupts.
>
> Signed-off-by: Changhuang Liang <[email protected]>
> ---
> .../bindings/power/starfive,jh7110-pmu.yaml | 15 +++++++++++++
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof