LinuxLists.cc - [PATCH 0/7] soc: imx: Enable additional functionality of i.MX8M

2019-12-05 02:20:23

Subject: [PATCH 0/7] soc: imx: Enable additional functionality of i.MX8M

The GPCv2 controller on the i.MX8M Mini is compatible with the driver
used for the i.MX8MQ except for the register locations and names.
The GPCv2 controller is used to enable additional periperals currently
unavailable on the i.MX8M Mini. In order to make them function,
the GPCv2 needs to be adapted so the drivers can associate their
power domain to the GPCv2 to enable them.

This series makes one include file slightly more generic,
adds the iMX8M Mini entries, updates the bindings, adds them
to the device tree, then associates the new power domain to
both the OTG and PCIe controllers.

Adam Ford (7):
soc: imx: gpcv2: Rename imx8mq-power.h to imx8m-power.h
soc: imx: gpcv2: Update imx8m-power.h to include iMX8M Mini
soc: imx: gpcv2: add support for i.MX8M Mini SoC
dt-bindings: imx-gpcv2: Update bindings to support i.MX8M Mini
arm64: dts: imx8mm: add GPC power domains
ARM64: dts: imx8mm: Fix clocks and power domain for USB OTG
arm64: dts: imx8mm: Add PCIe support

.../bindings/power/fsl,imx-gpcv2.txt | 6 +-
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 129 ++++++++-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
drivers/soc/imx/gpcv2.c | 246 +++++++++++++++++-
.../power/{imx8mq-power.h => imx8m-power.h} | 14 +
5 files changed, 389 insertions(+), 8 deletions(-)
rename include/dt-bindings/power/{imx8mq-power.h => imx8m-power.h} (57%)

--
2.20.1

2019-12-05 02:20:27

by Adam Ford

[permalink] [raw]

Subject: [PATCH 2/7] soc: imx: gpcv2: Update imx8m-power.h to include iMX8M Mini

In preparation for i.MX8M Mini support in the GPC driver, the
include file used by both the device tree and the source needs to
have the appropriate references for it.

Signed-off-by: Adam Ford <[email protected]>
---
include/dt-bindings/power/imx8m-power.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/include/dt-bindings/power/imx8m-power.h b/include/dt-bindings/power/imx8m-power.h
index 8a513bd9166e..0054bba744b8 100644
--- a/include/dt-bindings/power/imx8m-power.h
+++ b/include/dt-bindings/power/imx8m-power.h
@@ -18,4 +18,18 @@
#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9
#define IMX8M_POWER_DOMAIN_PCIE2 10

+#define IMX8MM_POWER_DOMAIN_MIPI 0
+#define IMX8MM_POWER_DOMAIN_PCIE 1
+#define IMX8MM_POWER_DOMAIN_USB_OTG1 2
+#define IMX8MM_POWER_DOMAIN_USB_OTG2 3
+#define IMX8MM_POWER_DOMAIN_DDR1 4
+#define IMX8MM_POWER_DOMAIN_GPU2D 5
+#define IMX8MM_POWER_DOMAIN_GPU 6
+#define IMX8MM_POWER_DOMAIN_VPU 7
+#define IMX8MM_POWER_DOMAIN_GPU3D 8
+#define IMX8MM_POWER_DOMAIN_DISP 9
+#define IMX8MM_POWER_VPU_G1 10
+#define IMX8MM_POWER_VPU_G2 11
+#define IMX8MM_POWER_VPU_H1 12
+
#endif
--
2.20.1

2019-12-05 02:20:32

by Adam Ford

[permalink] [raw]

Subject: [PATCH 3/7] soc: imx: gpcv2: add support for i.MX8M Mini SoC

The GPCv2 on the Freescale i.MX8M Mini SoC works in the same way as the
GPCv2 on the i.MX8MQ, but with slightly different power domains and
mapping.

This patch adds the necessary tables so the GPC can operate on the
i.MX8M Mini.

Signed-off-by: Adam Ford <[email protected]>
---
drivers/soc/imx/gpcv2.c | 244 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 244 insertions(+)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 250f740d2314..52668e985e8e 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -41,6 +41,20 @@
#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
#define IMX8M_MIPI_A53_DOMAIN BIT(2)

+#define IMX8MM_VPU_H1_A53_DOMAIN BIT(15)
+#define IMX8MM_VPU_G2_A53_DOMAIN BIT(14)
+#define IMX8MM_VPU_G1_A53_DOMAIN BIT(13)
+#define IMX8MM_DISP_MIX_A53_DOMAIN BIT(12)
+#define IMX8MM_GPU_3D_A53_DOMAIN BIT(11)
+#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
+#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
+#define IMX8MM_GPU_2D_A53_DOMAIN BIT(8)
+#define IMX8MM_DDR1_A53_DOMAIN BIT(7)
+#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
+#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
+#define IMX8MM_PCIE_A53_DOMAIN BIT(3)
+#define IMX8MM_MIPI_A53_DOMAIN BIT(2)
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104

@@ -64,6 +78,20 @@
#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)

+#define IMX8MM_VPU_H1_SW_Pxx_REQ BIT(13)
+#define IMX8MM_VPU_G2_SW_Pxx_REQ BIT(12)
+#define IMX8MM_VPU_G1_SW_Pxx_REQ BIT(11)
+#define IMX8MM_DISP_SW_Pxx_REQ BIT(10)
+#define IMX8MM_GPU_3D_SW_Pxx_REQ BIT(9)
+#define IMX8MM_VPU_SW_Pxx_REQ BIT(8)
+#define IMX8MM_GPU_SW_Pxx_REQ BIT(7)
+#define IMX8MM_GPU_2D_SW_PXX_REQ BIT(6)
+#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
+#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
+#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
+#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
+#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
+
#define GPC_M4_PU_PDN_FLG 0x1bc

#define GPC_PU_PWRHSK 0x1fc
@@ -72,6 +100,10 @@
#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)

+#define IMX8MM_GPU_HSK_PWRDNREQN BIT(9)
+#define IMX8MM_VPU_HSK_PWRDNREQN BIT(8)
+#define IMX8MM_DISP_HSK_PWRDNREQN BIT(7)
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -94,6 +126,24 @@
#define IMX8M_PGC_MIPI_CSI2 28
#define IMX8M_PGC_PCIE2 29

+/*
+ * Taken from i.MX8M Mini values from Reference
+ * Manual, Rev. 2, 08/2019
+ */
+#define IMX8MM_PGC_MIPI 16
+#define IMX8MM_PGC_PCIE 17
+#define IMX8MM_PGC_OTG1 18
+#define IMX8MM_PGC_OTG2 19
+#define IMX8MM_PGC_DDR1 21
+#define IMX8MM_PGC_GPU2D 22
+#define IMX8MM_PGC_GPU 23
+#define IMX8MM_PGC_VPU 24
+#define IMX8MM_PGC_GPU3D 25
+#define IMX8MM_PGC_DISP 26
+#define IMX8MM_PGC_VPU_G1 27
+#define IMX8MM_PGC_VPU_G2 28
+#define IMX8MM_PGC_VPU_H1 29
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)

@@ -278,6 +328,7 @@ static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
.reg_access_table = &imx7_access_table,
};

+/* i.MX8M dual/QuadLite/Quad */
static const struct imx_pgc_domain imx8m_pgc_domains[] = {
[IMX8M_POWER_DOMAIN_MIPI] = {
.genpd = {
@@ -442,6 +493,198 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.reg_access_table = &imx8m_access_table,
};

+/* i.MX8M Mini */
+static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
+ [IMX8MM_POWER_DOMAIN_MIPI] = {
+ .genpd = {
+ .name = "mipi",
+ },
+ .bits = {
+ .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
+ .map = IMX8MM_MIPI_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_MIPI,
+ },
+
+ [IMX8MM_POWER_DOMAIN_PCIE] = {
+ .genpd = {
+ .name = "pcie1",
+ },
+ .bits = {
+ .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
+ .map = IMX8MM_PCIE_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_PCIE,
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG1] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
+ .map = IMX8MM_OTG1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_OTG1,
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG2] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
+ .map = IMX8MM_OTG2_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_OTG2,
+ },
+
+ [IMX8MM_POWER_DOMAIN_DDR1] = {
+ .genpd = {
+ .name = "ddr1",
+ },
+ .bits = {
+ .pxx = IMX8MM_DDR1_SW_Pxx_REQ,
+ .map = IMX8MM_DDR1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_DDR1,
+ },
+
+ [IMX8MM_POWER_DOMAIN_GPU2D] = {
+ .genpd = {
+ .name = "gpu2d",
+ },
+ .bits = {
+ .pxx = IMX8MM_GPU_2D_SW_PXX_REQ,
+ .map = IMX8MM_GPU_2D_A53_DOMAIN,
+ .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
+ },
+ .pgc = IMX8MM_PGC_GPU2D,
+ },
+
+
+ [IMX8MM_POWER_DOMAIN_GPU] = {
+ .genpd = {
+ .name = "gpu",
+ },
+ .bits = {
+ .pxx = IMX8MM_GPU_SW_Pxx_REQ,
+ .map = IMX8MM_GPUMIX_A53_DOMAIN,
+ .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
+ },
+ .pgc = IMX8M_PGC_GPU,
+ },
+
+ [IMX8MM_POWER_DOMAIN_VPU] = {
+ .genpd = {
+ .name = "vpu",
+ },
+ .bits = {
+ .pxx = IMX8MM_VPU_SW_Pxx_REQ,
+ .map = IMX8MM_VPUMIX_A53_DOMAIN,
+ .hsk = IMX8MM_VPU_HSK_PWRDNREQN,
+ },
+ .pgc = IMX8M_PGC_VPU,
+ },
+
+ [IMX8MM_POWER_DOMAIN_GPU3D] = {
+ .genpd = {
+ .name = "gpu3d",
+ },
+ .bits = {
+ .pxx = IMX8MM_GPU_3D_SW_Pxx_REQ,
+ .map = IMX8MM_GPU_3D_A53_DOMAIN,
+ .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
+ },
+ .pgc = IMX8MM_PGC_GPU2D,
+ },
+
+ [IMX8MM_POWER_DOMAIN_DISP] = {
+ .genpd = {
+ .name = "disp",
+ },
+ .bits = {
+ .pxx = IMX8MM_DISP_SW_Pxx_REQ,
+ .map = IMX8MM_DISP_MIX_A53_DOMAIN,
+ .hsk = IMX8MM_DISP_HSK_PWRDNREQN,
+ },
+ .pgc = IMX8M_PGC_DISP,
+ },
+
+ [IMX8MM_POWER_VPU_G1] = {
+ .genpd = {
+ .name = "vpu_g1",
+ },
+ .bits = {
+ .pxx = IMX8MM_VPU_G1_SW_Pxx_REQ,
+ .map = IMX8MM_VPU_G1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_MIPI_CSI1,
+ },
+
+ [IMX8MM_POWER_VPU_G2] = {
+ .genpd = {
+ .name = "vpu_g2",
+ },
+ .bits = {
+ .pxx = IMX8MM_VPU_G2_SW_Pxx_REQ,
+ .map = IMX8MM_VPU_G2_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_MIPI_CSI2,
+ },
+
+ [IMX8MM_POWER_VPU_H1] = {
+ .genpd = {
+ .name = "vpu_h1",
+ },
+ .bits = {
+ .pxx = IMX8MM_VPU_H1_SW_Pxx_REQ,
+ .map = IMX8MM_VPU_H1_A53_DOMAIN,
+ },
+ .pgc = IMX8M_PGC_PCIE2,
+ },
+};
+
+static const struct regmap_range imx8mm_yes_ranges[] = {
+ regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+ GPC_PU_PWRHSK),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
+ GPC_PGC_SR(IMX8MM_PGC_MIPI)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
+ GPC_PGC_SR(IMX8MM_PGC_PCIE)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
+ GPC_PGC_SR(IMX8MM_PGC_OTG1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
+ GPC_PGC_SR(IMX8MM_PGC_OTG2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
+ GPC_PGC_SR(IMX8MM_PGC_DDR1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
+ GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU),
+ GPC_PGC_SR(IMX8MM_PGC_GPU)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU),
+ GPC_PGC_SR(IMX8MM_PGC_VPU)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISP),
+ GPC_PGC_SR(IMX8MM_PGC_DISP)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G1),
+ GPC_PGC_SR(IMX8MM_PGC_VPU_G1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G2),
+ GPC_PGC_SR(IMX8MM_PGC_VPU_G2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_H1),
+ GPC_PGC_SR(IMX8MM_PGC_VPU_H1)),
+};
+
+static const struct regmap_access_table imx8mm_access_table = {
+ .yes_ranges = imx8mm_yes_ranges,
+ .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
+ .domains = imx8mm_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
+ .reg_access_table = &imx8mm_access_table,
+};
+
static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
{
int i, ret;
@@ -641,6 +884,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
+ { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ }
};

--
2.20.1

2019-12-05 02:20:44

by Adam Ford

[permalink] [raw]

Subject: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains

There is a power domain controller on the i.XM8M Mini used for
handling interrupts and controlling certain peripherals like
USB OTG and PCIe, which are currently unavailable.

This patch enables support the controller itself to the help
facilitate enabling additional peripherals.

Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 82 ++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 23c8fad7932b..d05c5b617a4d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -4,6 +4,7 @@
*/

#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/power/imx8m-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -13,7 +14,7 @@

/ {
compatible = "fsl,imx8mm";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&gpc>;
#address-cells = <2>;
#size-cells = <2>;

@@ -495,6 +496,85 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_mipi: power-domain@0 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_MIPI>;
+ };
+
+ pgc_pcie: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_PCIE>;
+ };
+
+ pgc_otg1: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG1>;
+ };
+
+ pgc_otg2: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG2>;
+ };
+
+ pgc_ddr1: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_DDR1>;
+ };
+
+ pgc_gpu2d: power-domain@5 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_GPU2D>;
+ };
+
+ pgc_gpu: power-domain@6 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_GPU>;
+ };
+
+ pgc_vpu: power-domain@7 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_VPU>;
+ };
+
+ pgc_gpu3d: power-domain@8 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_GPU3D>;
+ };
+
+ pgc_disp: power-domain@9 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_DISP>;
+ };
+
+ pgc_vpu_g1: power-domain@a {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_VPU_G1>;
+ };
+
+ pgc_vpu_g2: power-domain@b {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_VPU_G2>;
+ };
+
+ pgc_vpu_h1: power-domain@c {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_VPU_H1>;
+ };
+ };
+ };
};

aips2: bus@30400000 {
--
2.20.1

2019-12-05 02:20:51

by Adam Ford

[permalink] [raw]

Subject: [PATCH 7/7] arm64: dts: imx8mm: Add PCIe support

The PCIE controller on the i.MX8M Mini appears to be the same
as the i.MX8MQ but it is absent.

This patch uses the bindings from the i.MX8MQ and the clock
information from the NXP Linux release and marks it as disabled
so it can be configured and enabled on boards where needed.

Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 +++++++++++++++++++++++
1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 5036d713558f..f384934ddbb4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -5,6 +5,7 @@

#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/power/imx8m-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -936,6 +937,40 @@
status = "disabled";
};

+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33800000 0x400000>,
+ <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ status = "disabled";
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
--
2.20.1

2019-12-05 02:21:02

by Adam Ford

[permalink] [raw]

Subject: [PATCH 6/7] ARM64: dts: imx8mm: Fix clocks and power domain for USB OTG

There are two USB OTG controllers on the i.MX8M Mini, but currently
neither are functional.

According to the device tree entries published on the NXP kernel
for the imx8m mini, these both need to be assigned to the proper
clocks and power domain in order to function.

This patch configures both USB OTG controllers to enable a missing
clock and define the power domain so boards wishing to enable
the USB OTG can do so.

Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index d05c5b617a4d..5036d713558f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -14,7 +14,7 @@

/ {
compatible = "fsl,imx8mm";
- interrupt-parent = <&gpc>;
+ interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;

@@ -867,8 +867,11 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
- assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+ <&clk IMX8MM_CLK_USB_CORE_REF>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+ <&clk IMX8MM_SYS_PLL1_100M>;
+ power-domains = <&pgc_otg1>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
@@ -886,8 +889,11 @@
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
- assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+ assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+ <&clk IMX8MM_CLK_USB_CORE_REF>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+ <&clk IMX8MM_SYS_PLL1_100M>;
+ power-domains = <&pgc_otg2>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
--
2.20.1

2019-12-05 02:21:38

by Adam Ford

[permalink] [raw]

Subject: [PATCH 1/7] soc: imx: gpcv2: Rename imx8mq-power.h to imx8m-power.h

In preparation to add support for i.MX8M Mini, this renames
the existing file to be more generic, so it doesn't become
necessary to include multiple files to accomplish the same
task in the future.

Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
drivers/soc/imx/gpcv2.c | 2 +-
include/dt-bindings/power/{imx8mq-power.h => imx8m-power.h} | 0
3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 55a3d1c4bdf0..f73045539fb1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -5,7 +5,7 @@
*/

#include <dt-bindings/clock/imx8mq-clock.h>
-#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/power/imx8m-power.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include "dt-bindings/input/input.h"
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index b0dffb06c05d..250f740d2314 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -15,7 +15,7 @@
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <dt-bindings/power/imx7-power.h>
-#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/power/imx8m-power.h>

#define GPC_LPCR_A_CORE_BSC 0x000

diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8m-power.h
similarity index 100%
rename from include/dt-bindings/power/imx8mq-power.h
rename to include/dt-bindings/power/imx8m-power.h
--
2.20.1

2019-12-05 02:21:49

by Adam Ford

[permalink] [raw]

Subject: [PATCH 4/7] dt-bindings: imx-gpcv2: Update bindings to support i.MX8M Mini

The with the recent additions to the driver, the GPCv2 driver can
support the i.MX8M Mini, but it needs updated 'compatible' entry
to use the proper table.

This patch adds the i.MX8MM to the compatible list of devices.

Signed-off-by: Adam Ford <[email protected]>
---
Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt
index 7c7e972aaa42..576a79097a4c 100644
--- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt
@@ -9,6 +9,7 @@ Required properties:
- compatible: Should be one of:
- "fsl,imx7d-gpc"
- "fsl,imx8mq-gpc"
+ - "fsl,imx8mm-gpc"

- reg: should be register base and length as documented in the
datasheet
@@ -24,8 +25,9 @@ which, in turn, is expected to contain the following:
Required properties:

- reg: Power domain index. Valid values are defined in
- include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
- include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
+ include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc,
+ include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc, and
+ include/dt-bindings/power/imx8m-power.h for fsl,imx8mm-gpc

- #power-domain-cells: Should be 0

--
2.20.1

2019-12-05 02:34:36

by Jacky Bai

[permalink] [raw]

Subject: RE: [PATCH 3/7] soc: imx: gpcv2: add support for i.MX8M Mini SoC

> -----Original Message-----
> From: Adam Ford <[email protected]>
> Sent: Thursday, December 5, 2019 10:19 AM
> To: [email protected]
> Cc: Adam Ford <[email protected]>; Rob Herring <[email protected]>;
> Mark Rutland <[email protected]>; Shawn Guo
> <[email protected]>; Sascha Hauer <[email protected]>;
> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> <[email protected]>; dl-linux-imx <[email protected]>;
> [email protected]; [email protected]
> Subject: [PATCH 3/7] soc: imx: gpcv2: add support for i.MX8M Mini SoC
>
> The GPCv2 on the Freescale i.MX8M Mini SoC works in the same way as the
> GPCv2 on the i.MX8MQ, but with slightly different power domains and
> mapping.
>

Have you tested all the power domain? Some power domains have to do special power up sequence. I am sure
below change can NOT work for GPU & VPU power domain. Adding code in the GPCv2 driver will make this driver
hard to maintain over time. i.MX8MM, i.MX8MN, and in the future, we have other new SOC, different SOC has
different power domain design & on/off sequence. Finally, it will make the GPCv2 very ugly.

> This patch adds the necessary tables so the GPC can operate on the i.MX8M
> Mini.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> drivers/soc/imx/gpcv2.c | 244
> ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 244 insertions(+)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> 250f740d2314..52668e985e8e 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -41,6 +41,20 @@
> #define IMX8M_PCIE1_A53_DOMAIN BIT(3)
> #define IMX8M_MIPI_A53_DOMAIN BIT(2)
>
> +#define IMX8MM_VPU_H1_A53_DOMAIN BIT(15)
> +#define IMX8MM_VPU_G2_A53_DOMAIN BIT(14)
> +#define IMX8MM_VPU_G1_A53_DOMAIN BIT(13)
> +#define IMX8MM_DISP_MIX_A53_DOMAIN BIT(12)
> +#define IMX8MM_GPU_3D_A53_DOMAIN BIT(11)
> +#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
> +#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
> +#define IMX8MM_GPU_2D_A53_DOMAIN BIT(8)
> +#define IMX8MM_DDR1_A53_DOMAIN BIT(7)
> +#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
> +#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
> +#define IMX8MM_PCIE_A53_DOMAIN BIT(3)
> +#define IMX8MM_MIPI_A53_DOMAIN BIT(2)
> +
> #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
> #define GPC_PU_PGC_SW_PDN_REQ 0x104
>
> @@ -64,6 +78,20 @@
> #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
> #define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
>
> +#define IMX8MM_VPU_H1_SW_Pxx_REQ BIT(13)
> +#define IMX8MM_VPU_G2_SW_Pxx_REQ BIT(12)
> +#define IMX8MM_VPU_G1_SW_Pxx_REQ BIT(11)
> +#define IMX8MM_DISP_SW_Pxx_REQ BIT(10)
> +#define IMX8MM_GPU_3D_SW_Pxx_REQ BIT(9)
> +#define IMX8MM_VPU_SW_Pxx_REQ BIT(8)
> +#define IMX8MM_GPU_SW_Pxx_REQ BIT(7)
> +#define IMX8MM_GPU_2D_SW_PXX_REQ BIT(6)
> +#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
> +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
> +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
> +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
> +#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
> +
> #define GPC_M4_PU_PDN_FLG 0x1bc
>
> #define GPC_PU_PWRHSK 0x1fc
> @@ -72,6 +100,10 @@
> #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
> #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
>
> +#define IMX8MM_GPU_HSK_PWRDNREQN BIT(9)
> +#define IMX8MM_VPU_HSK_PWRDNREQN BIT(8)
> +#define IMX8MM_DISP_HSK_PWRDNREQN BIT(7)
> +
> /*
> * The PGC offset values in Reference Manual
> * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -94,6 +126,24
> @@
> #define IMX8M_PGC_MIPI_CSI2 28
> #define IMX8M_PGC_PCIE2 29
>
> +/*
> + * Taken from i.MX8M Mini values from Reference
> + * Manual, Rev. 2, 08/2019
> + */
> +#define IMX8MM_PGC_MIPI 16
> +#define IMX8MM_PGC_PCIE 17
> +#define IMX8MM_PGC_OTG1 18
> +#define IMX8MM_PGC_OTG2 19
> +#define IMX8MM_PGC_DDR1 21
> +#define IMX8MM_PGC_GPU2D 22
> +#define IMX8MM_PGC_GPU 23
> +#define IMX8MM_PGC_VPU 24
> +#define IMX8MM_PGC_GPU3D 25
> +#define IMX8MM_PGC_DISP 26
> +#define IMX8MM_PGC_VPU_G1 27
> +#define IMX8MM_PGC_VPU_G2 28
> +#define IMX8MM_PGC_VPU_H1 29
> +
> #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
> #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
>
> @@ -278,6 +328,7 @@ static const struct imx_pgc_domain_data
> imx7_pgc_domain_data = {
> .reg_access_table = &imx7_access_table, };
>
> +/* i.MX8M dual/QuadLite/Quad */
> static const struct imx_pgc_domain imx8m_pgc_domains[] = {
> [IMX8M_POWER_DOMAIN_MIPI] = {
> .genpd = {
> @@ -442,6 +493,198 @@ static const struct imx_pgc_domain_data
> imx8m_pgc_domain_data = {
> .reg_access_table = &imx8m_access_table, };
>
> +/* i.MX8M Mini */
> +static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
> + [IMX8MM_POWER_DOMAIN_MIPI] = {
> + .genpd = {
> + .name = "mipi",
> + },
> + .bits = {
> + .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
> + .map = IMX8MM_MIPI_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_MIPI,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_PCIE] = {
> + .genpd = {
> + .name = "pcie1",
> + },
> + .bits = {
> + .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
> + .map = IMX8MM_PCIE_A53_DOMAIN,
> + },
> + .pgc = IMX8MM_PGC_PCIE,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_USB_OTG1] = {
> + .genpd = {
> + .name = "usb-otg1",
> + },
> + .bits = {
> + .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
> + .map = IMX8MM_OTG1_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_OTG1,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_USB_OTG2] = {
> + .genpd = {
> + .name = "usb-otg2",
> + },
> + .bits = {
> + .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
> + .map = IMX8MM_OTG2_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_OTG2,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_DDR1] = {
> + .genpd = {
> + .name = "ddr1",
> + },
> + .bits = {
> + .pxx = IMX8MM_DDR1_SW_Pxx_REQ,
> + .map = IMX8MM_DDR1_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_DDR1,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_GPU2D] = {
> + .genpd = {
> + .name = "gpu2d",
> + },
> + .bits = {
> + .pxx = IMX8MM_GPU_2D_SW_PXX_REQ,
> + .map = IMX8MM_GPU_2D_A53_DOMAIN,
> + .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
> + },
> + .pgc = IMX8MM_PGC_GPU2D,
> + },
> +
> +
> + [IMX8MM_POWER_DOMAIN_GPU] = {
> + .genpd = {
> + .name = "gpu",
> + },
> + .bits = {
> + .pxx = IMX8MM_GPU_SW_Pxx_REQ,
> + .map = IMX8MM_GPUMIX_A53_DOMAIN,
> + .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
> + },
> + .pgc = IMX8M_PGC_GPU,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_VPU] = {
> + .genpd = {
> + .name = "vpu",
> + },
> + .bits = {
> + .pxx = IMX8MM_VPU_SW_Pxx_REQ,
> + .map = IMX8MM_VPUMIX_A53_DOMAIN,
> + .hsk = IMX8MM_VPU_HSK_PWRDNREQN,
> + },
> + .pgc = IMX8M_PGC_VPU,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_GPU3D] = {
> + .genpd = {
> + .name = "gpu3d",
> + },
> + .bits = {
> + .pxx = IMX8MM_GPU_3D_SW_Pxx_REQ,
> + .map = IMX8MM_GPU_3D_A53_DOMAIN,
> + .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
> + },
> + .pgc = IMX8MM_PGC_GPU2D,
> + },
> +
> + [IMX8MM_POWER_DOMAIN_DISP] = {
> + .genpd = {
> + .name = "disp",
> + },
> + .bits = {
> + .pxx = IMX8MM_DISP_SW_Pxx_REQ,
> + .map = IMX8MM_DISP_MIX_A53_DOMAIN,
> + .hsk = IMX8MM_DISP_HSK_PWRDNREQN,
> + },
> + .pgc = IMX8M_PGC_DISP,
> + },
> +
> + [IMX8MM_POWER_VPU_G1] = {
> + .genpd = {
> + .name = "vpu_g1",
> + },
> + .bits = {
> + .pxx = IMX8MM_VPU_G1_SW_Pxx_REQ,
> + .map = IMX8MM_VPU_G1_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_MIPI_CSI1,
> + },
> +
> + [IMX8MM_POWER_VPU_G2] = {
> + .genpd = {
> + .name = "vpu_g2",
> + },
> + .bits = {
> + .pxx = IMX8MM_VPU_G2_SW_Pxx_REQ,
> + .map = IMX8MM_VPU_G2_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_MIPI_CSI2,
> + },
> +
> + [IMX8MM_POWER_VPU_H1] = {
> + .genpd = {
> + .name = "vpu_h1",
> + },
> + .bits = {
> + .pxx = IMX8MM_VPU_H1_SW_Pxx_REQ,
> + .map = IMX8MM_VPU_H1_A53_DOMAIN,
> + },
> + .pgc = IMX8M_PGC_PCIE2,
> + },
> +};
> +
> +static const struct regmap_range imx8mm_yes_ranges[] = {
> + regmap_reg_range(GPC_LPCR_A_CORE_BSC,
> + GPC_PU_PWRHSK),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
> + GPC_PGC_SR(IMX8MM_PGC_MIPI)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
> + GPC_PGC_SR(IMX8MM_PGC_PCIE)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
> + GPC_PGC_SR(IMX8MM_PGC_OTG1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
> + GPC_PGC_SR(IMX8MM_PGC_OTG2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
> + GPC_PGC_SR(IMX8MM_PGC_DDR1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
> + GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU),
> + GPC_PGC_SR(IMX8MM_PGC_GPU)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU),
> + GPC_PGC_SR(IMX8MM_PGC_VPU)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISP),
> + GPC_PGC_SR(IMX8MM_PGC_DISP)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G1),
> + GPC_PGC_SR(IMX8MM_PGC_VPU_G1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G2),
> + GPC_PGC_SR(IMX8MM_PGC_VPU_G2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_H1),
> + GPC_PGC_SR(IMX8MM_PGC_VPU_H1)),
> +};
> +
> +static const struct regmap_access_table imx8mm_access_table = {
> + .yes_ranges = imx8mm_yes_ranges,
> + .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
> +};
> +
> +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
> + .domains = imx8mm_pgc_domains,
> + .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
> + .reg_access_table = &imx8mm_access_table, };
> +
> static int imx_pgc_get_clocks(struct imx_pgc_domain *domain) {
> int i, ret;
> @@ -641,6 +884,7 @@ static int imx_gpcv2_probe(struct platform_device
> *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = {
> { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
> { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> + { .compatible = "fsl,imx8mm-gpc", .data =
> &imx8mm_pgc_domain_data, },
> { }
> };
>
> --
> 2.20.1

2019-12-05 02:38:17

by Jacky Bai

[permalink] [raw]

Subject: RE: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains

2019-12-05 03:15:06

by Adam Ford

[permalink] [raw]

Subject: Re: [PATCH 3/7] soc: imx: gpcv2: add support for i.MX8M Mini SoC

On Wed, Dec 4, 2019 at 8:33 PM Jacky Bai <[email protected]> wrote:
>
> > -----Original Message-----
> > From: Adam Ford <[email protected]>
> > Sent: Thursday, December 5, 2019 10:19 AM
> > To: [email protected]
> > Cc: Adam Ford <[email protected]>; Rob Herring <[email protected]>;
> > Mark Rutland <[email protected]>; Shawn Guo
> > <[email protected]>; Sascha Hauer <[email protected]>;
> > Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> > <[email protected]>; dl-linux-imx <[email protected]>;
> > [email protected]; [email protected]
> > Subject: [PATCH 3/7] soc: imx: gpcv2: add support for i.MX8M Mini SoC
> >
> > The GPCv2 on the Freescale i.MX8M Mini SoC works in the same way as the
> > GPCv2 on the i.MX8MQ, but with slightly different power domains and
> > mapping.
> >
>
> Have you tested all the power domain? Some power domains have to do special power up sequence. I am sure

I haven't because NXP hasn't pushed drivers to support items like the
DSI or the VPU, so trying some of those power domains won't really do
anyone any good, but I have tested USB OTG and some limited testing on
PCIe.

> below change can NOT work for GPU & VPU power domain. Adding code in the GPCv2 driver will make this driver
> hard to maintain over time. i.MX8MM, i.MX8MN, and in the future, we have other new SOC, different SOC has
> different power domain design & on/off sequence. Finally, it will make the GPCv2 very ugly.

I based it off the i.MX8MQ which uses this driver and most of the
registers appear to be the same or similar with some small variation.
Without this driver, features like USB, PCIe and others are
non-functional, so until NXP updates the drivers, it seems like this
is the best of what was available.

What makes the i.MX8M so much different than the i.MX8MQ? The layout
of the registers is the same, the naming convention is the same, and
for the registers listed, the only apparent difference is the bit
order and possible naming convention.

adam
>
> > This patch adds the necessary tables so the GPC can operate on the i.MX8M
> > Mini.
> >
> > Signed-off-by: Adam Ford <[email protected]>
> > ---
> > drivers/soc/imx/gpcv2.c | 244
> > ++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 244 insertions(+)
> >
> > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index
> > 250f740d2314..52668e985e8e 100644
> > --- a/drivers/soc/imx/gpcv2.c
> > +++ b/drivers/soc/imx/gpcv2.c
> > @@ -41,6 +41,20 @@
> > #define IMX8M_PCIE1_A53_DOMAIN BIT(3)
> > #define IMX8M_MIPI_A53_DOMAIN BIT(2)
> >
> > +#define IMX8MM_VPU_H1_A53_DOMAIN BIT(15)
> > +#define IMX8MM_VPU_G2_A53_DOMAIN BIT(14)
> > +#define IMX8MM_VPU_G1_A53_DOMAIN BIT(13)
> > +#define IMX8MM_DISP_MIX_A53_DOMAIN BIT(12)
> > +#define IMX8MM_GPU_3D_A53_DOMAIN BIT(11)
> > +#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
> > +#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
> > +#define IMX8MM_GPU_2D_A53_DOMAIN BIT(8)
> > +#define IMX8MM_DDR1_A53_DOMAIN BIT(7)
> > +#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
> > +#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
> > +#define IMX8MM_PCIE_A53_DOMAIN BIT(3)
> > +#define IMX8MM_MIPI_A53_DOMAIN BIT(2)
> > +
> > #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
> > #define GPC_PU_PGC_SW_PDN_REQ 0x104
> >
> > @@ -64,6 +78,20 @@
> > #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
> > #define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
> >
> > +#define IMX8MM_VPU_H1_SW_Pxx_REQ BIT(13)
> > +#define IMX8MM_VPU_G2_SW_Pxx_REQ BIT(12)
> > +#define IMX8MM_VPU_G1_SW_Pxx_REQ BIT(11)
> > +#define IMX8MM_DISP_SW_Pxx_REQ BIT(10)
> > +#define IMX8MM_GPU_3D_SW_Pxx_REQ BIT(9)
> > +#define IMX8MM_VPU_SW_Pxx_REQ BIT(8)
> > +#define IMX8MM_GPU_SW_Pxx_REQ BIT(7)
> > +#define IMX8MM_GPU_2D_SW_PXX_REQ BIT(6)
> > +#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
> > +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
> > +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
> > +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
> > +#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
> > +
> > #define GPC_M4_PU_PDN_FLG 0x1bc
> >
> > #define GPC_PU_PWRHSK 0x1fc
> > @@ -72,6 +100,10 @@
> > #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
> > #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
> >
> > +#define IMX8MM_GPU_HSK_PWRDNREQN BIT(9)
> > +#define IMX8MM_VPU_HSK_PWRDNREQN BIT(8)
> > +#define IMX8MM_DISP_HSK_PWRDNREQN BIT(7)
> > +
> > /*
> > * The PGC offset values in Reference Manual
> > * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -94,6 +126,24
> > @@
> > #define IMX8M_PGC_MIPI_CSI2 28
> > #define IMX8M_PGC_PCIE2 29
> >
> > +/*
> > + * Taken from i.MX8M Mini values from Reference
> > + * Manual, Rev. 2, 08/2019
> > + */
> > +#define IMX8MM_PGC_MIPI 16
> > +#define IMX8MM_PGC_PCIE 17
> > +#define IMX8MM_PGC_OTG1 18
> > +#define IMX8MM_PGC_OTG2 19
> > +#define IMX8MM_PGC_DDR1 21
> > +#define IMX8MM_PGC_GPU2D 22
> > +#define IMX8MM_PGC_GPU 23
> > +#define IMX8MM_PGC_VPU 24
> > +#define IMX8MM_PGC_GPU3D 25
> > +#define IMX8MM_PGC_DISP 26
> > +#define IMX8MM_PGC_VPU_G1 27
> > +#define IMX8MM_PGC_VPU_G2 28
> > +#define IMX8MM_PGC_VPU_H1 29
> > +
> > #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
> > #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
> >
> > @@ -278,6 +328,7 @@ static const struct imx_pgc_domain_data
> > imx7_pgc_domain_data = {
> > .reg_access_table = &imx7_access_table, };
> >
> > +/* i.MX8M dual/QuadLite/Quad */
> > static const struct imx_pgc_domain imx8m_pgc_domains[] = {
> > [IMX8M_POWER_DOMAIN_MIPI] = {
> > .genpd = {
> > @@ -442,6 +493,198 @@ static const struct imx_pgc_domain_data
> > imx8m_pgc_domain_data = {
> > .reg_access_table = &imx8m_access_table, };
> >
> > +/* i.MX8M Mini */
> > +static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
> > + [IMX8MM_POWER_DOMAIN_MIPI] = {
> > + .genpd = {
> > + .name = "mipi",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
> > + .map = IMX8MM_MIPI_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_MIPI,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_PCIE] = {
> > + .genpd = {
> > + .name = "pcie1",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
> > + .map = IMX8MM_PCIE_A53_DOMAIN,
> > + },
> > + .pgc = IMX8MM_PGC_PCIE,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_USB_OTG1] = {
> > + .genpd = {
> > + .name = "usb-otg1",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
> > + .map = IMX8MM_OTG1_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_OTG1,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_USB_OTG2] = {
> > + .genpd = {
> > + .name = "usb-otg2",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
> > + .map = IMX8MM_OTG2_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_OTG2,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_DDR1] = {
> > + .genpd = {
> > + .name = "ddr1",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_DDR1_SW_Pxx_REQ,
> > + .map = IMX8MM_DDR1_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_DDR1,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_GPU2D] = {
> > + .genpd = {
> > + .name = "gpu2d",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_GPU_2D_SW_PXX_REQ,
> > + .map = IMX8MM_GPU_2D_A53_DOMAIN,
> > + .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
> > + },
> > + .pgc = IMX8MM_PGC_GPU2D,
> > + },
> > +
> > +
> > + [IMX8MM_POWER_DOMAIN_GPU] = {
> > + .genpd = {
> > + .name = "gpu",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_GPU_SW_Pxx_REQ,
> > + .map = IMX8MM_GPUMIX_A53_DOMAIN,
> > + .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
> > + },
> > + .pgc = IMX8M_PGC_GPU,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_VPU] = {
> > + .genpd = {
> > + .name = "vpu",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_VPU_SW_Pxx_REQ,
> > + .map = IMX8MM_VPUMIX_A53_DOMAIN,
> > + .hsk = IMX8MM_VPU_HSK_PWRDNREQN,
> > + },
> > + .pgc = IMX8M_PGC_VPU,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_GPU3D] = {
> > + .genpd = {
> > + .name = "gpu3d",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_GPU_3D_SW_Pxx_REQ,
> > + .map = IMX8MM_GPU_3D_A53_DOMAIN,
> > + .hsk = IMX8MM_GPU_HSK_PWRDNREQN,
> > + },
> > + .pgc = IMX8MM_PGC_GPU2D,
> > + },
> > +
> > + [IMX8MM_POWER_DOMAIN_DISP] = {
> > + .genpd = {
> > + .name = "disp",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_DISP_SW_Pxx_REQ,
> > + .map = IMX8MM_DISP_MIX_A53_DOMAIN,
> > + .hsk = IMX8MM_DISP_HSK_PWRDNREQN,
> > + },
> > + .pgc = IMX8M_PGC_DISP,
> > + },
> > +
> > + [IMX8MM_POWER_VPU_G1] = {
> > + .genpd = {
> > + .name = "vpu_g1",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_VPU_G1_SW_Pxx_REQ,
> > + .map = IMX8MM_VPU_G1_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_MIPI_CSI1,
> > + },
> > +
> > + [IMX8MM_POWER_VPU_G2] = {
> > + .genpd = {
> > + .name = "vpu_g2",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_VPU_G2_SW_Pxx_REQ,
> > + .map = IMX8MM_VPU_G2_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_MIPI_CSI2,
> > + },
> > +
> > + [IMX8MM_POWER_VPU_H1] = {
> > + .genpd = {
> > + .name = "vpu_h1",
> > + },
> > + .bits = {
> > + .pxx = IMX8MM_VPU_H1_SW_Pxx_REQ,
> > + .map = IMX8MM_VPU_H1_A53_DOMAIN,
> > + },
> > + .pgc = IMX8M_PGC_PCIE2,
> > + },
> > +};
> > +
> > +static const struct regmap_range imx8mm_yes_ranges[] = {
> > + regmap_reg_range(GPC_LPCR_A_CORE_BSC,
> > + GPC_PU_PWRHSK),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
> > + GPC_PGC_SR(IMX8MM_PGC_MIPI)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
> > + GPC_PGC_SR(IMX8MM_PGC_PCIE)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
> > + GPC_PGC_SR(IMX8MM_PGC_OTG1)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
> > + GPC_PGC_SR(IMX8MM_PGC_OTG2)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
> > + GPC_PGC_SR(IMX8MM_PGC_DDR1)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
> > + GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU),
> > + GPC_PGC_SR(IMX8MM_PGC_GPU)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU),
> > + GPC_PGC_SR(IMX8MM_PGC_VPU)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISP),
> > + GPC_PGC_SR(IMX8MM_PGC_DISP)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G1),
> > + GPC_PGC_SR(IMX8MM_PGC_VPU_G1)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G2),
> > + GPC_PGC_SR(IMX8MM_PGC_VPU_G2)),
> > + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_H1),
> > + GPC_PGC_SR(IMX8MM_PGC_VPU_H1)),
> > +};
> > +
> > +static const struct regmap_access_table imx8mm_access_table = {
> > + .yes_ranges = imx8mm_yes_ranges,
> > + .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
> > +};
> > +
> > +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
> > + .domains = imx8mm_pgc_domains,
> > + .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
> > + .reg_access_table = &imx8mm_access_table, };
> > +
> > static int imx_pgc_get_clocks(struct imx_pgc_domain *domain) {
> > int i, ret;
> > @@ -641,6 +884,7 @@ static int imx_gpcv2_probe(struct platform_device
> > *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = {
> > { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
> > { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> > + { .compatible = "fsl,imx8mm-gpc", .data =
> > &imx8mm_pgc_domain_data, },
> > { }
> > };
> >
> > --
> > 2.20.1
>

2019-12-05 03:16:31

by Adam Ford

[permalink] [raw]

Subject: Re: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains

On Wed, Dec 4, 2019 at 8:37 PM Jacky Bai <[email protected]> wrote:
>
> > -----Original Message-----
> > From: Adam Ford <[email protected]>
> > Sent: Thursday, December 5, 2019 10:19 AM
> > To: [email protected]
> > Cc: Adam Ford <[email protected]>; Rob Herring <[email protected]>;
> > Mark Rutland <[email protected]>; Shawn Guo
> > <[email protected]>; Sascha Hauer <[email protected]>;
> > Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> > <[email protected]>; dl-linux-imx <[email protected]>;
> > [email protected]; [email protected]
> > Subject: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains
> >
> > There is a power domain controller on the i.XM8M Mini used for handling
> > interrupts and controlling certain peripherals like USB OTG and PCIe, which
> > are currently unavailable.
> >
> > This patch enables support the controller itself to the help facilitate enabling
> > additional peripherals.
> >
> > Signed-off-by: Adam Ford <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 82
> > ++++++++++++++++++++++-
> > 1 file changed, 81 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 23c8fad7932b..d05c5b617a4d 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include <dt-bindings/clock/imx8mm-clock.h>
> > +#include <dt-bindings/power/imx8m-power.h>
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/input/input.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -13,7 +14,7 @@
> >
> > / {
> > compatible = "fsl,imx8mm";
> > - interrupt-parent = <&gic>;
> > + interrupt-parent = <&gpc>;
>
> NACK, for imx8mm, imx8mn & future i.MX8M SOC, we don't treat GPC as interrupt controller in linux anymore.
> Above change will break the low power mode support(suspend/resume)

What makes it different than the i.MX8MQ? The I basically copied this
from the i.MX8MQ and updated the bit locations and tried to leave
everything else the same.

I'm OK with removing the interrupt controller stuff, but if that's
required, I'd like to understand why it's still in the i.MX8Q.

adam
>
> BR
> Jacky Bai
>
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > @@ -495,6 +496,85 @@
> > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > #reset-cells = <1>;
> > };
> > +
> > + gpc: gpc@303a0000 {
> > + compatible = "fsl,imx8mm-gpc";
> > + reg = <0x303a0000 0x10000>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > +
> > + pgc {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + pgc_mipi: power-domain@0 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_MIPI>;
> > + };
> > +
> > + pgc_pcie: power-domain@1 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> > + };
> > +
> > + pgc_otg1: power-domain@2 {
> > + #power-domain-cells = <0>;
> > + reg =
> > <IMX8MM_POWER_DOMAIN_USB_OTG1>;
> > + };
> > +
> > + pgc_otg2: power-domain@3 {
> > + #power-domain-cells = <0>;
> > + reg =
> > <IMX8MM_POWER_DOMAIN_USB_OTG2>;
> > + };
> > +
> > + pgc_ddr1: power-domain@4 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_DDR1>;
> > + };
> > +
> > + pgc_gpu2d: power-domain@5 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_GPU2D>;
> > + };
> > +
> > + pgc_gpu: power-domain@6 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_GPU>;
> > + };
> > +
> > + pgc_vpu: power-domain@7 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_VPU>;
> > + };
> > +
> > + pgc_gpu3d: power-domain@8 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_GPU3D>;
> > + };
> > +
> > + pgc_disp: power-domain@9 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + pgc_vpu_g1: power-domain@a {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_VPU_G1>;
> > + };
> > +
> > + pgc_vpu_g2: power-domain@b {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_VPU_G2>;
> > + };
> > +
> > + pgc_vpu_h1: power-domain@c {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MM_POWER_VPU_H1>;
> > + };
> > + };
> > + };
> > };
> >
> > aips2: bus@30400000 {
> > --
> > 2.20.1
>

2020-02-05 15:43:00

by Frieder Schrempf

[permalink] [raw]

Subject: Re: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains

Hi,

On 05.12.19 04:15, Adam Ford wrote:
> On Wed, Dec 4, 2019 at 8:37 PM Jacky Bai <[email protected]> wrote:
>>
>>> -----Original Message-----
>>> From: Adam Ford <[email protected]>
>>> Sent: Thursday, December 5, 2019 10:19 AM
>>> To: [email protected]
>>> Cc: Adam Ford <[email protected]>; Rob Herring <[email protected]>;
>>> Mark Rutland <[email protected]>; Shawn Guo
>>> <[email protected]>; Sascha Hauer <[email protected]>;
>>> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
>>> <[email protected]>; dl-linux-imx <[email protected]>;
>>> [email protected]; [email protected]
>>> Subject: [PATCH 5/7] arm64: dts: imx8mm: add GPC power domains
>>>
>>> There is a power domain controller on the i.XM8M Mini used for handling
>>> interrupts and controlling certain peripherals like USB OTG and PCIe, which
>>> are currently unavailable.
>>>
>>> This patch enables support the controller itself to the help facilitate enabling
>>> additional peripherals.
>>>
>>> Signed-off-by: Adam Ford <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 82
>>> ++++++++++++++++++++++-
>>> 1 file changed, 81 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
>>> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
>>> index 23c8fad7932b..d05c5b617a4d 100644
>>> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
>>> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
>>> @@ -4,6 +4,7 @@
>>> */
>>>
>>> #include <dt-bindings/clock/imx8mm-clock.h>
>>> +#include <dt-bindings/power/imx8m-power.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>> #include <dt-bindings/input/input.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> @@ -13,7 +14,7 @@
>>>
>>> / {
>>> compatible = "fsl,imx8mm";
>>> - interrupt-parent = <&gic>;
>>> + interrupt-parent = <&gpc>;
>>
>> NACK, for imx8mm, imx8mn & future i.MX8M SOC, we don't treat GPC as interrupt controller in linux anymore.
>> Above change will break the low power mode support(suspend/resume)
>
> What makes it different than the i.MX8MQ? The I basically copied this
> from the i.MX8MQ and updated the bit locations and tried to leave
> everything else the same.
>
> I'm OK with removing the interrupt controller stuff, but if that's
> required, I'd like to understand why it's still in the i.MX8Q.

I would also like to know how NXP plans to implement things like GPC in
mainline. I currently use a tree [1] that doesn't use any power domain
driver but USB, LCDIF and MIPI-DSI are working fine.
For this I ported some patches from the imx_5.4.0_8dxlphantom_er tree in
the NXP repository [2] and added a few small hacks to enable missing
clocks, etc.

Is there some roadmap for the upstream support of the different drivers
and features of the i.MX8MM?

Thanks,
Frieder

[1] https://git.kontron-electronics.de/linux/linux/commits/v5.4-ktn
[2]
https://source.codeaurora.org/external/imx/linux-imx/log/?h=imx_5.4.0_8dxlphantom_er

>
> adam
>>
>> BR
>> Jacky Bai
>>
>>> #address-cells = <2>;
>>> #size-cells = <2>;
>>>
>>> @@ -495,6 +496,85 @@
>>> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>>> #reset-cells = <1>;
>>> };
>>> +
>>> + gpc: gpc@303a0000 {
>>> + compatible = "fsl,imx8mm-gpc";
>>> + reg = <0x303a0000 0x10000>;
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-controller;
>>> + #interrupt-cells = <3>;
>>> +
>>> + pgc {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + pgc_mipi: power-domain@0 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_MIPI>;
>>> + };
>>> +
>>> + pgc_pcie: power-domain@1 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_PCIE>;
>>> + };
>>> +
>>> + pgc_otg1: power-domain@2 {
>>> + #power-domain-cells = <0>;
>>> + reg =
>>> <IMX8MM_POWER_DOMAIN_USB_OTG1>;
>>> + };
>>> +
>>> + pgc_otg2: power-domain@3 {
>>> + #power-domain-cells = <0>;
>>> + reg =
>>> <IMX8MM_POWER_DOMAIN_USB_OTG2>;
>>> + };
>>> +
>>> + pgc_ddr1: power-domain@4 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_DDR1>;
>>> + };
>>> +
>>> + pgc_gpu2d: power-domain@5 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_GPU2D>;
>>> + };
>>> +
>>> + pgc_gpu: power-domain@6 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_GPU>;
>>> + };
>>> +
>>> + pgc_vpu: power-domain@7 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_VPU>;
>>> + };
>>> +
>>> + pgc_gpu3d: power-domain@8 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_GPU3D>;
>>> + };
>>> +
>>> + pgc_disp: power-domain@9 {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_DOMAIN_DISP>;
>>> + };
>>> +
>>> + pgc_vpu_g1: power-domain@a {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_VPU_G1>;
>>> + };
>>> +
>>> + pgc_vpu_g2: power-domain@b {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_VPU_G2>;
>>> + };
>>> +
>>> + pgc_vpu_h1: power-domain@c {
>>> + #power-domain-cells = <0>;
>>> + reg = <IMX8MM_POWER_VPU_H1>;
>>> + };
>>> + };
>>> + };
>>> };
>>>
>>> aips2: bus@30400000 {
>>> --
>>> 2.20.1
>>
>
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