AMD devices with the FCH SATA Controller 0x1022:0x7901 do not need the
default debounce delay of 200 ms.
07:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
So skip it, by mapping it to the board with no debounce delay.
Tested on the MSI MS-7A37/B350M MORTAR (MS-7A37).
To-do: Add test details and results.
Signed-off-by: Paul Menzel <[email protected]>
Cc: Hans de Goede <[email protected]>
Cc: Mario Limonciello <[email protected]>
---
I am travelling so could not test this exact patch just yet, but I ran
something similar for several weeks already. It’d be great, if the
desktop and AMD folks could also give this a try.
drivers/ata/ahci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 0fc09b86a559..44b79fe43d13 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -456,7 +456,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
- { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
+ { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power_no_debounce_delay }, /* AMD Green Sardine */
/* AMD is using RAID class only for ahci controllers */
{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
--
2.30.2
On 2022/03/03 12:04, Paul Menzel wrote:
> AMD devices with the FCH SATA Controller 0x1022:0x7901 do not need the
> default debounce delay of 200 ms.
>
> 07:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
>
> So skip it, by mapping it to the board with no debounce delay.
>
> Tested on the MSI MS-7A37/B350M MORTAR (MS-7A37).
>
> To-do: Add test details and results.
Please squash this patch together with patch 1. Since you are adding a new board
entry definition, it is better to have a user for it in the same patch (this
avoids reverts to leave unused code behind).
>
> Signed-off-by: Paul Menzel <[email protected]>
> Cc: Hans de Goede <[email protected]>
> Cc: Mario Limonciello <[email protected]>
> ---
> I am travelling so could not test this exact patch just yet, but I ran
> something similar for several weeks already. It’d be great, if the
> desktop and AMD folks could also give this a try.
>
> drivers/ata/ahci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index 0fc09b86a559..44b79fe43d13 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -456,7 +456,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
> { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
> { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
> { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
> - { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
> + { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power_no_debounce_delay }, /* AMD Green Sardine */
Really long name, but I cannot think of anything better...
> /* AMD is using RAID class only for ahci controllers */
> { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
> PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
--
Damien Le Moal
Western Digital Research
On 3/3/22 06:23, Damien Le Moal wrote:
> On 2022/03/03 12:04, Paul Menzel wrote:
>> AMD devices with the FCH SATA Controller 0x1022:0x7901 do not need the
>> default debounce delay of 200 ms.
>>
>> 07:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
>>
>> So skip it, by mapping it to the board with no debounce delay.
>>
>> Tested on the MSI MS-7A37/B350M MORTAR (MS-7A37).
>>
>> To-do: Add test details and results.
>
> Please squash this patch together with patch 1. Since you are adding a new board
> entry definition, it is better to have a user for it in the same patch (this
> avoids reverts to leave unused code behind). >
>>
>> Signed-off-by: Paul Menzel <[email protected]>
>> Cc: Hans de Goede <[email protected]>
>> Cc: Mario Limonciello <[email protected]>
>> ---
>> I am travelling so could not test this exact patch just yet, but I ran
>> something similar for several weeks already. It’d be great, if the
>> desktop and AMD folks could also give this a try.
As we are trying to drop the low power definition for 5.18, maybe can
this wait until 5.19 so we can see if that sticks so this doesn't get
caught up in possible reverts?
>>
>> drivers/ata/ahci.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>> index 0fc09b86a559..44b79fe43d13 100644
>> --- a/drivers/ata/ahci.c
>> +++ b/drivers/ata/ahci.c
>> @@ -456,7 +456,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
>> { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
>> { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
>> { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
>> - { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
>> + { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power_no_debounce_delay }, /* AMD Green Sardine */
>
> Really long name, but I cannot think of anything better...
>
>> /* AMD is using RAID class only for ahci controllers */
>> { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
>> PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
>
>
On 2022/03/03 15:19, Mario Limonciello wrote:
> On 3/3/22 06:23, Damien Le Moal wrote:
>> On 2022/03/03 12:04, Paul Menzel wrote:
>>> AMD devices with the FCH SATA Controller 0x1022:0x7901 do not need the
>>> default debounce delay of 200 ms.
>>>
>>> 07:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51)
>>>
>>> So skip it, by mapping it to the board with no debounce delay.
>>>
>>> Tested on the MSI MS-7A37/B350M MORTAR (MS-7A37).
>>>
>>> To-do: Add test details and results.
>>
>> Please squash this patch together with patch 1. Since you are adding a new board
>> entry definition, it is better to have a user for it in the same patch (this
>> avoids reverts to leave unused code behind). >
>>>
>>> Signed-off-by: Paul Menzel <[email protected]>
>>> Cc: Hans de Goede <[email protected]>
>>> Cc: Mario Limonciello <[email protected]>
>>> ---
>>> I am travelling so could not test this exact patch just yet, but I ran
>>> something similar for several weeks already. It’d be great, if the
>>> desktop and AMD folks could also give this a try.
>
> As we are trying to drop the low power definition for 5.18, maybe can
> this wait until 5.19 so we can see if that sticks so this doesn't get
> caught up in possible reverts?
The "no debounce delay" addition is a valid change regardless of the "low_power
is default" change. So I do not think this is an issue. But you will need to
rebase your patch to include this change :)
Going forward, I would also like to have the "no debounce delay" as the default
too, after the low power default change settles and hopefully sticks.
>
>>>
>>> drivers/ata/ahci.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
>>> index 0fc09b86a559..44b79fe43d13 100644
>>> --- a/drivers/ata/ahci.c
>>> +++ b/drivers/ata/ahci.c
>>> @@ -456,7 +456,7 @@ static const struct pci_device_id ahci_pci_tbl[] = {
>>> { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
>>> { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
>>> { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
>>> - { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
>>> + { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power_no_debounce_delay }, /* AMD Green Sardine */
>>
>> Really long name, but I cannot think of anything better...
>>
>>> /* AMD is using RAID class only for ahci controllers */
>>> { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
>>> PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
>>
>>
>
--
Damien Le Moal
Western Digital Research