2007-12-06 12:41:38

by Jesper Nilsson

Subject: [PATCH 00/47] CRIS patches for CRISv32 EtraxFS and ARTPEC-3

Hi,

This patchset contains the differences to add support for the EtraxFS and
ARTPEC-3 CPUs, both of the CRISv32 family. Both chips can now be compiled
with minimal configs.

To compile you'll need the Axis gcc cross port for CRISv32, it is mentioned
in http://marc.info/?l=linux-kernel&m=119337976126184&w=2 how to get this.

Still missing to allow full compile is include/linux/mtd/mtdram.h,
see http://marc.info/?l=linux-kernel&m=119373777301863&w=2

This is step two in syncing the Axis internal changes with mainline Linux,
with the final goal being getting the CRIS port to the same level as
the rest of the kernel.

I've tried to remove as much checkpatch warnings and errors as possible,
but some remain, mostly (I think you'll agree) spurious warnings,
although there's also a bunch of generated files which don't conform,
but I hope to fix this at the source later on.

I realise this is a hefty chunk of code to review, but any suggestions
on improvements are thankfully received.

The changes are also available in the export2 branch at

git://http://www.jni.nu/axis.git

Best regards,

/^JN - Jesper Nilsson
--
Jesper Nilsson -- [email protected]

2007-12-06 12:55:53

by Jesper Nilsson

Subject: [PATCH 42/47] Minor updates to CRISv32 kernel/process.c

- Shorten include paths for machine dependent header files.
- Remove unused extern declaration of etrax_gpio_wake_up_check.
- Register name for first timer is now regi_timer0.

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/arch-v32/kernel/process.c | 16 ++++++----------
1 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c
index b72a155..3933c04 100644
--- a/arch/cris/arch-v32/kernel/process.c
+++ b/arch/cris/arch-v32/kernel/process.c
@@ -12,17 +12,13 @@
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/slab.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/timer_defs.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/timer_defs.h>
+#include <hwregs/intr_vect_defs.h>

extern void stop_watchdog(void);

-#ifdef CONFIG_ETRAX_GPIO
-extern void etrax_gpio_wake_up_check(void); /* Defined in drivers/gpio.c. */
-#endif
-
extern int cris_hlt_counter;

/* We use this if we don't have any better idle routine. */
@@ -82,7 +78,7 @@ hard_reset_now(void)
wd_ctrl.cmd = regk_timer_start;

arch_enable_nmi();
- REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+ REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
}
#endif

@@ -162,7 +158,7 @@ copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
/* Put the switch stack right below the pt_regs. */
swstack = ((struct switch_stack *) childregs) - 1;

- /* Parameter to ret_from_sys_call. 0 is don't restart the syscall. */
+ /* Paramater to ret_from_sys_call. 0 is don't restart the syscall. */
swstack->r9 = 0;

/*
--
1.5.3.6.970.gd25430

2007-12-06 12:56:19

by Jesper Nilsson

Subject: [PATCH 43/47] Update and improve CRISv32 kernel/traps.c

- Remove watchdog handling, handled elsewhere.
- Shorten include paths to machine dependent header files.
- Remove raw_printk hack, we now use oops_in_progress instead.
- Add handling of BUG for exception handlers (break 14).
- Formatting and whitespace changes.

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/arch-v32/kernel/traps.c | 192 ++++++++++++++++++++++---------------
1 files changed, 114 insertions(+), 78 deletions(-)

diff --git a/arch/cris/arch-v32/kernel/traps.c b/arch/cris/arch-v32/kernel/traps.c
index 17fd3db..9003e38 100644
--- a/arch/cris/arch-v32/kernel/traps.c
+++ b/arch/cris/arch-v32/kernel/traps.c
@@ -1,50 +1,45 @@
/*
- * Copyright (C) 2003, Axis Communications AB.
+ * Copyright (C) 2003-2006, Axis Communications AB.
*/

#include <linux/ptrace.h>
+#include <linux/module.h>
#include <asm/uaccess.h>
-
-#include <asm/arch/hwregs/supp_reg.h>
-
-extern void reset_watchdog(void);
-extern void stop_watchdog(void);
-
-extern int raw_printk(const char *fmt, ...);
+#include <hwregs/supp_reg.h>
+#include <hwregs/intr_vect_defs.h>
+#include <asm/irq.h>

void
show_registers(struct pt_regs *regs)
{
/*
* It's possible to use either the USP register or current->thread.usp.
- * USP might not correspond to the current proccess for all cases this
+ * USP might not correspond to the current process for all cases this
* function is called, and current->thread.usp isn't up to date for the
- * current proccess. Experience shows that using USP is the way to go.
+ * current process. Experience shows that using USP is the way to go.
*/
- unsigned long usp;
+ unsigned long usp = rdusp();
unsigned long d_mmu_cause;
unsigned long i_mmu_cause;

- usp = rdusp();
+ printk("CPU: %d\n", smp_processor_id());

- raw_printk("CPU: %d\n", smp_processor_id());
+ printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
+ regs->erp, regs->srp, regs->ccs, usp, regs->mof);

- raw_printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
- regs->erp, regs->srp, regs->ccs, usp, regs->mof);
+ printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
+ regs->r0, regs->r1, regs->r2, regs->r3);

- raw_printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
+ printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
+ regs->r4, regs->r5, regs->r6, regs->r7);

- raw_printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
+ printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
+ regs->r8, regs->r9, regs->r10, regs->r11);

- raw_printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
+ printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
+ regs->r12, regs->r13, regs->orig_r10, regs->acr);

- raw_printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, regs->acr);
-
- raw_printk("sp: %08lx\n", regs);
+ printk(" sp: %08lx\n", (unsigned long)regs);

SUPP_BANK_SEL(BANK_IM);
SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause);
@@ -52,18 +47,20 @@ show_registers(struct pt_regs *regs)
SUPP_BANK_SEL(BANK_DM);
SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause);

- raw_printk(" Data MMU Cause: %08lx\n", d_mmu_cause);
- raw_printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);
+ printk(" Data MMU Cause: %08lx\n", d_mmu_cause);
+ printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);

- raw_printk("Process %s (pid: %d, stackpage: %08lx)\n",
- current->comm, current->pid, (unsigned long) current);
+ printk("Process %s (pid: %d, stackpage=%08lx)\n",
+ current->comm, current->pid, (unsigned long)current);

- /* Show additional info if in kernel-mode. */
+ /*
+ * When in-kernel, we also print out the stack and code at the
+ * time of the fault..
+ */
if (!user_mode(regs)) {
int i;
- unsigned char c;

- show_stack(NULL, (unsigned long *) usp);
+ show_stack(NULL, (unsigned long *)usp);

/*
* If the previous stack-dump wasn't a kernel one, dump the
@@ -72,7 +69,7 @@ show_registers(struct pt_regs *regs)
if (usp != 0)
show_stack(NULL, NULL);

- raw_printk("\nCode: ");
+ printk("\nCode: ");

if (regs->erp < PAGE_OFFSET)
goto bad_value;
@@ -84,76 +81,115 @@ show_registers(struct pt_regs *regs)
* instruction decoding should be in sync at the interesting
* point, but small enough to fit on a row. The regs->erp
* location is pointed out in a ksymoops-friendly way by
- * wrapping the byte for that address in parenthesis.
+ * wrapping the byte for that address in parenthesises.
*/
for (i = -12; i < 12; i++) {
- if (__get_user(c, &((unsigned char *) regs->erp)[i])) {
+ unsigned char c;
+
+ if (__get_user(c, &((unsigned char *)regs->erp)[i])) {
bad_value:
- raw_printk(" Bad IP value.");
+ printk(" Bad IP value.");
break;
}

if (i == 0)
- raw_printk("(%02x) ", c);
+ printk("(%02x) ", c);
else
- raw_printk("%02x ", c);
+ printk("%02x ", c);
}
-
- raw_printk("\n");
+ printk("\n");
}
}

-/*
- * This gets called from entry.S when the watchdog has bitten. Show something
- * similar to an Oops dump, and if the kernel is configured to be a nice doggy;
- * halt instead of reboot.
- */
void
-watchdog_bite_hook(struct pt_regs *regs)
+arch_enable_nmi(void)
{
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- local_irq_disable();
- stop_watchdog();
- show_registers(regs);
+ unsigned long flags;

- while (1)
- ; /* Do nothing. */
-#else
- show_registers(regs);
-#endif
+ local_save_flags(flags);
+ flags |= (1 << 30); /* NMI M flag is at bit 30 */
+ local_irq_restore(flags);
}

-/* This is normally the Oops function. */
-void
-die_if_kernel(const char *str, struct pt_regs *regs, long err)
+extern void (*nmi_handler)(struct pt_regs *);
+void handle_nmi(struct pt_regs *regs)
{
- if (user_mode(regs))
- return;
+#ifdef CONFIG_ETRAXFS
+ reg_intr_vect_r_nmi r;
+#endif

-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- /*
- * This printout might take too long and could trigger
- * the watchdog normally. If NICE_DOGGY is set, simply
- * stop the watchdog during the printout.
- */
- stop_watchdog();
+ if (nmi_handler)
+ nmi_handler(regs);
+
+#ifdef CONFIG_ETRAXFS
+ /* Wait until nmi is no longer active. */
+ do {
+ r = REG_RD(intr_vect, regi_irq, r_nmi);
+ } while (r.ext == regk_intr_vect_on);
#endif
+}

- raw_printk("%s: %04lx\n", str, err & 0xffff);

- show_registers(regs);
+#ifdef CONFIG_BUG
+extern void die_if_kernel(const char *str, struct pt_regs *regs, long err);

-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
+/* Copy of the regs at BUG() time. */
+struct pt_regs BUG_regs;

- do_exit(SIGSEGV);
+void do_BUG(char *file, unsigned int line)
+{
+ printk("kernel BUG at %s:%d!\n", file, line);
+ die_if_kernel("Oops", &BUG_regs, 0);
}
+EXPORT_SYMBOL(do_BUG);

-void arch_enable_nmi(void)
+void fixup_BUG(struct pt_regs *regs)
{
- unsigned long flags;
- local_save_flags(flags);
- flags |= (1<<30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
+ BUG_regs = *regs;
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+ /*
+ * Fixup the BUG arguments through exception handlers.
+ */
+ {
+ const struct exception_table_entry *fixup;
+
+ /*
+ * ERP points at the "break 14" + 2, compensate for the 2
+ * bytes.
+ */
+ fixup = search_exception_tables(instruction_pointer(regs) - 2);
+ if (fixup) {
+ /* Adjust the instruction pointer in the stackframe. */
+ instruction_pointer(regs) = fixup->fixup;
+ arch_fixup(regs);
+ }
+ }
+#else
+ /* Dont try to lookup the filename + line, just dump regs. */
+ do_BUG("unknown", 0);
+#endif
}
+
+/*
+ * Break 14 handler. Save regs and jump into the fixup_BUG.
+ */
+__asm__ ( ".text\n\t"
+ ".global breakh_BUG\n\t"
+ "breakh_BUG:\n\t"
+ SAVE_ALL
+ KGDB_FIXUP
+ "move.d $sp, $r10\n\t"
+ "jsr fixup_BUG\n\t"
+ "nop\n\t"
+ "jump ret_from_intr\n\t"
+ "nop\n\t");
+
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+void
+handle_BUG(struct pt_regs *regs)
+{
+}
+#endif
+#endif
--
1.5.3.6.970.gd25430

2007-12-06 12:56:41

by Jesper Nilsson

Subject: [PATCH 44/47] Minor fixes for CRISv32 io.h

- Shorten include paths for machine dependent header files.
- Add volatile to hardeware register pointers.
- Add spinlocks around critical region.
- Expand macros for handling of leds.

Signed-off-by: Jesper Nilsson <[email protected]>
---
include/asm-cris/arch-v32/io.h | 70 +++++++++++++++++++++++++++++++--------
1 files changed, 55 insertions(+), 15 deletions(-)

diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h
index 5efe4d9..65a2879 100644
--- a/include/asm-cris/arch-v32/io.h
+++ b/include/asm-cris/arch-v32/io.h
@@ -1,9 +1,10 @@
#ifndef _ASM_ARCH_CRIS_IO_H
#define _ASM_ARCH_CRIS_IO_H

-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/gio_defs.h>
+#include <linux/spinlock.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/gio_defs.h>

enum crisv32_io_dir
{
@@ -13,10 +14,11 @@ enum crisv32_io_dir

struct crisv32_ioport
{
- unsigned long* oe;
- unsigned long* data;
- unsigned long* data_in;
+ volatile unsigned long *oe;
+ volatile unsigned long *data;
+ volatile unsigned long *data_in;
unsigned int pin_count;
+ spinlock_t lock;
};

struct crisv32_iopin
@@ -34,22 +36,37 @@ extern struct crisv32_iopin crisv32_led2_red;
extern struct crisv32_iopin crisv32_led3_green;
extern struct crisv32_iopin crisv32_led3_red;

+extern struct crisv32_iopin crisv32_led_net0_green;
+extern struct crisv32_iopin crisv32_led_net0_red;
+extern struct crisv32_iopin crisv32_led_net1_green;
+extern struct crisv32_iopin crisv32_led_net1_red;
+
static inline void crisv32_io_set(struct crisv32_iopin* iopin,
int val)
{
+ long flags;
+ spin_lock_irqsave(&iopin->port->lock, flags);
+
if (val)
*iopin->port->data |= iopin->bit;
else
*iopin->port->data &= ~iopin->bit;
+
+ spin_unlock_irqrestore(&iopin->port->lock, flags);
}

static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
enum crisv32_io_dir dir)
{
+ long flags;
+ spin_lock_irqsave(&iopin->port->lock, flags);
+
if (dir == crisv32_io_dir_in)
*iopin->port->oe &= ~iopin->bit;
else
*iopin->port->oe |= iopin->bit;
+
+ spin_unlock_irqrestore(&iopin->port->lock, flags);
}

static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
@@ -60,28 +77,51 @@ static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
int crisv32_io_get(struct crisv32_iopin* iopin,
unsigned int port, unsigned int pin);
int crisv32_io_get_name(struct crisv32_iopin* iopin,
- char* name);
+ const char *name);

#define LED_OFF 0x00
#define LED_GREEN 0x01
#define LED_RED 0x02
#define LED_ORANGE (LED_GREEN | LED_RED)

-#define LED_NETWORK_SET(x) \
- do { \
- LED_NETWORK_SET_G((x) & LED_GREEN); \
- LED_NETWORK_SET_R((x) & LED_RED); \
+#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
+#define LED_NETWORK_GRP0_SET(x) \
+ do { \
+ LED_NETWORK_GRP0_SET_G((x) & LED_GREEN); \
+ LED_NETWORK_GRP0_SET_R((x) & LED_RED); \
} while (0)
+#else
+#define LED_NETWORK_GRP0_SET(x) while (0) {}
+#endif
+
+#define LED_NETWORK_GRP0_SET_G(x) \
+ crisv32_io_set(&crisv32_led_net0_green, !(x));
+
+#define LED_NETWORK_GRP0_SET_R(x) \
+ crisv32_io_set(&crisv32_led_net0_red, !(x));
+
+#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
+#define LED_NETWORK_GRP1_SET(x) \
+ do { \
+ LED_NETWORK_GRP1_SET_G((x) & LED_GREEN); \
+ LED_NETWORK_GRP1_SET_R((x) & LED_RED); \
+ } while (0)
+#else
+#define LED_NETWORK_GRP1_SET(x) while (0) {}
+#endif
+
+#define LED_NETWORK_GRP1_SET_G(x) \
+ crisv32_io_set(&crisv32_led_net1_green, !(x));
+
+#define LED_NETWORK_GRP1_SET_R(x) \
+ crisv32_io_set(&crisv32_led_net1_red, !(x));
+
#define LED_ACTIVE_SET(x) \
do { \
LED_ACTIVE_SET_G((x) & LED_GREEN); \
LED_ACTIVE_SET_R((x) & LED_RED); \
} while (0)

-#define LED_NETWORK_SET_G(x) \
- crisv32_io_set(&crisv32_led1_green, !(x));
-#define LED_NETWORK_SET_R(x) \
- crisv32_io_set(&crisv32_led1_red, !(x));
#define LED_ACTIVE_SET_G(x) \
crisv32_io_set(&crisv32_led2_green, !(x));
#define LED_ACTIVE_SET_R(x) \
--
1.5.3.6.970.gd25430

2007-12-06 12:56:57

by Jesper Nilsson

Subject: [PATCH 45/47] New default config for CRISv10.

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/defconfig | 796 ++++++++++++++++++---------------------------------
1 files changed, 274 insertions(+), 522 deletions(-)

diff --git a/arch/cris/defconfig b/arch/cris/defconfig
index 9c33ae6..ec857c6 100644
--- a/arch/cris/defconfig
+++ b/arch/cris/defconfig
@@ -1,52 +1,92 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11
-# Mon Jun 20 13:42:02 2005
+# Linux kernel version: 2.6.24-rc3
+# Mon Dec 3 11:34:27 2007
#
CONFIG_MMU=y
-CONFIG_UID16=y
+CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_IOMAP=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NO_IOPORT=y
+CONFIG_NO_IOMEM=y
+CONFIG_FORCE_MAX_ZONEORDER=6
CONFIG_CRIS=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"

#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
+CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_HOTPLUG is not set
-CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set

#
-# Loadable module support
+# IO Schedulers
#
-# CONFIG_MODULES is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"

#
# General setup
@@ -54,12 +94,27 @@ CONFIG_CC_ALIGN_JUMPS=0
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_GENERIC_HARDIRQS=y
-# CONFIG_SMP is not set
CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
# CONFIG_ETRAX_WATCHDOG is not set
CONFIG_ETRAX_FAST_TIMER=y
-# CONFIG_PREEMPT is not set
+# CONFIG_ETRAX_KMALLOCED_MODULES is not set
# CONFIG_OOM_REBOOT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y

#
# Hardware setup
@@ -68,127 +123,180 @@ CONFIG_ETRAX_FAST_TIMER=y
CONFIG_ETRAX100LX_V2=y
# CONFIG_SVINTO_SIM is not set
# CONFIG_ETRAXFS is not set
-# CONFIG_ETRAXFS_SIM is not set
+# CONFIG_CRIS_MACH_ARTPEC3 is not set
+# CONFIG_ETRAX_VCS_SIM is not set
CONFIG_ETRAX_ARCH_V10=y
# CONFIG_ETRAX_ARCH_V32 is not set
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_FLASH_BUSWIDTH=2
+CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
CONFIG_ETRAX_FLASH1_SIZE=4
+# CONFIG_ETRAX_DEBUG_PORT0 is not set
+# CONFIG_ETRAX_DEBUG_PORT1 is not set
+# CONFIG_ETRAX_DEBUG_PORT2 is not set
+# CONFIG_ETRAX_DEBUG_PORT3 is not set
+CONFIG_ETRAX_DEBUG_PORT_NULL=y
+
+#
+# CRIS v10 options
+#
CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
CONFIG_ETRAX_PA_LEDS=y
# CONFIG_ETRAX_PB_LEDS is not set
# CONFIG_ETRAX_CSP0_LEDS is not set
# CONFIG_ETRAX_NO_LEDS is not set
CONFIG_ETRAX_LED1G=2
-CONFIG_ETRAX_LED1R=2
-CONFIG_ETRAX_LED2G=3
-CONFIG_ETRAX_LED2R=3
+CONFIG_ETRAX_LED1R=3
+CONFIG_ETRAX_LED2G=4
+CONFIG_ETRAX_LED2R=5
CONFIG_ETRAX_LED3G=2
CONFIG_ETRAX_LED3R=2
-CONFIG_ETRAX_DEBUG_PORT0=y
-# CONFIG_ETRAX_DEBUG_PORT1 is not set
-# CONFIG_ETRAX_DEBUG_PORT2 is not set
-# CONFIG_ETRAX_DEBUG_PORT3 is not set
-# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
CONFIG_ETRAX_RESCUE_SER0=y
# CONFIG_ETRAX_RESCUE_SER1 is not set
# CONFIG_ETRAX_RESCUE_SER2 is not set
# CONFIG_ETRAX_RESCUE_SER3 is not set
-CONFIG_ETRAX_DEF_R_WAITSTATES=0x95a6
-CONFIG_ETRAX_DEF_R_BUS_CONFIG=0x4
-CONFIG_ETRAX_SDRAM=y
-CONFIG_ETRAX_DEF_R_SDRAM_CONFIG=0x09e05757
-CONFIG_ETRAX_DEF_R_SDRAM_TIMING=0x80008002
-CONFIG_ETRAX_DEF_R_PORT_PA_DIR=0x1d
-CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0x00
-CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=0x00
-CONFIG_ETRAX_DEF_R_PORT_PB_DIR=0x1e
-CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3
+CONFIG_ETRAX_DEF_R_WAITSTATES=95a6
+CONFIG_ETRAX_DEF_R_BUS_CONFIG=104
+# CONFIG_ETRAX_SDRAM is not set
+CONFIG_ETRAX_DEF_R_DRAM_CONFIG=1a200040
+CONFIG_ETRAX_DEF_R_DRAM_TIMING=5611
+CONFIG_ETRAX_DEF_R_PORT_PA_DIR=1c
+CONFIG_ETRAX_DEF_R_PORT_PA_DATA=00
+CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=00
+CONFIG_ETRAX_DEF_R_PORT_PB_DIR=00
+CONFIG_ETRAX_DEF_R_PORT_PB_DATA=ff
# CONFIG_ETRAX_SOFT_SHUTDOWN is not set

#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
# Drivers for built-in interfaces
#
CONFIG_ETRAX_ETHERNET=y
-# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
-CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
CONFIG_ETRAX_SERIAL=y
# CONFIG_ETRAX_SERIAL_FAST_TIMER is not set
# CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST is not set
CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS=5
-CONFIG_ETRAX_SERIAL_PORT0=y
-# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT is not set
-CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT=y
-# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN is not set
-CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN=y
-CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE=y
-# CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA is not set
-# CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB is not set
-# CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED is not set
-CONFIG_ETRAX_SER0_DTR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_RI_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_DSR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_CD_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_DTR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER0_RI_ON_PB_BIT=-1
-CONFIG_ETRAX_SER0_DSR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER0_CD_ON_PB_BIT=-1
+# CONFIG_ETRAX_SERIAL_PORT0 is not set
# CONFIG_ETRAX_SERIAL_PORT1 is not set
-CONFIG_ETRAX_SERIAL_PORT2=y
-# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT is not set
-CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT=y
-# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN is not set
-CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN=y
-CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE=y
-# CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA is not set
-# CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB is not set
-# CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED is not set
-CONFIG_ETRAX_SER2_DTR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_RI_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_DSR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_CD_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_DTR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER2_RI_ON_PB_BIT=-1
-CONFIG_ETRAX_SER2_DSR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER2_CD_ON_PB_BIT=-1
+# CONFIG_ETRAX_SERIAL_PORT2 is not set
# CONFIG_ETRAX_SERIAL_PORT3 is not set
-CONFIG_ETRAX_RS485=y
-# CONFIG_ETRAX_RS485_ON_PA is not set
-# CONFIG_ETRAX_RS485_DISABLE_RECEIVER is not set
-CONFIG_ETRAX_IDE=y
-CONFIG_ETRAX_IDE_DELAY=15
-CONFIG_ETRAX_IDE_PB7_RESET=y
-# CONFIG_ETRAX_IDE_G27_RESET is not set
-CONFIG_ETRAX_USB_HOST=y
-CONFIG_ETRAX_USB_HOST_PORT1=y
-CONFIG_ETRAX_USB_HOST_PORT2=y
+# CONFIG_ETRAX_RS485 is not set
+# CONFIG_ETRAX_IDE is not set
+# CONFIG_ETRAX_USB_HOST is not set
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_ETRAX_PTABLE_SECTOR=65536
# CONFIG_ETRAX_I2C is not set
# CONFIG_ETRAX_GPIO is not set
-CONFIG_ETRAX_RTC=y
-CONFIG_ETRAX_DS1302=y
-# CONFIG_ETRAX_PCF8563 is not set
-CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT=y
-CONFIG_ETRAX_DS1302_RSTBIT=0
-CONFIG_ETRAX_DS1302_SCLBIT=1
-CONFIG_ETRAX_DS1302_SDABIT=0
-CONFIG_ETRAX_DS1302_TRICKLE_CHARGE=0
+# CONFIG_ETRAX_RTC is not set
+# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y

#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_SYS_HYPERVISOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set

@@ -196,16 +304,20 @@ CONFIG_MTD_CONCAT=y
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set

#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
@@ -220,20 +332,18 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_AMDSTD_RETRY=0
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_SHARP is not set
-# CONFIG_MTD_JEDEC is not set

#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set

#
# Self-contained MTD device drivers
@@ -244,7 +354,6 @@ CONFIG_MTD_MTDRAM=y
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
-# CONFIG_MTD_BLKMTD is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
@@ -253,216 +362,54 @@ CONFIG_MTDRAM_ABS_POS=0x0
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set

#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
+# UBI - Unsorted block images
#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
+# CONFIG_MTD_UBI is not set
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_INITRAMFS_SOURCE=""
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
# CONFIG_ATA_OVER_ETH is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-# CONFIG_PARIDE is not set
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-# CONFIG_ISCSI_TCP is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_IP_NF_CONNTRACK is not set
-# CONFIG_IP_NF_CONNTRACK_MARK is not set
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_BT is not set
-# CONFIG_I2C is not set
-
CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y

#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_RTC_CLASS is not set

#
# Input device support
@@ -470,7 +417,7 @@ CONFIG_NET_ETHERNET=y
# CONFIG_INPUT is not set

#
-# Input I/O drivers
+# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
@@ -480,94 +427,39 @@ CONFIG_SERIO=y
# CONFIG_GAMEPORT is not set

#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
# Character devices
#
# CONFIG_VT is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
-# CONFIG_RTC_LIB is not set
-# CONFIG_RTC_CLASS is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set

#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
+# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set

#
# CD-ROM/DVD Filesystems
@@ -587,13 +479,12 @@ CONFIG_DNOTIFY=y
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set

#
# Miscellaneous filesystems
@@ -605,15 +496,15 @@ CONFIG_RAMFS=y
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=y
-CONFIG_JFFS_FS_VERBOSE=0
-# CONFIG_JFFS_PROC_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
@@ -622,12 +513,10 @@ CONFIG_CRAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
@@ -649,181 +538,44 @@ CONFIG_SUNRPC=y
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
# CONFIG_NLS is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# Generic devices
-#
-# CONFIG_SND_MPU401_UART is not set
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-# CONFIG_PARPORT_PC_PCMCIA is not set
-# CONFIG_NET_PCMCIA is not set
-
-#
-# PC-card bridges
-#
-
-#
-# USB support
-#
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-
-#
-# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
-#
-# CONFIG_USB_STORAGE is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-# HID_SUPPORT is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-CONFIG_USB_RTL8150=y
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB ATM/DSL drivers
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
+# CONFIG_DLM is not set

#
# Kernel hacking
#
# CONFIG_PROFILING is not set
# CONFIG_SYSTEM_PROFILER is not set
-# CONFIG_ETRAX_KGDB is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_FRAME_POINTER is not set
-# CONFIG_DEBUG_NMI_OOPS is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SAMPLES is not set

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set

#
-# Hardware crypto devices
-# CONFIG_CRYPTO_HW is not set
-
-#
# Library routines
#
+CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_DMA=y
--
1.5.3.6.970.gd25430

2007-12-06 12:57:25

by Jesper Nilsson

Subject: [PATCH 46/47] Update and improve CRISv32 kernel/time.c

- Shorten include paths to machine dependent header files.
- Register name for first timer is now regi_timer0.
- Remove raw_printk hack, use oops_in_progress instead.
- Add handling of CPU frequency scaling for CRIS.
- Remove regs parameter to timer_interrupt, get them from get_irq_regs instead.
- Whitespace and formatting changes.

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/arch-v32/kernel/time.c | 237 ++++++++++++++++++++++----------------
1 files changed, 139 insertions(+), 98 deletions(-)

diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index 2f7e8e2..3a13dd6 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -1,8 +1,7 @@
-/* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $
- *
+/*
* linux/arch/cris/arch-v32/kernel/time.c
*
- * Copyright (C) 2003 Axis Communications AB
+ * Copyright (C) 2003-2007 Axis Communications AB
*
*/

@@ -14,28 +13,34 @@
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/threads.h>
+#include <linux/cpufreq.h>
#include <asm/types.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/rtc.h>
#include <asm/irq.h>
-
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/timer_defs.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <asm/irq_regs.h>
+
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/timer_defs.h>
+#include <hwregs/intr_vect_defs.h>
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+#include <hwregs/clkgen_defs.h>
+#endif

/* Watchdog defines */
-#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
-#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
-#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */
+#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
+#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
+/* Number of 763 counts before watchdog bites */
+#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)

unsigned long timer_regs[NR_CPUS] =
{
- regi_timer,
+ regi_timer0,
#ifdef CONFIG_SMP
- regi_timer2
+ regi_timer2
#endif
};

@@ -44,12 +49,22 @@ extern int set_rtc_mmss(unsigned long nowtime);
extern int setup_irq(int, struct irqaction *);
extern int have_rtc;

+#ifdef CONFIG_CPU_FREQ
+static int
+cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data);
+
+static struct notifier_block cris_time_freq_notifier_block = {
+ .notifier_call = cris_time_freq_notifier,
+};
+#endif
+
unsigned long get_ns_in_jiffie(void)
{
reg_timer_r_tmr0_data data;
unsigned long ns;

- data = REG_RD(timer, regi_timer, r_tmr0_data);
+ data = REG_RD(timer, regi_timer0, r_tmr0_data);
ns = (TIMER0_DIV - data) * 10;
return ns;
}
@@ -59,31 +74,27 @@ unsigned long do_slow_gettimeoffset(void)
unsigned long count;
unsigned long usec_count = 0;

- static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
+ /* For the first call after boot */
+ static unsigned long count_p = TIMER0_DIV;
static unsigned long jiffies_p = 0;

- /*
- * cache volatile jiffies temporarily; we have IRQs turned off.
- */
+ /* Cache volatile jiffies temporarily; we have IRQs turned off. */
unsigned long jiffies_t;

/* The timer interrupt comes from Etrax timer 0. In order to get
* better precision, we check the current value. It might have
- * underflowed already though.
- */
+ * underflowed already though. */
+ count = REG_RD(timer, regi_timer0, r_tmr0_data);
+ jiffies_t = jiffies;

- count = REG_RD(timer, regi_timer, r_tmr0_data);
- jiffies_t = jiffies;
-
- /*
- * avoiding timer inconsistencies (they are rare, but they happen)...
- * there are one problem that must be avoided here:
- * 1. the timer counter underflows
+ /* Avoiding timer inconsistencies (they are rare, but they happen)
+ * There is one problem that must be avoided here:
+ * 1. the timer counter underflows
*/
if( jiffies_t == jiffies_p ) {
if( count > count_p ) {
- /* Timer wrapped, use new count and prescale
- * increase the time corresponding to one jiffie
+ /* Timer wrapped, use new count and prescale.
+ * Increase the time corresponding to one jiffy.
*/
usec_count = 1000000/HZ;
}
@@ -106,17 +117,15 @@ unsigned long do_slow_gettimeoffset(void)
*/
/* This gives us 1.3 ms to do something useful when the NMI comes */

-/* right now, starting the watchdog is the same as resetting it */
+/* Right now, starting the watchdog is the same as resetting it */
#define start_watchdog reset_watchdog

#if defined(CONFIG_ETRAX_WATCHDOG)
static short int watchdog_key = 42; /* arbitrary 7 bit number */
#endif

-/* number of pages to consider "out of memory". it is normal that the memory
- * is used though, so put this really low.
- */
-
+/* Number of pages to consider "out of memory". It is normal that the memory
+ * is used though, so set this really low. */
#define WATCHDOG_MIN_FREE_PAGES 8

void
@@ -125,14 +134,15 @@ reset_watchdog(void)
#if defined(CONFIG_ETRAX_WATCHDOG)
reg_timer_rw_wd_ctrl wd_ctrl = { 0 };

- /* only keep watchdog happy as long as we have memory left! */
+ /* Only keep watchdog happy as long as we have memory left! */
if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
- /* reset the watchdog with the inverse of the old key */
- watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
+ /* Reset the watchdog with the inverse of the old key */
+ /* Invert key, which is 7 bits */
+ watchdog_key ^= ETRAX_WD_KEY_MASK;
wd_ctrl.cnt = ETRAX_WD_CNT;
wd_ctrl.cmd = regk_timer_start;
wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+ REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
}
#endif
}
@@ -148,7 +158,7 @@ stop_watchdog(void)
wd_ctrl.cnt = ETRAX_WD_CNT;
wd_ctrl.cmd = regk_timer_stop;
wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+ REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
#endif
}

@@ -160,17 +170,28 @@ handle_watchdog_bite(struct pt_regs* regs)
#if defined(CONFIG_ETRAX_WATCHDOG)
extern int cause_of_death;

- raw_printk("Watchdog bite\n");
+ oops_in_progress = 1;
+ printk(KERN_WARNING "Watchdog bite\n");

/* Check if forced restart or unexpected watchdog */
if (cause_of_death == 0xbedead) {
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+ /* There is a bug in Artpec-3 (voodoo TR 78) that requires
+ * us to go to lower frequency for the reset to be reliable
+ */
+ reg_clkgen_rw_clk_ctrl ctrl =
+ REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
+ ctrl.pll = 0;
+ REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
+#endif
while(1);
}

- /* Unexpected watchdog, stop the watchdog and dump registers*/
+ /* Unexpected watchdog, stop the watchdog and dump registers. */
stop_watchdog();
- raw_printk("Oops: bitten by watchdog\n");
- show_registers(regs);
+ printk(KERN_WARNING "Oops: bitten by watchdog\n");
+ show_registers(regs);
+ oops_in_progress = 0;
#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
reset_watchdog();
#endif
@@ -178,21 +199,19 @@ handle_watchdog_bite(struct pt_regs* regs)
#endif
}

-/* last time the cmos clock got updated */
+/* Last time the cmos clock got updated. */
static long last_rtc_update = 0;

/*
* timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
+ * as well as call the "do_timer()" routine every clocktick.
*/
-
-//static unsigned short myjiff; /* used by our debug routine print_timestamp */
-
extern void cris_do_profile(struct pt_regs *regs);

static inline irqreturn_t
-timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+timer_interrupt(int irq, void *dev_id)
{
+ struct pt_regs *regs = get_irq_regs();
int cpu = smp_processor_id();
reg_timer_r_masked_intr masked_intr;
reg_timer_rw_ack_intr ack_intr = { 0 };
@@ -202,11 +221,11 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
if (!masked_intr.tmr0)
return IRQ_NONE;

- /* acknowledge the timer irq */
+ /* Acknowledge the timer irq. */
ack_intr.tmr0 = 1;
REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);

- /* reset watchdog otherwise it resets us! */
+ /* Reset watchdog otherwise it resets us! */
reset_watchdog();

/* Update statistics. */
@@ -218,7 +237,7 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
if (cpu != 0)
return IRQ_HANDLED;

- /* call the real timer interrupt handler */
+ /* Call the real timer interrupt handler */
do_timer(1);

/*
@@ -236,17 +255,17 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
- last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
+ /* Do it again in 60 s */
+ last_rtc_update = xtime.tv_sec - 600;
}
return IRQ_HANDLED;
}

-/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
- * it needs to be IRQF_DISABLED to make the jiffies update work properly
+/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
+ * It needs to be IRQF_DISABLED to make the jiffies update work properly.
*/
-
-static struct irqaction irq_timer = {
- .mask = timer_interrupt,
+static struct irqaction irq_timer = {
+ .handler = timer_interrupt,
.flags = IRQF_SHARED | IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "timer"
@@ -256,27 +275,27 @@ void __init
cris_timer_init(void)
{
int cpu = smp_processor_id();
- reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
- reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
+ reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
+ reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
reg_timer_rw_intr_mask timer_intr_mask;

- /* Setup the etrax timers
+ /* Setup the etrax timers.
* Base frequency is 100MHz, divider 1000000 -> 100 HZ
* We use timer0, so timer1 is free.
* The trig timer is used by the fasttimer API if enabled.
*/

- tmr0_ctrl.op = regk_timer_ld;
+ tmr0_ctrl.op = regk_timer_ld;
tmr0_ctrl.freq = regk_timer_f100;
- REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
- REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
- tmr0_ctrl.op = regk_timer_run;
- REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
-
- /* enable the timer irq */
- timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
- timer_intr_mask.tmr0 = 1;
- REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
+ REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
+ REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
+ tmr0_ctrl.op = regk_timer_run;
+ REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
+
+ /* Enable the timer irq. */
+ timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
+ timer_intr_mask.tmr0 = 1;
+ REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
}

void __init
@@ -284,7 +303,7 @@ time_init(void)
{
reg_intr_vect_rw_mask intr_mask;

- /* probe for the RTC and read it if it exists
+ /* Probe for the RTC and read it if it exists.
* Before the RTC can be probed the loops_per_usec variable needs
* to be initialized to make usleep work. A better value for
* loops_per_usec is calculated by the kernel later once the
@@ -293,52 +312,74 @@ time_init(void)
loops_per_usec = 50;

if(RTC_INIT() < 0) {
- /* no RTC, start at 1980 */
+ /* No RTC, start at 1980 */
xtime.tv_sec = 0;
xtime.tv_nsec = 0;
have_rtc = 0;
} else {
- /* get the current time */
+ /* Get the current time */
have_rtc = 1;
update_xtime_from_cmos();
}

/*
- * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
- * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
+ * Initialize wall_to_monotonic such that adding it to
+ * xtime will yield zero, the tv_nsec field must be normalized
+ * (i.e., 0 <= nsec < NSEC_PER_SEC).
*/
set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);

- /* Start CPU local timer */
+ /* Start CPU local timer. */
cris_timer_init();

- /* enable the timer irq in global config */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.timer = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- /* now actually register the timer irq handler that calls timer_interrupt() */
+ /* Enable the timer irq in global config. */
+ intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
+ intr_mask.timer0 = 1;
+ REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);

- setup_irq(TIMER_INTR_VECT, &irq_timer);
+ /* Now actually register the timer irq handler that calls
+ * timer_interrupt(). */
+ setup_irq(TIMER0_INTR_VECT, &irq_timer);

- /* enable watchdog if we should use one */
+ /* Enable watchdog if we should use one. */

#if defined(CONFIG_ETRAX_WATCHDOG)
- printk("Enabling watchdog...\n");
+ printk(KERN_INFO "Enabling watchdog...\n");
start_watchdog();

/* If we use the hardware watchdog, we want to trap it as an NMI
- and dump registers before it resets us. For this to happen, we
- must set the "m" NMI enable flag (which once set, is unset only
- when an NMI is taken).
-
- The same goes for the external NMI, but that doesn't have any
- driver or infrastructure support yet. */
- {
- unsigned long flags;
- local_save_flags(flags);
- flags |= (1<<30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
- }
+ * and dump registers before it resets us. For this to happen, we
+ * must set the "m" NMI enable flag (which once set, is unset only
+ * when an NMI is taken). */
+ {
+ unsigned long flags;
+ local_save_flags(flags);
+ flags |= (1<<30); /* NMI M flag is at bit 30 */
+ local_irq_restore(flags);
+ }
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+ cpufreq_register_notifier(&cris_time_freq_notifier_block,
+ CPUFREQ_TRANSITION_NOTIFIER);
#endif
}
+
+#ifdef CONFIG_CPU_FREQ
+static int
+cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ struct cpufreq_freqs *freqs = data;
+ if (val == CPUFREQ_POSTCHANGE) {
+ reg_timer_r_tmr0_data data;
+ reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
+ do {
+ data = REG_RD(timer, timer_regs[freqs->cpu],
+ r_tmr0_data);
+ } while (data > 20);
+ REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
+ }
+ return 0;
+}
+#endif
--
1.5.3.6.970.gd25430

2007-12-06 12:57:44

by Jesper Nilsson

Subject: [PATCH 47/47] Add new defconfigs for Artpec-3 and EtraxFS, both CRISv32.

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/artpec_3_defconfig | 583 +++++++++++++++++++++++++++++++++++++++++
arch/cris/etraxfs_defconfig | 586 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 1169 insertions(+), 0 deletions(-)
create mode 100644 arch/cris/artpec_3_defconfig
create mode 100644 arch/cris/etraxfs_defconfig

diff --git a/arch/cris/artpec_3_defconfig b/arch/cris/artpec_3_defconfig
new file mode 100644
index 0000000..55c90a4
--- /dev/null
+++ b/arch/cris/artpec_3_defconfig
@@ -0,0 +1,583 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc3
+# Mon Dec 3 11:18:54 2007
+#
+CONFIG_MMU=y
+CONFIG_ZONE_DMA=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NO_IOPORT=y
+CONFIG_NO_IOMEM=y
+CONFIG_FORCE_MAX_ZONEORDER=6
+CONFIG_CRIS=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# General setup
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
+# CONFIG_ETRAX_WATCHDOG is not set
+CONFIG_ETRAX_FAST_TIMER=y
+# CONFIG_ETRAX_KMALLOCED_MODULES is not set
+# CONFIG_OOM_REBOOT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+
+#
+# Hardware setup
+#
+# CONFIG_ETRAX100LX is not set
+# CONFIG_ETRAX100LX_V2 is not set
+# CONFIG_SVINTO_SIM is not set
+# CONFIG_ETRAXFS is not set
+CONFIG_CRIS_MACH_ARTPEC3=y
+# CONFIG_ETRAX_VCS_SIM is not set
+# CONFIG_ETRAX_ARCH_V10 is not set
+CONFIG_ETRAX_ARCH_V32=y
+CONFIG_ETRAX_DRAM_SIZE=32
+CONFIG_ETRAX_VMEM_SIZE=8
+CONFIG_ETRAX_FLASH_BUSWIDTH=2
+CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
+CONFIG_ETRAX_FLASH1_SIZE=4
+CONFIG_ETRAX_DEBUG_PORT0=y
+# CONFIG_ETRAX_DEBUG_PORT1 is not set
+# CONFIG_ETRAX_DEBUG_PORT2 is not set
+# CONFIG_ETRAX_DEBUG_PORT3 is not set
+# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
+CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
+CONFIG_ETRAX_SERIAL_PORTS=5
+CONFIG_ETRAX_DEF_GIO_PA_OE=1c
+CONFIG_ETRAX_DEF_GIO_PA_OUT=00
+CONFIG_ETRAX_DEF_GIO_PB_OE=00000
+CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PC_OE=00000
+CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
+
+#
+# Artpec-3 options
+#
+CONFIG_ETRAX_L2CACHE=y
+CONFIG_ETRAX_DDR=y
+CONFIG_ETRAX_DDR2_MRS=0
+CONFIG_ETRAX_DDR2_TIMING=0
+CONFIG_ETRAX_DDR2_CONFIG=0
+CONFIG_ETRAX_PIO_CE0_CFG=0
+CONFIG_ETRAX_PIO_CE1_CFG=0
+CONFIG_ETRAX_PIO_CE2_CFG=0
+# CONFIG_CPU_FREQ is not set
+# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
+CONFIG_ETRAX_NBR_LED_GRP_ONE=y
+# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
+CONFIG_ETRAX_LED_G_NET0="PA3"
+CONFIG_ETRAX_LED_R_NET0="PA4"
+CONFIG_ETRAX_V32_LED2G="PA5"
+CONFIG_ETRAX_V32_LED2R="PA6"
+CONFIG_ETRAX_V32_LED3G="PA7"
+CONFIG_ETRAX_V32_LED3R="PA7"
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Drivers for built-in interfaces
+#
+CONFIG_ETRAX_ETHERNET=y
+# CONFIG_ETRAX_IDE is not set
+CONFIG_ETRAX_AXISFLASHMAP=y
+CONFIG_ETRAX_PTABLE_SECTOR=65536
+# CONFIG_ETRAX_I2C is not set
+# CONFIG_ETRAX_GPIO is not set
+# CONFIG_ETRAX_NO_PHY is not set
+# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
+# CONFIG_ETRAX_ETHERNET_GBIT is not set
+# CONFIG_ETRAXFS_SERIAL is not set
+# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
+# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
+# CONFIG_ETRAX_NANDFLASH is not set
+# CONFIG_ETRAX_CARDBUS is not set
+# CONFIG_ETRAX_IOP_FW_LOAD is not set
+# CONFIG_ETRAX_STREAMCOPROC is not set
+# CONFIG_ETRAX_SPI_MMC is not set
+# CONFIG_ETRAX_SPI_MMC_BOARD is not set
+# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_MTDRAM=y
+CONFIG_MTDRAM_TOTAL_SIZE=0
+CONFIG_MTDRAM_ERASE_SIZE=64
+CONFIG_MTDRAM_ABS_POS=0x0
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_HW_RANDOM=y
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PROFILING is not set
+# CONFIG_SYSTEM_PROFILER is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_DMA=y
diff --git a/arch/cris/etraxfs_defconfig b/arch/cris/etraxfs_defconfig
new file mode 100644
index 0000000..808d911
--- /dev/null
+++ b/arch/cris/etraxfs_defconfig
@@ -0,0 +1,586 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc3
+# Fri Nov 30 14:24:26 2007
+#
+CONFIG_MMU=y
+CONFIG_ZONE_DMA=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NO_IOPORT=y
+CONFIG_NO_IOMEM=y
+CONFIG_FORCE_MAX_ZONEORDER=6
+CONFIG_CRIS=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# General setup
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
+# CONFIG_ETRAX_WATCHDOG is not set
+CONFIG_ETRAX_FAST_TIMER=y
+# CONFIG_ETRAX_KMALLOCED_MODULES is not set
+# CONFIG_OOM_REBOOT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+
+#
+# Hardware setup
+#
+# CONFIG_ETRAX100LX is not set
+# CONFIG_ETRAX100LX_V2 is not set
+# CONFIG_SVINTO_SIM is not set
+CONFIG_ETRAXFS=y
+# CONFIG_CRIS_MACH_ARTPEC3 is not set
+# CONFIG_ETRAX_VCS_SIM is not set
+# CONFIG_ETRAX_ARCH_V10 is not set
+CONFIG_ETRAX_ARCH_V32=y
+CONFIG_ETRAX_DRAM_SIZE=32
+CONFIG_ETRAX_FLASH_BUSWIDTH=2
+CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
+CONFIG_ETRAX_FLASH1_SIZE=4
+CONFIG_ETRAX_DEBUG_PORT0=y
+# CONFIG_ETRAX_DEBUG_PORT1 is not set
+# CONFIG_ETRAX_DEBUG_PORT2 is not set
+# CONFIG_ETRAX_DEBUG_PORT3 is not set
+# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
+CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
+
+#
+# ETRAX FS options
+#
+CONFIG_ETRAX_SERIAL_PORTS=4
+CONFIG_ETRAX_MEM_GRP1_CONFIG=4044a
+CONFIG_ETRAX_MEM_GRP2_CONFIG=0
+CONFIG_ETRAX_MEM_GRP3_CONFIG=0
+CONFIG_ETRAX_MEM_GRP4_CONFIG=0
+CONFIG_ETRAX_SDRAM_GRP0_CONFIG=336
+CONFIG_ETRAX_SDRAM_GRP1_CONFIG=0
+CONFIG_ETRAX_SDRAM_TIMING=104a
+CONFIG_ETRAX_SDRAM_COMMAND=0
+CONFIG_ETRAX_DEF_GIO_PA_OE=1c
+CONFIG_ETRAX_DEF_GIO_PA_OUT=00
+CONFIG_ETRAX_DEF_GIO_PB_OE=00000
+CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PC_OE=00000
+CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PD_OE=00000
+CONFIG_ETRAX_DEF_GIO_PD_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PE_OE=00000
+CONFIG_ETRAX_DEF_GIO_PE_OUT=00000
+# CONFIG_CPU_FREQ is not set
+# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
+CONFIG_ETRAX_NBR_LED_GRP_ONE=y
+# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
+CONFIG_ETRAX_LED_G_NET0="PA3"
+CONFIG_ETRAX_LED_R_NET0="PA4"
+CONFIG_ETRAX_V32_LED2G="PA5"
+CONFIG_ETRAX_V32_LED2R="PA6"
+CONFIG_ETRAX_V32_LED3G="PA7"
+CONFIG_ETRAX_V32_LED3R="PA7"
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Drivers for built-in interfaces
+#
+CONFIG_ETRAX_ETHERNET=y
+# CONFIG_ETRAX_IDE is not set
+CONFIG_ETRAX_AXISFLASHMAP=y
+CONFIG_ETRAX_PTABLE_SECTOR=65536
+# CONFIG_ETRAX_I2C is not set
+# CONFIG_ETRAX_GPIO is not set
+# CONFIG_ETRAX_NO_PHY is not set
+# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
+# CONFIG_ETRAX_ETHERNET_IFACE1 is not set
+# CONFIG_ETRAXFS_SERIAL is not set
+# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
+# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
+# CONFIG_ETRAX_NANDFLASH is not set
+# CONFIG_ETRAX_CARDBUS is not set
+# CONFIG_ETRAX_IOP_FW_LOAD is not set
+# CONFIG_ETRAX_STREAMCOPROC is not set
+# CONFIG_ETRAX_SPI_MMC is not set
+# CONFIG_ETRAX_SPI_MMC_BOARD is not set
+# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_MTDRAM=y
+CONFIG_MTDRAM_TOTAL_SIZE=0
+CONFIG_MTDRAM_ERASE_SIZE=64
+CONFIG_MTDRAM_ABS_POS=0x0
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_HW_RANDOM=y
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PROFILING is not set
+# CONFIG_SYSTEM_PROFILER is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_DMA=y
--
1.5.3.6.970.gd25430

2007-12-06 13:58:17

by David Miller

Subject: Re: [PATCH 27/47] Update CRISv10 rescue head.s

From: Jesper Nilsson <[email protected]>
Date: Fri, 30 Nov 2007 16:13:29 +0100
^^^^^^^^^^^

Any particular reason for the 6 day long delay in these mails going
out or is your clock simply wrong?

As co-postmaster, I am noticing that your postings are bouncing at a
lot of sites because of this. There are several that impose things
like 96-hour-old limits on date fields in received mails.

2007-12-07 00:46:47

by Jesper Nilsson

Subject: Re: [PATCH 27/47] Update CRISv10 rescue head.s

On Thu, Dec 06, 2007 at 05:58:04AM -0800, David Miller wrote:
> From: Jesper Nilsson <[email protected]>
> Date: Fri, 30 Nov 2007 16:13:29 +0100
> ^^^^^^^^^^^
>
> Any particular reason for the 6 day long delay in these mails going
> out or is your clock simply wrong?
> As co-postmaster, I am noticing that your postings are bouncing at a
> lot of sites because of this. There are several that impose things
> like 96-hour-old limits on date fields in received mails.

Sorry, this is not intended. I have no idea why the date was set to
a random value, but it was certainly not my intention.
I did run a script to send the mails, but it's not
clear to me why the date would be screwed up.
Another lesson to be learned I guess, back to manual submission.

/^JN - Jesper Nilsson
--
Jesper Nilsson -- [email protected]

2007-12-12 10:52:55

by Andrew Morton

Subject: Re: [PATCH 00/47] CRIS patches for CRISv32 EtraxFS and ARTPEC-3

On Thu, 29 Nov 2007 17:02:22 +0100 Jesper Nilsson <[email protected]> wrote:

> Hi,
>
> This patchset contains the differences to add support for the EtraxFS and
> ARTPEC-3 CPUs, both of the CRISv32 family. Both chips can now be compiled
> with minimal configs.
>
> To compile you'll need the Axis gcc cross port for CRISv32, it is mentioned
> in http://marc.info/?l=linux-kernel&m=119337976126184&w=2 how to get this.
>
> Still missing to allow full compile is include/linux/mtd/mtdram.h,
> see http://marc.info/?l=linux-kernel&m=119373777301863&w=2
>
> This is step two in syncing the Axis internal changes with mainline Linux,
> with the final goal being getting the CRIS port to the same level as
> the rest of the kernel.
>
> I've tried to remove as much checkpatch warnings and errors as possible,
> but some remain, mostly (I think you'll agree) spurious warnings,
> although there's also a bunch of generated files which don't conform,
> but I hope to fix this at the source later on.
>
> I realise this is a hefty chunk of code to review, but any suggestions
> on improvements are thankfully received.
>
> The changes are also available in the export2 branch at
>
> git://http://www.jni.nu/axis.git
>

I don't think there's much point in me merging these. Please ask Linus to
pull that tree once the 2.6.25 merge window opens.

2007-12-12 11:10:18

by Andrew Morton

Subject: Re: [PATCH 02/47] Add new driver files for Artpec-3.

On Thu, 29 Nov 2007 17:03:41 +0100 Jesper Nilsson <[email protected]> wrote:

> Adds gpio and nandflash handling for Artpec-3.
>
> ...
>
> +static volatile unsigned long *data_out[NUM_PORTS] = {

all these volatiles really shouldn't be here.

> +static void
> +gpio_set_alarm(struct gpio_private *priv)
> +{
> + int bit;
> + int intr_cfg;
> + int mask;
> + int pins;
> + unsigned long flags;
> +
> + local_irq_save(flags);

Will never run on SMP?

> +
> +inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
> +{
> + /* Set direction 0=unchanged 1=input,
> + * return mask with 1=input
> + */
> + unsigned long flags;
> + unsigned long dir_shadow;
> +
> + local_irq_save(flags);
> + dir_shadow = *dir_oe[priv->minor];
> + dir_shadow &= ~(arg & changeable_dir[priv->minor]);
> + *dir_oe[priv->minor] = dir_shadow;
> + local_irq_restore(flags);
> +
> + if (priv->minor == GPIO_MINOR_C)
> + dir_shadow ^= 0xFFFF; /* Only 16 bits */
> +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
> + else if (priv->minor == GPIO_MINOR_V)
> + dir_shadow ^= 0xFFFF; /* Only 16 bits */
> +#endif
> + else
> + dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
> +
> + return dir_shadow;
> +
> +} /* setget_input */
> +
> +inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
> +{
> + unsigned long flags;
> + unsigned long dir_shadow;
> +
> + local_irq_save(flags);
> + dir_shadow = *dir_oe[priv->minor];
> + dir_shadow |= (arg & changeable_dir[priv->minor]);
> + *dir_oe[priv->minor] = dir_shadow;
> + local_irq_restore(flags);
> + return dir_shadow;
> +} /* setget_output */

The `inline's here are surely deoptimising the code.

> +static int
> +gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
> +
> +static int
> +gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg);
> +
> +static int
> +gpio_ioctl(struct inode *inode, struct file *file,
> + unsigned int cmd, unsigned long arg)
> +{
> + unsigned long flags;
> + unsigned long val;
> + unsigned long shadow;
> + struct gpio_private *priv = (struct gpio_private *)file->private_data;

Unneeded and undesirable cast of void*.

> +
> + if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
> + return -EINVAL;

Not ENOTTY?

> + /* Check for special ioctl handlers first */
> +
> +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
> + if (priv->minor == GPIO_MINOR_V)
> + return virtual_gpio_ioctl(file, cmd, arg);
> +#endif
> +
> + if (priv->minor == GPIO_MINOR_LEDS)
> + return gpio_leds_ioctl(cmd, arg);
> +
> + if (priv->minor >= GPIO_MINOR_PWM0 &&
> + priv->minor <= GPIO_MINOR_LAST_PWM)
> + return gpio_pwm_ioctl(priv, cmd, arg);
> +
> + switch (_IOC_NR(cmd)) {
> + case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
> + /* Read the port. */
> + return *data_in[priv->minor];

Really. Nuke the volatiles, use readl().

> + break;
> + case IO_SETBITS:
> + local_irq_save(flags);
> + /* Set changeable bits with a 1 in arg. */
> + shadow = *data_out[priv->minor];

readl()

> + shadow |= (arg & changeable_bits[priv->minor]);
> + *data_out[priv->minor] = shadow;

writel()

> + local_irq_restore(flags);
> + break;
> + case IO_CLRBITS:
> + local_irq_save(flags);
> + /* Clear changeable bits with a 1 in arg. */
> + shadow = *data_out[priv->minor];
> + shadow &= ~(arg & changeable_bits[priv->minor]);
> + *data_out[priv->minor] = shadow;
> + local_irq_restore(flags);
> + break;
> + case IO_HIGHALARM:
> + /* Set alarm when bits with 1 in arg go high. */
> + priv->highalarm |= arg;
> + gpio_set_alarm(priv);
> + break;
> + case IO_LOWALARM:
> + /* Set alarm when bits with 1 in arg go low. */
> + priv->lowalarm |= arg;
> + gpio_set_alarm(priv);
> + break;
> + case IO_CLRALARM:
> + /* Clear alarm for bits with 1 in arg. */
> + priv->highalarm &= ~arg;
> + priv->lowalarm &= ~arg;
> + gpio_set_alarm(priv);
> + break;
> + case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
> + /* Read direction 0=input 1=output */
> + return *dir_oe[priv->minor];
> + case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
> + /* Set direction 0=unchanged 1=input,
> + * return mask with 1=input
> + */
> + return setget_input(priv, arg);
> + break;

That break is a bit pointless.

> + case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
> + /* Set direction 0=unchanged 1=output,
> + * return mask with 1=output
> + */
> + return setget_output(priv, arg);
> +
> + case IO_CFG_WRITE_MODE:
> + {
> + unsigned long dir_shadow;
> + dir_shadow = *dir_oe[priv->minor];
> +
> + priv->clk_mask = arg & 0xFF;
> + priv->data_mask = (arg >> 8) & 0xFF;
> + priv->write_msb = (arg >> 16) & 0x01;
> + /* Check if we're allowed to change the bits and
> + * the direction is correct
> + */
> + if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
> + (priv->data_mask & changeable_bits[priv->minor]) &&
> + (priv->clk_mask & dir_shadow) &&
> + (priv->data_mask & dir_shadow))) {
> + priv->clk_mask = 0;
> + priv->data_mask = 0;
> + return -EPERM;
> + }
> + break;
> + }
> + case IO_READ_INBITS:
> + /* *arg is result of reading the input pins */
> + val = *data_in[priv->minor];
> + if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))

Strange cast. Maybe void __user *?

> + return -EFAULT;
> + return 0;
> + break;
> + case IO_READ_OUTBITS:
> + /* *arg is result of reading the output shadow */
> + val = *data_out[priv->minor];
> + if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
> + return -EFAULT;
> + break;
> + case IO_SETGET_INPUT:
> + /* bits set in *arg is set to input,
> + * *arg updated with current input pins.
> + */
> + if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
> + return -EFAULT;
> + val = setget_input(priv, val);
> + if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
> + return -EFAULT;
> + break;
> + case IO_SETGET_OUTPUT:
> + /* bits set in *arg is set to output,
> + * *arg updated with current output pins.
> + */
> + if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
> + return -EFAULT;
> + val = setget_output(priv, val);
> + if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
> + return -EFAULT;
> + break;
> + default:
> + return -EINVAL;
> + } /* switch */
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
> +static int
> +virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
> +{
> + unsigned long flags;
> + unsigned short val;
> + unsigned short shadow;
> + struct gpio_private *priv = (struct gpio_private *)file->private_data;

unneeded cast.

> + int mode;
> + reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
> + .ccd_val = 0,
> + .ccd_override = regk_gio_no,
> + .mode = regk_gio_no
> + };
> + int allocstatus;
> +
> + if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
> + return -EFAULT;
> + rw_pwm_ctrl.mode = mode;
> + if (mode != PWM_OFF)
> + allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
> + else
> + allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
> + if (allocstatus)
> + return allocstatus;
> + REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
> + 12 * pwm_port, rw_pwm_ctrl);
> + return 0;
> +}

You might like to run sparse across this code (make C=1)

> +static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
> +{
> + struct io_pwm_set_period periods;
> + reg_gio_rw_pwm0_var rw_pwm_widths;
> +
> + if (copy_from_user(&periods, (struct io_pwm_set_period *) arg,
> + sizeof(periods)))
> + return -EFAULT;
> + if (periods.lo > 8191 || periods.hi > 8191)
> + return -EINVAL;

(Can't find the definition of io_pwm_set_period)

I hope .lo and .hi are unsigned.

> + rw_pwm_widths.lo = periods.lo;
> + rw_pwm_widths.hi = periods.hi;
> + REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
> + 12 * pwm_port, rw_pwm_widths);
> + return 0;
> +}
> +
> +static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
> +{
> + unsigned int duty;
> + reg_gio_rw_pwm0_data rw_pwm_duty;
> +
> + if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
> + return -EFAULT;
> + if (duty > 255)
> + return -EINVAL;
> + rw_pwm_duty.data = duty;
> + REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
> + 12 * pwm_port, rw_pwm_duty);
> + return 0;
> +}
> +
> +static int
> +gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg)
> +{
> + int pwm_port = priv->minor - GPIO_MINOR_PWM0;
> +
> + switch (_IOC_NR(cmd)) {
> + case IO_PWM_SET_MODE:
> + return gpio_pwm_set_mode(arg, pwm_port);
> + case IO_PWM_SET_PERIOD:
> + return gpio_pwm_set_period(arg, pwm_port);
> + case IO_PWM_SET_DUTY:
> + return gpio_pwm_set_duty(arg, pwm_port);
> + default:
> + return -EINVAL;
> + }
> + return 0;
> +}

What a lot of ioctls

> +struct file_operations gpio_fops = {
> + .owner = THIS_MODULE,
> + .poll = gpio_poll,
> + .ioctl = gpio_ioctl,
> + .write = gpio_write,
> + .open = gpio_open,
> + .release = gpio_release,
> +};

static?

> +static __init int
> +gpio_init(void)

Normally we'd do `static int __init'. Cosmetic.

> +{
> + int res;
> +
> + /* do the formalities */
> +
> + res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
> + if (res < 0) {
> + printk(KERN_ERR "gpio: couldn't get a major number.\n");
> + return res;
> + }
> +
> + /* Clear all leds */
> + LED_NETWORK_GRP0_SET(0);
> + LED_NETWORK_GRP1_SET(0);
> + LED_ACTIVE_SET(0);
> + LED_DISK_READ(0);
> + LED_DISK_WRITE(0);
> +
> + printk(KERN_INFO "ETRAX FS GPIO driver v2.6, (c) 2003-2007 "
> + "Axis Communications AB\n");
> + if (request_irq(GIO_INTR_VECT, gpio_interrupt,
> + IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist))
> + printk(KERN_ERR "err: irq for gpio\n");

Should handle this properly.

> + /* No IRQs by default. */
> + REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
> +
> +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
> + virtual_gpio_init();
> +#endif
> +
> + return res;
> +}
>
> ...
>
> +/*
> + * hardware specific access to control-lines
> + */
> +static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
> + unsigned int ctrl)
> +{
> + unsigned long flags;
> + reg_pio_rw_dout dout;
> + struct nand_chip *this = mtd->priv;
> +
> + local_irq_save(flags);
> +
> + /* control bits change */
> + if (ctrl & NAND_CTRL_CHANGE) {
> + dout = REG_RD(pio, regi_pio, rw_dout);
> + dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
> +
> +#if !MANUAL_ALE_CLE_CONTROL
> + if (ctrl & NAND_ALE) {
> + /* A0 = ALE high */
> + this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
> + regi_pio, rw_io_access1);
> + } else if (ctrl & NAND_CLE) {
> + /* A1 = CLE high */
> + this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
> + regi_pio, rw_io_access2);
> + } else {
> + /* A1 = CLE and A0 = ALE low */
> + this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
> + regi_pio, rw_io_access0);
> + }
> +#else
> +
> + dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
> + dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
> +#endif
> + REG_WR(pio, regi_pio, rw_dout, dout);
> + }
> +
> + /* command to chip */
> + if (cmd != NAND_CMD_NONE)
> + writeb(cmd, this->IO_ADDR_W);
> +
> + local_irq_restore(flags);
> +}

Maybe the MTD developers should have a look at this code.

> +/*
> +* read device ready pin
> +*/
> +int crisv32_device_ready(struct mtd_info *mtd)
> +{
> + reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
> + return din.rdy;
> +}

Please check that all new global symbols do indeed need to be global.

> +/*
> + * Main initialization routine
> + */
> +struct mtd_info *__init crisv32_nand_flash_probe(void)
> +{
> + void __iomem *read_cs;
> + void __iomem *write_cs;
> +
> + struct nand_chip *this;
> + int err = 0;
> +
> + reg_pio_rw_man_ctrl man_ctrl = {
> + .regf_NCE = regk_pio_yes,
> +#if MANUAL_ALE_CLE_CONTROL
> + .regf_ALE = regk_pio_yes,
> + .regf_CLE = regk_pio_yes
> +#endif
> + };
> + reg_pio_rw_oe oe = {
> + .regf_NCE = regk_pio_yes,
> +#if MANUAL_ALE_CLE_CONTROL
> + .regf_ALE = regk_pio_yes,
> + .regf_CLE = regk_pio_yes
> +#endif
> + };
> + reg_pio_rw_dout dout = { .regf_NCE = 1 };
> +
> + /* Allocate pio pins to pio */
> + crisv32_pinmux_alloc_fixed(pinmux_pio);
> + /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
> + REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
> + REG_WR(pio, regi_pio, rw_dout, dout);
> + REG_WR(pio, regi_pio, rw_oe, oe);
> +
> + /* Allocate memory for MTD device structure and private data */
> + crisv32_mtd = kmalloc(sizeof(struct mtd_info) +
> + sizeof(struct nand_chip), GFP_KERNEL);
> + if (!crisv32_mtd) {
> + printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
> + "device structure.\n");
> + err = -ENOMEM;
> + return NULL;
> + }
> +
> + read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
> + rw_io_access0);
> +
> + /* Get pointer to private data */
> + this = (struct nand_chip *) (&crisv32_mtd[1]);

What on earth is going on here? We cast a struct mtd_info* into a struct
nand_chip*?

otoh maybe I don't want to know what's going on here.

oic we've jammed two structs together into the same kmalloc. If that's
_really_ worth bothering about, why not do it properly?

struct foo {
struct mtd_info a;
struct nand_chip b;
};

rather than this gruesomeness.

> + /* Initialize structures */
> + memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
> + memset((char *) this, 0, sizeof(struct nand_chip));

kzalloc()...

> + /* Link the private data with the MTD structure */
> + crisv32_mtd->priv = this;
> +
> + /* Set address of NAND IO lines */
> + this->IO_ADDR_R = read_cs;
> + this->IO_ADDR_W = write_cs;
> + this->cmd_ctrl = crisv32_hwcontrol;
> + this->dev_ready = crisv32_device_ready;
> + /* 20 us command delay time */
> + this->chip_delay = 20;
> + this->ecc.mode = NAND_ECC_SOFT;
> +
> + /* Enable the following for a flash based bad block table */
> + /* this->options = NAND_USE_FLASH_BBT; */
> +
> + /* Scan to find existance of the device */
> + if (nand_scan(crisv32_mtd, 1)) {
> + err = -ENXIO;
> + goto out_mtd;
> + }
> +
> + return crisv32_mtd;
> +
> +out_mtd:
> + kfree(crisv32_mtd);
> + return NULL;
> +}

This code all looks rather hacky.

2007-12-12 11:14:26

by Andrew Morton

Subject: Re: [PATCH 06/47] Add serial driver for CRISv32.

On Thu, 29 Nov 2007 17:23:14 +0100 Jesper Nilsson <[email protected]> wrote:

> +static void serial_cris_set_mctrl(struct uart_port *port, unsigned int mctrl)
> +{
> + struct uart_cris_port *up = (struct uart_cris_port *)port;

use container_of() here

> +static irqreturn_t dma_tr_interrupt(int irq, void *dev_id)
> +{
> + struct uart_cris_port *up = (struct uart_cris_port *)dev_id;

This driver is a somewhat depressing read too.

2007-12-12 11:17:25

by Andrew Morton

Subject: Re: [PATCH 15/47] Minor fixes to mm/fault.c for CRIS.

On Fri, 30 Nov 2007 13:59:57 +0100 Jesper Nilsson <[email protected]> wrote:

> @@ -360,7 +247,7 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
> up_read(&mm->mmap_sem);
> printk("VM: killing process %s\n", tsk->comm);
> if (user_mode(regs))
> - do_group_exit(SIGKILL);
> + do_exit(SIGKILL);

Is this change correct?

2007-12-12 11:19:18

by Andrew Morton

Subject: Re: [PATCH 21/47] New version of CRISv32 I2C driver.

On Fri, 30 Nov 2007 15:54:01 +0100 Jesper Nilsson <[email protected]> wrote:

> +int
> +i2c_write(unsigned char theSlave, void *data, size_t nbytes)
> +{
> + int error, cntr = 3;
> + unsigned char bytes_wrote = 0;
> + unsigned char value;
> + unsigned long flags;
> +
> + spin_lock(&i2c_lock);
> +
> + do {
> + error = 0;
> + /*
> + * we don't like to be interrupted
> + */
> + local_irq_save(flags);
> +
> + i2c_start();
> + /*

Well if you _are_ interrupted prior to the local_irq_save() you'll deadlock
on i2c_lock?

2007-12-12 11:21:35

by Andrew Morton

Subject: Re: [PATCH 29/47] Update CRISv32 traps.c

On Fri, 30 Nov 2007 16:22:50 +0100 Jesper Nilsson <[email protected]> wrote:

> +#ifdef CONFIG_DEBUG_BUGVERBOSE
> +void
> +handle_BUG(struct pt_regs *regs)
> {
> - asm volatile("setf m");
> + struct bug_frame f;
> + unsigned char c;
> + unsigned long irp = regs->irp;
> +
> + if (__copy_from_user(&f, (const void __user *)(irp - 8), sizeof f))
> + return;
> + if (f.prefix != BUG_PREFIX || f.magic != BUG_MAGIC)
> + return;
> + if (__get_user(c, f.filename))
> + f.filename = "<bad filename>";
> +
> + printk("kernel BUG at %s:%d!\n", f.filename, f.line);
> }
> +#endif

Why is it accessing user memory in the BUG handler?

2007-12-12 11:23:54

by Andrew Morton

Subject: Re: [PATCH 39/47] Update and improve CRISv32 fasttimer.c

On Fri, 30 Nov 2007 17:46:11 +0100 Jesper Nilsson <[email protected]> wrote:

> arch/cris/arch-v32/kernel/fasttimer.c | 519 ++++++++++++--------------------

I'm suspecting that most of the inlines which this patch retains are
deoptimising the code.

This file still seems to use two-spaces for indentation in many places.

2007-12-12 11:24:58

by Andrew Morton

Subject: Re: [PATCH 42/47] Minor updates to CRISv32 kernel/process.c

On Mon, 3 Dec 2007 10:54:15 +0100 Jesper Nilsson <[email protected]> wrote:

> - /* Parameter to ret_from_sys_call. 0 is don't restart the syscall. */
> + /* Paramater to ret_from_sys_call. 0 is don't restart the syscall. */

"Parameter".

2007-12-12 11:29:53

by Andrew Morton

Subject: Re: [PATCH 44/47] Minor fixes for CRISv32 io.h

On Mon, 3 Dec 2007 11:16:25 +0100 Jesper Nilsson <[email protected]> wrote:

> - Shorten include paths for machine dependent header files.
> - Add volatile to hardeware register pointers.
> - Add spinlocks around critical region.
> - Expand macros for handling of leds.
>
> ...
>
> struct crisv32_ioport
> {
> - unsigned long* oe;
> - unsigned long* data;
> - unsigned long* data_in;
> + volatile unsigned long *oe;
> + volatile unsigned long *data;
> + volatile unsigned long *data_in;
> unsigned int pin_count;
> + spinlock_t lock;
> };

tabs.

> struct crisv32_iopin
> @@ -34,22 +36,37 @@ extern struct crisv32_iopin crisv32_led2_red;
> extern struct crisv32_iopin crisv32_led3_green;
> extern struct crisv32_iopin crisv32_led3_red;
>
> +extern struct crisv32_iopin crisv32_led_net0_green;
> +extern struct crisv32_iopin crisv32_led_net0_red;
> +extern struct crisv32_iopin crisv32_led_net1_green;
> +extern struct crisv32_iopin crisv32_led_net1_red;
> +
> static inline void crisv32_io_set(struct crisv32_iopin* iopin,
> int val)
> {
> + long flags;
> + spin_lock_irqsave(&iopin->port->lock, flags);
> +
> if (val)
> *iopin->port->data |= iopin->bit;
> else
> *iopin->port->data &= ~iopin->bit;
> +
> + spin_unlock_irqrestore(&iopin->port->lock, flags);
> }
>
> static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
> enum crisv32_io_dir dir)
> {
> + long flags;
> + spin_lock_irqsave(&iopin->port->lock, flags);
> +
> if (dir == crisv32_io_dir_in)
> *iopin->port->oe &= ~iopin->bit;
> else
> *iopin->port->oe |= iopin->bit;
> +
> + spin_unlock_irqrestore(&iopin->port->lock, flags);
> }

These surely are far too large to be inlined.

> +#define LED_NETWORK_GRP0_SET(x) \
> + do { \
> + LED_NETWORK_GRP0_SET_G((x) & LED_GREEN); \
> + LED_NETWORK_GRP0_SET_R((x) & LED_RED); \
> } while (0)
> +#else
> +#define LED_NETWORK_GRP0_SET(x) while (0) {}
> +#endif
> +
> +#define LED_NETWORK_GRP0_SET_G(x) \
> + crisv32_io_set(&crisv32_led_net0_green, !(x));
> +
> +#define LED_NETWORK_GRP0_SET_R(x) \
> + crisv32_io_set(&crisv32_led_net0_red, !(x));
> +
> +#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
> +#define LED_NETWORK_GRP1_SET(x) \
> + do { \
> + LED_NETWORK_GRP1_SET_G((x) & LED_GREEN); \
> + LED_NETWORK_GRP1_SET_R((x) & LED_RED); \
> + } while (0)
> +#else
> +#define LED_NETWORK_GRP1_SET(x) while (0) {}
> +#endif
> +
> +#define LED_NETWORK_GRP1_SET_G(x) \
> + crisv32_io_set(&crisv32_led_net1_green, !(x));
> +
> +#define LED_NETWORK_GRP1_SET_R(x) \
> + crisv32_io_set(&crisv32_led_net1_red, !(x));
> +
> #define LED_ACTIVE_SET(x) \
> do { \
> LED_ACTIVE_SET_G((x) & LED_GREEN); \
> LED_ACTIVE_SET_R((x) & LED_RED); \
> } while (0)
>

PLease generally prefer (lower-case) inlined functions over macros. They
are cleaner, clearer, safer and have better typechecking.

Several of the above macros reference their argument more than once and
hence cannot be used as, for example,

LED_ACTIVE_SET(foo++);

2007-12-12 11:33:47

by Andrew Morton

Subject: Re: [PATCH 46/47] Update and improve CRISv32 kernel/time.c

On Tue, 4 Dec 2007 17:25:45 +0100 Jesper Nilsson <[email protected]> wrote:

> +#ifdef CONFIG_CPU_FREQ
> + cpufreq_register_notifier(&cris_time_freq_notifier_block,
> + CPUFREQ_TRANSITION_NOTIFIER);
> #endif

include/linux/cpufreq.h has

#ifdef CONFIG_CPU_FREQ
...
#else /* CONFIG_CPU_FREQ */
static inline int cpufreq_register_notifier(struct notifier_block *nb,
unsigned int list)
{
return 0;
}


the idea is that you remove the above ifdefs and also the ifdefs around
cris_time_freq_notifier_block and then gcc magically removes
cris_time_freq_notifier_block from your generated code.

Advantages: no ifdefs, and full typechecking even when CONFIG_CPU_FREQ=n.


cpufreq_register_notifier() can fail but this code pretends otherwise...

2007-12-12 13:28:50

by Adrian Bunk

Subject: Re: [PATCH 00/47] CRIS patches for CRISv32 EtraxFS and ARTPEC-3

On Wed, Dec 12, 2007 at 02:52:12AM -0800, Andrew Morton wrote:
> On Thu, 29 Nov 2007 17:02:22 +0100 Jesper Nilsson <[email protected]> wrote:
>
> > Hi,
> >
> > This patchset contains the differences to add support for the EtraxFS and
> > ARTPEC-3 CPUs, both of the CRISv32 family. Both chips can now be compiled
> > with minimal configs.
> >
> > To compile you'll need the Axis gcc cross port for CRISv32, it is mentioned
> > in http://marc.info/?l=linux-kernel&m=119337976126184&w=2 how to get this.
> >
> > Still missing to allow full compile is include/linux/mtd/mtdram.h,
> > see http://marc.info/?l=linux-kernel&m=119373777301863&w=2
> >
> > This is step two in syncing the Axis internal changes with mainline Linux,
> > with the final goal being getting the CRIS port to the same level as
> > the rest of the kernel.
> >
> > I've tried to remove as much checkpatch warnings and errors as possible,
> > but some remain, mostly (I think you'll agree) spurious warnings,
> > although there's also a bunch of generated files which don't conform,
> > but I hope to fix this at the source later on.
> >
> > I realise this is a hefty chunk of code to review, but any suggestions
> > on improvements are thankfully received.
> >
> > The changes are also available in the export2 branch at
> >
> > git://http://www.jni.nu/axis.git
>
> I don't think there's much point in me merging these. Please ask Linus to
> pull that tree once the 2.6.25 merge window opens.

This sounds reasonable for the arch/cris/ and include/asm-cris/ parts,
but shouldn't the rest go through the maintainers?

cu
Adrian

--

"Is there not promise of rain?" Ling Tan asked suddenly out
of the darkness. There had been need of rain for many days.
"Only a promise," Lao Er said.
Pearl S. Buck - Dragon Seed

2007-12-12 13:29:10

by Jesper Nilsson

Subject: Re: [PATCH 00/47] CRIS patches for CRISv32 EtraxFS and ARTPEC-3

On Wed, Dec 12, 2007 at 02:52:12AM -0800, Andrew Morton wrote:
> > ...
> > The changes are also available in the export2 branch at
> >
> > git://http://www.jni.nu/axis.git
> >
>
> I don't think there's much point in me merging these. Please ask Linus to
> pull that tree once the 2.6.25 merge window opens.

Ok, I'll do that. Thanks for all the comments, I really appreciate
you taking the time to review.

/^JN - Jesper Nilsson
--
Jesper Nilsson -- [email protected]

2007-12-12 13:37:01

by Jesper Nilsson

Subject: Re: [PATCH 15/47] Minor fixes to mm/fault.c for CRIS.

On Wed, Dec 12, 2007 at 03:17:13AM -0800, Andrew Morton wrote:
> On Fri, 30 Nov 2007 13:59:57 +0100 Jesper Nilsson <[email protected]> wrote:
>
> > @@ -360,7 +247,7 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
> > up_read(&mm->mmap_sem);
> > printk("VM: killing process %s\n", tsk->comm);
> > if (user_mode(regs))
> > - do_group_exit(SIGKILL);
> > + do_exit(SIGKILL);
>
> Is this change correct?

No, good catch, that's a change since we last imported to the internal tree.

/^JN - Jesper Nilsson
--
Jesper Nilsson -- [email protected]

2007-12-12 13:47:17

by Jesper Nilsson

Subject: Re: [PATCH 00/47] CRIS patches for CRISv32 EtraxFS and ARTPEC-3

On Wed, Dec 12, 2007 at 02:28:42PM +0100, Adrian Bunk wrote:
> On Wed, Dec 12, 2007 at 02:52:12AM -0800, Andrew Morton wrote:
> > On Thu, 29 Nov 2007 17:02:22 +0100 Jesper Nilsson <[email protected]> wrote:
> > > The changes are also available in the export2 branch at
> > >
> > > git://http://www.jni.nu/axis.git
> >
> > I don't think there's much point in me merging these. Please ask Linus to
> > pull that tree once the 2.6.25 merge window opens.
>
> This sounds reasonable for the arch/cris/ and include/asm-cris/ parts,
> but shouldn't the rest go through the maintainers?

That would just be the crisv32 serial driver. I'll send an reworked version
of that patch later on, but it won't be useful until the rest is merged.

> cu
> Adrian

/^JN - Jesper Nilsson
--
Jesper Nilsson -- [email protected]

2007-12-12 17:05:07

by Jesper Nilsson

Subject: Re: [PATCH 44/47] Minor fixes for CRISv32 io.h

On Wed, Dec 12, 2007 at 03:29:39AM -0800, Andrew Morton wrote:
> On Mon, 3 Dec 2007 11:16:25 +0100 Jesper Nilsson <[email protected]> wrote:
> > struct crisv32_ioport
> > {
> > - unsigned long* oe;
> > - unsigned long* data;
> > - unsigned long* data_in;
> > + volatile unsigned long *oe;
> > + volatile unsigned long *data;
> > + volatile unsigned long *data_in;
> > unsigned int pin_count;
> > + spinlock_t lock;
> > };
>
> tabs.

Will fix.

> > static inline void crisv32_io_set(struct crisv32_iopin* iopin,
> > int val)
> > {
> > + long flags;
> > + spin_lock_irqsave(&iopin->port->lock, flags);
> > +
> > if (val)
> > *iopin->port->data |= iopin->bit;
> > else
> > *iopin->port->data &= ~iopin->bit;
> > +
> > + spin_unlock_irqrestore(&iopin->port->lock, flags);
> > }
> >
> > static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
> > enum crisv32_io_dir dir)
> > {
> > + long flags;
> > + spin_lock_irqsave(&iopin->port->lock, flags);
> > +
> > if (dir == crisv32_io_dir_in)
> > *iopin->port->oe &= ~iopin->bit;
> > else
> > *iopin->port->oe |= iopin->bit;
> > +
> > + spin_unlock_irqrestore(&iopin->port->lock, flags);
> > }
>
> These surely are far too large to be inlined.

Actually not, since the CRISv32 is UP, these should be ok to inline,
and since we most often call them with a constant argument,
the compiler is free to optimize away the if statement...

> > +#define LED_NETWORK_GRP0_SET(x) \
> > + do { \
> > + LED_NETWORK_GRP0_SET_G((x) & LED_GREEN); \
> > + LED_NETWORK_GRP0_SET_R((x) & LED_RED); \
> > } while (0)
> > +#else
> > +#define LED_NETWORK_GRP0_SET(x) while (0) {}
> > +#endif
> > +
> > +#define LED_NETWORK_GRP0_SET_G(x) \
> > + crisv32_io_set(&crisv32_led_net0_green, !(x));
> > +
> > +#define LED_NETWORK_GRP0_SET_R(x) \
> > + crisv32_io_set(&crisv32_led_net0_red, !(x));
> > +
> > +#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
> > +#define LED_NETWORK_GRP1_SET(x) \
> > + do { \
> > + LED_NETWORK_GRP1_SET_G((x) & LED_GREEN); \
> > + LED_NETWORK_GRP1_SET_R((x) & LED_RED); \
> > + } while (0)
> > +#else
> > +#define LED_NETWORK_GRP1_SET(x) while (0) {}
> > +#endif
> > +
> > +#define LED_NETWORK_GRP1_SET_G(x) \
> > + crisv32_io_set(&crisv32_led_net1_green, !(x));
> > +
> > +#define LED_NETWORK_GRP1_SET_R(x) \
> > + crisv32_io_set(&crisv32_led_net1_red, !(x));
> > +
> > #define LED_ACTIVE_SET(x) \
> > do { \
> > LED_ACTIVE_SET_G((x) & LED_GREEN); \
> > LED_ACTIVE_SET_R((x) & LED_RED); \
> > } while (0)
> >
>
> PLease generally prefer (lower-case) inlined functions over macros. They
> are cleaner, clearer, safer and have better typechecking.

Yes, you are right, I'll have to check where this is used, but hopefully
I can pare this down to a few inlines instead.

> Several of the above macros reference their argument more than once and
> hence cannot be used as, for example,
>
> LED_ACTIVE_SET(foo++);

Also true, although the argument should never be such a statement,
it is still bad form.

Thanks again for commenting, it is enormously helpful!

/^JN - Jesper Nilsson
--
Jesper Nilsson -- [email protected]

2007-12-06 12:41:56

by Jesper Nilsson

Subject: [PATCH 01/47] Rearrange Kconfigs for CRIS v10 and v32 to allow compilation without warnings.

- Remove some unneeded configs and add some new ones.
- Merge common config items to common file instead of duplicating them.
- Pull in standard Kconfig.preempt.
- Remove some unneeded Kconfigs for subsystems not (yet) available on CRIS
(md, scsi, ieee1394, i2o, isdn, telephony, media, pcmcia, pci)
- Rename CRISv32 config items which had different types from CRISv10.
(ETRAX_LED2G, ETRAX_LED2R, ETRAX_LED3G, ETRAX_LED3R, ETRAX_I2C_DATA_PORT,
ETRAX_I2C_CLK_PORT)

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/Kconfig | 490 +++++++++++++++++++++++---
arch/cris/arch-v10/Kconfig | 71 +----
arch/cris/arch-v10/drivers/Kconfig | 158 +--------
arch/cris/arch-v32/Kconfig | 309 ++++-------------
arch/cris/arch-v32/drivers/Kconfig | 697 +++++++++++++++++++++++++-----------
5 files changed, 1006 insertions(+), 719 deletions(-)

diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 222da15..0e9926d 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -13,10 +13,6 @@ config ZONE_DMA
bool
default y

-config NO_DMA
- bool
- default y
-
config RWSEM_GENERIC_SPINLOCK
bool
default y
@@ -24,6 +20,10 @@ config RWSEM_GENERIC_SPINLOCK
config RWSEM_XCHGADD_ALGORITHM
bool

+config GENERIC_IOMAP
+ bool
+ default y
+
config ARCH_HAS_ILOG2_U32
bool
default n
@@ -44,13 +44,16 @@ config GENERIC_CALIBRATE_DELAY
bool
default y

-config IRQ_PER_CPU
- bool
- default y
-
config NO_IOPORT
def_bool y

+config NO_IOMEM
+ def_bool y
+
+config FORCE_MAX_ZONEORDER
+ int
+ default 6
+
config CRIS
bool
default y
@@ -93,17 +96,15 @@ config ETRAX_FAST_TIMER
timers).
This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled.

-config PREEMPT
- bool "Preemptible Kernel"
+config ETRAX_KMALLOCED_MODULES
+ bool "Enable module allocation with kmalloc"
help
- This option reduces the latency of the kernel when reacting to
- real-time or interactive events by allowing a low priority process to
- be preempted even if it is in kernel mode executing a system call.
- This allows applications to run more reliably even when the system is
- under load.
+ Enable module allocation with kmalloc instead of vmalloc.

- Say Y here if you are building a kernel for a desktop, embedded
- or real-time system. Say N if you are unsure.
+config OOM_REBOOT
+ bool "Enable reboot at out of memory"
+
+source "kernel/Kconfig.preempt"

source mm/Kconfig

@@ -130,26 +131,127 @@ config SVINTO_SIM
help
Support the xsim ETRAX Simulator.

+config ETRAXFS
+ bool "ETRAX-FS-V32"
+ help
+ Support CRIS V32.
+
+config CRIS_MACH_ARTPEC3
+ bool "ARTPEC-3"
+ help
+ Support Axis ARTPEC-3.
+
endchoice

+config ETRAX_VCS_SIM
+ bool "VCS Simulator"
+ help
+ Setup hardware to be run in the VCS simulator.
+
config ETRAX_ARCH_V10
bool
default y if ETRAX100LX || ETRAX100LX_V2
default n if !(ETRAX100LX || ETRAX100LX_V2)

+config ETRAX_ARCH_V32
+ bool
+ default y if (ETRAXFS || CRIS_MACH_ARTPEC3)
+ default n if !(ETRAXFS || CRIS_MACH_ARTPEC3)
+
config ETRAX_DRAM_SIZE
int "DRAM size (dec, in MB)"
default "8"
help
Size of DRAM (decimal in MB) typically 2, 8 or 16.

+config ETRAX_VMEM_SIZE
+ int "Video memory size (dec, in MB)"
+ depends on ETRAX_ARCH_V32 && !ETRAXFS
+ default 8 if !ETRAXFS
+ help
+ Size of Video accessible memory (decimal, in MB).
+
config ETRAX_FLASH_BUSWIDTH
- int "Buswidth of flash in bytes"
+ int "Buswidth of NOR flash in bytes"
default "2"
help
- Width in bytes of the Flash bus (1, 2 or 4). Is usually 2.
+ Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2.
+
+config ETRAX_NANDFLASH_BUSWIDTH
+ int "Buswidth of NAND flash in bytes"
+ default "1"
+ help
+ Width in bytes of the NAND flash (1 or 2).
+
+config ETRAX_FLASH1_SIZE
+ int "FLASH1 size (dec, in MB. 0 = Unknown)"
+ default "0"
+
+choice
+ prompt "Product debug-port"
+ default ETRAX_DEBUG_PORT0
+
+config ETRAX_DEBUG_PORT0
+ bool "Serial-0"
+ help
+ Choose a serial port for the ETRAX debug console. Default to
+ port 0.
+
+config ETRAX_DEBUG_PORT1
+ bool "Serial-1"
+ help
+ Use serial port 1 for the console.
+
+config ETRAX_DEBUG_PORT2
+ bool "Serial-2"
+ help
+ Use serial port 2 for the console.
+
+config ETRAX_DEBUG_PORT3
+ bool "Serial-3"
+ help
+ Use serial port 3 for the console.
+
+config ETRAX_DEBUG_PORT_NULL
+ bool "disabled"
+ help
+ Disable serial-port debugging.
+
+endchoice
+
+choice
+ prompt "Kernel GDB port"
+ depends on ETRAX_KGDB
+ default ETRAX_KGDB_PORT0
+ help
+ Choose a serial port for kernel debugging. NOTE: This port should
+ not be enabled under Drivers for built-in interfaces (as it has its
+ own initialization code) and should not be the same as the debug port.
+
+config ETRAX_KGDB_PORT0
+ bool "Serial-0"
+ help
+ Use serial port 0 for kernel debugging.
+
+config ETRAX_KGDB_PORT1
+ bool "Serial-1"
+ help
+ Use serial port 1 for kernel debugging.
+
+config ETRAX_KGDB_PORT2
+ bool "Serial-2"
+ help
+ Use serial port 2 for kernel debugging.
+
+config ETRAX_KGDB_PORT3
+ bool "Serial-3"
+ help
+ Use serial port 3 for kernel debugging.
+
+endchoice

source arch/cris/arch-v10/Kconfig
+source arch/cris/arch-v32/Kconfig

endmenu

@@ -157,8 +259,331 @@ source "net/Kconfig"

# bring in ETRAX built-in drivers
menu "Drivers for built-in interfaces"
-# arch/cris/arch is a symlink to correct arch (arch-v10 or arch-v32)
-source arch/cris/arch/drivers/Kconfig
+source arch/cris/arch-v10/drivers/Kconfig
+source arch/cris/arch-v32/drivers/Kconfig
+
+choice
+ prompt "RTC chip"
+ depends on ETRAX_RTC
+ default ETRAX_PCF8563 if ETRAX_ARCH_V32
+ default ETRAX_DS1302 if ETRAX_ARCH_V10
+
+config ETRAX_DS1302
+ depends on ETRAX_ARCH_V10
+ bool "DS1302"
+ help
+ Enables the driver for the DS1302 Real-Time Clock battery-backed
+ chip on some products.
+
+config ETRAX_PCF8563
+ bool "PCF8563"
+ help
+ Enables the driver for the PCF8563 Real-Time Clock battery-backed
+ chip on some products.
+
+endchoice
+
+choice
+ prompt "Network LED behavior"
+ depends on ETRAX_ETHERNET
+ default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+
+config ETRAX_NETWORK_LED_ON_WHEN_LINK
+ bool "LED_on_when_link"
+ help
+ Selecting LED_on_when_link will light the LED when there is a
+ connection and will flash off when there is activity.
+
+ Selecting LED_on_when_activity will light the LED only when
+ there is activity.
+
+ This setting will also affect the behaviour of other activity LEDs
+ e.g. Bluetooth.
+
+config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+ bool "LED_on_when_activity"
+ help
+ Selecting LED_on_when_link will light the LED when there is a
+ connection and will flash off when there is activity.
+
+ Selecting LED_on_when_activity will light the LED only when
+ there is activity.
+
+ This setting will also affect the behaviour of other activity LEDs
+ e.g. Bluetooth.
+
+endchoice
+
+choice
+ prompt "Ser0 DMA out channel"
+ depends on ETRAX_SERIAL_PORT0
+ default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10
+
+config ETRAX_SERIAL_PORT0_NO_DMA_OUT
+ bool "Ser0 uses no DMA for output"
+ help
+ Do not use DMA for ser0 output.
+
+config ETRAX_SERIAL_PORT0_DMA6_OUT
+ bool "Ser0 uses DMA6 for output"
+ depends on ETRAXFS
+ help
+ Enables the DMA6 output channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT0_DMA0_OUT
+ bool "Ser0 uses DMA0 for output"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA0 output channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser0 DMA in channel "
+ depends on ETRAX_SERIAL_PORT0
+ default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser0.
+
+config ETRAX_SERIAL_PORT0_NO_DMA_IN
+ bool "Ser0 uses no DMA for input"
+ help
+ Do not use DMA for ser0 input.
+
+config ETRAX_SERIAL_PORT0_DMA7_IN
+ bool "Ser0 uses DMA7 for input"
+ depends on ETRAXFS
+ help
+ Enables the DMA7 input channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT0_DMA1_IN
+ bool "Ser0 uses DMA1 for input"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA1 input channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiveing data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser1 DMA in channel "
+ depends on ETRAX_SERIAL_PORT1
+ default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser1.
+
+config ETRAX_SERIAL_PORT1_NO_DMA_IN
+ bool "Ser1 uses no DMA for input"
+ help
+ Do not use DMA for ser1 input.
+
+config ETRAX_SERIAL_PORT1_DMA5_IN
+ bool "Ser1 uses DMA5 for input"
+ depends on ETRAX_ARCH_V32
+ help
+ Enables the DMA5 input channel for ser1 (ttyS1).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want this on, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT1_DMA9_IN
+ depends on ETRAX_ARCH_V10
+ bool "Ser1 uses DMA9 for input"
+
+endchoice
+
+
+choice
+ prompt "Ser1 DMA out channel"
+ depends on ETRAX_SERIAL_PORT1
+ default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser1.
+
+config ETRAX_SERIAL_PORT1_NO_DMA_OUT
+ bool "Ser1 uses no DMA for output"
+ help
+ Do not use DMA for ser1 output.
+
+config ETRAX_SERIAL_PORT1_DMA8_OUT
+ depends on ETRAX_ARCH_V10
+ bool "Ser1 uses DMA8 for output"
+
+config ETRAX_SERIAL_PORT1_DMA4_OUT
+ depends on ETRAX_ARCH_V32
+ bool "Ser1 uses DMA4 for output"
+ help
+ Enables the DMA4 output channel for ser1 (ttyS1).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want this on, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser2 DMA out channel"
+ depends on ETRAX_SERIAL_PORT2
+ default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10
+
+config ETRAX_SERIAL_PORT2_NO_DMA_OUT
+ bool "Ser2 uses no DMA for output"
+ help
+ Do not use DMA for ser2 output.
+
+config ETRAX_SERIAL_PORT2_DMA2_OUT
+ bool "Ser2 uses DMA2 for output"
+ depends on ETRAXFS || ETRAX_ARCH_V10
+ help
+ Enables the DMA2 output channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT2_DMA6_OUT
+ bool "Ser2 uses DMA6 for output"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA6 output channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser2 DMA in channel"
+ depends on ETRAX_SERIAL_PORT2
+ default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser2.
+
+config ETRAX_SERIAL_PORT2_NO_DMA_IN
+ bool "Ser2 uses no DMA for input"
+ help
+ Do not use DMA for ser2 input.
+
+config ETRAX_SERIAL_PORT2_DMA3_IN
+ bool "Ser2 uses DMA3 for input"
+ depends on ETRAXFS || ETRAX_ARCH_V10
+ help
+ Enables the DMA3 input channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT2_DMA7_IN
+ bool "Ser2 uses DMA7 for input"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA7 input channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiveing data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser3 DMA in channel"
+ depends on ETRAX_SERIAL_PORT3
+ default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser3.
+
+config ETRAX_SERIAL_PORT3_NO_DMA_IN
+ bool "Ser3 uses no DMA for input"
+ help
+ Do not use DMA for ser3 input.
+
+config ETRAX_SERIAL_PORT3_DMA5_IN
+ depends on ETRAX_ARCH_V10
+ bool "DMA 5"
+
+config ETRAX_SERIAL_PORT3_DMA9_IN
+ bool "Ser3 uses DMA9 for input"
+ depends on ETRAXFS
+ help
+ Enables the DMA9 input channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT3_DMA3_IN
+ bool "Ser3 uses DMA3 for input"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA3 input channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiveing data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser3 DMA out channel"
+ depends on ETRAX_SERIAL_PORT3
+ default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10
+
+config ETRAX_SERIAL_PORT3_NO_DMA_OUT
+ bool "Ser3 uses no DMA for output"
+ help
+ Do not use DMA for ser3 output.
+
+config ETRAX_SERIAL_PORT3_DMA4_OUT
+ depends on ETRAX_ARCH_V10
+ bool "DMA 4"
+
+config ETRAX_SERIAL_PORT3_DMA8_OUT
+ bool "Ser3 uses DMA8 for output"
+ depends on ETRAXFS
+ help
+ Enables the DMA8 output channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT3_DMA2_OUT
+ bool "Ser3 uses DMA2 for output"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA2 output channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice

endmenu

@@ -173,22 +598,10 @@ source "drivers/pnp/Kconfig"

source "drivers/block/Kconfig"

-source "drivers/md/Kconfig"
-
source "drivers/ide/Kconfig"

-source "drivers/scsi/Kconfig"
-
-source "drivers/ieee1394/Kconfig"
-
-source "drivers/message/i2o/Kconfig"
-
source "drivers/net/Kconfig"

-source "drivers/isdn/Kconfig"
-
-source "drivers/telephony/Kconfig"
-
source "drivers/i2c/Kconfig"

source "drivers/rtc/Kconfig"
@@ -200,21 +613,10 @@ source "drivers/input/Kconfig"

source "drivers/char/Kconfig"

-#source drivers/misc/Config.in
-source "drivers/media/Kconfig"
-
source "fs/Kconfig"

-source "sound/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-source "drivers/pci/Kconfig"
-
source "drivers/usb/Kconfig"

-source "kernel/Kconfig.instrumentation"
-
source "arch/cris/Kconfig.debug"

source "security/Kconfig"
diff --git a/arch/cris/arch-v10/Kconfig b/arch/cris/arch-v10/Kconfig
index f1ce6f6..adc164e 100644
--- a/arch/cris/arch-v10/Kconfig
+++ b/arch/cris/arch-v10/Kconfig
@@ -1,3 +1,7 @@
+if ETRAX_ARCH_V10
+
+menu "CRIS v10 options"
+
# ETRAX 100LX v1 has a MMU "feature" requiring a low mapping
config CRIS_LOW_MAP
bool
@@ -226,69 +230,6 @@ config ETRAX_LED12R
For products with only one or two controllable LEDs,
set this to same as CONFIG_ETRAX_LED1G (normally 2).

-choice
- prompt "Product debug-port"
- depends on ETRAX_ARCH_V10
- default ETRAX_DEBUG_PORT0
-
-config ETRAX_DEBUG_PORT0
- bool "Serial-0"
- help
- Choose a serial port for the ETRAX debug console. Default to
- port 0.
-
-config ETRAX_DEBUG_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for the console.
-
-config ETRAX_DEBUG_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for the console.
-
-config ETRAX_DEBUG_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for the console.
-
-config ETRAX_DEBUG_PORT_NULL
- bool "disabled"
- help
- Disable serial-port debugging.
-
-endchoice
-
-choice
- prompt "Kernel GDB port"
- depends on ETRAX_KGDB
- default ETRAX_KGDB_PORT0
- help
- Choose a serial port for kernel debugging. NOTE: This port should
- not be enabled under Drivers for built-in interfaces (as it has its
- own initialization code) and should not be the same as the debug port.
-
-config ETRAX_KGDB_PORT0
- bool "Serial-0"
- help
- Use serial port 0 for kernel debugging.
-
-config ETRAX_KGDB_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for kernel debugging.
-
-config ETRAX_KGDB_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for kernel debugging.
-
-config ETRAX_KGDB_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for kernel debugging.
-
-endchoice

choice
prompt "Product rescue-port"
@@ -451,3 +392,7 @@ config ETRAX_POWERBUTTON_BIT
default "25"
help
Configure where power button is connected.
+
+endmenu
+
+endif
diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig
index e3c0f29..10e9b50 100644
--- a/arch/cris/arch-v10/drivers/Kconfig
+++ b/arch/cris/arch-v10/drivers/Kconfig
@@ -1,3 +1,5 @@
+if ETRAX_ARCH_V10
+
config ETRAX_ETHERNET
bool "Ethernet support"
depends on ETRAX_ARCH_V10
@@ -7,37 +9,6 @@ config ETRAX_ETHERNET
This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
controller.

-choice
- prompt "Network LED behavior"
- depends on ETRAX_ETHERNET
- default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
-
-config ETRAX_NETWORK_LED_ON_WHEN_LINK
- bool "LED_on_when_link"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
- bool "LED_on_when_activity"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-endchoice
-
config ETRAX_SERIAL
bool "Serial-port support"
depends on ETRAX_ARCH_V10
@@ -82,32 +53,6 @@ config ETRAX_SERIAL_PORT0
the same DMA channels.

choice
- prompt "Ser0 DMA out assignment"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_DMA6_OUT
-
-config ETRAX_SERIAL_PORT0_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT0_DMA6_OUT
- bool "DMA 6"
-
-endchoice
-
-choice
- prompt "Ser0 DMA in assignment"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_DMA7_IN
-
-config ETRAX_SERIAL_PORT0_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT0_DMA7_IN
- bool "DMA 7"
-
-endchoice
-
-choice
prompt "Ser0 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT0
default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
@@ -196,32 +141,6 @@ config ETRAX_SERIAL_PORT1
Enables the ETRAX 100 serial driver for ser1 (ttyS1).

choice
- prompt "Ser1 DMA out assignment"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_DMA8_OUT
-
-config ETRAX_SERIAL_PORT1_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT1_DMA8_OUT
- bool "DMA 8"
-
-endchoice
-
-choice
- prompt "Ser1 DMA in assignment"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_DMA9_IN
-
-config ETRAX_SERIAL_PORT1_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT1_DMA9_IN
- bool "DMA 9"
-
-endchoice
-
-choice
prompt "Ser1 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT1
default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
@@ -313,32 +232,6 @@ config ETRAX_SERIAL_PORT2
Enables the ETRAX 100 serial driver for ser2 (ttyS2).

choice
- prompt "Ser2 DMA out assignment"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_DMA2_OUT
-
-config ETRAX_SERIAL_PORT2_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT2_DMA2_OUT
- bool "DMA 2"
-
-endchoice
-
-choice
- prompt "Ser2 DMA in assignment"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_DMA3_IN
-
-config ETRAX_SERIAL_PORT2_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT2_DMA3_IN
- bool "DMA 3"
-
-endchoice
-
-choice
prompt "Ser2 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT2
default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
@@ -427,32 +320,6 @@ config ETRAX_SERIAL_PORT3
Enables the ETRAX 100 serial driver for ser3 (ttyS3).

choice
- prompt "Ser3 DMA out assignment"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_DMA4_OUT
-
-config ETRAX_SERIAL_PORT3_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT3_DMA4_OUT
- bool "DMA 4"
-
-endchoice
-
-choice
- prompt "Ser3 DMA in assignment"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_DMA5_IN
-
-config ETRAX_SERIAL_PORT3_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT3_DMA5_IN
- bool "DMA 5"
-
-endchoice
-
-choice
prompt "Ser3 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT3
default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
@@ -741,25 +608,6 @@ config ETRAX_RTC
normal time reading should be done using libc function time and
friends.

-choice
- prompt "RTC chip"
- depends on ETRAX_RTC
- default ETRAX_DS1302
-
-config ETRAX_DS1302
- bool "DS1302"
- help
- Enables the driver for the DS1302 Real-Time Clock battery-backed
- chip on some products.
-
-config ETRAX_PCF8563
- bool "PCF8563"
- help
- Enables the driver for the PCF8563 Real-Time Clock battery-backed
- chip on some products.
-
-endchoice
-
config ETRAX_DS1302_RST_ON_GENERIC_PORT
bool "DS1302 RST on Generic Port"
depends on ETRAX_DS1302
@@ -806,3 +654,5 @@ config ETRAX_DS1302_TRICKLE_CHARGE
1 = 2kohm, 2 = 4kohm, 3 = 4kohm
4 = 1 diode, 8 = 2 diodes
Allowed values are (increasing current): 0, 11, 10, 9, 7, 6, 5
+
+endif
diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig
index 4f79d8e..70d8dc9 100644
--- a/arch/cris/arch-v32/Kconfig
+++ b/arch/cris/arch-v32/Kconfig
@@ -1,25 +1,73 @@
+if ETRAX_ARCH_V32
+
+source arch/cris/arch-v32/mach-fs/Kconfig
+source arch/cris/arch-v32/mach-a3/Kconfig
+
+source drivers/cpufreq/Kconfig
+
config ETRAX_DRAM_VIRTUAL_BASE
hex
depends on ETRAX_ARCH_V32
default "c0000000"

-config ETRAX_LED1G
- string "First green LED bit"
+choice
+ prompt "Nbr of Ethernet LED groups"
depends on ETRAX_ARCH_V32
+ default ETRAX_NBR_LED_GRP_ONE
+ help
+ Select how many Ethernet LED groups that can be used. Usually one per Ethernet
+ interface is a good choice.
+
+config ETRAX_NBR_LED_GRP_ZERO
+ bool "Use zero LED groups"
+ help
+ Select this if you do not want any Ethernet LEDs.
+
+config ETRAX_NBR_LED_GRP_ONE
+ bool "Use one LED group"
+ help
+ Select this if you want one Ethernet LED group. This LED group
+ can be used for one or more Ethernet interfaces. However, it is
+ recomended that each Ethernet interface use a dedicated LED group.
+
+config ETRAX_NBR_LED_GRP_TWO
+ bool "Use two LED groups"
+ help
+ Select this if you want two Ethernet LED groups. This is the
+ best choice if you have more than one Ethernet interface and
+ would like to have separate LEDs for the interfaces.
+
+endchoice
+
+config ETRAX_LED_G_NET0
+ string "Ethernet LED group 0 green LED bit"
+ depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA3"
help
- Bit to use for the first green LED (network LED).
- Most Axis products use bit A3 here.
+ Bit to use for the green LED in Ethernet LED group 0.

-config ETRAX_LED1R
- string "First red LED bit"
- depends on ETRAX_ARCH_V32
+config ETRAX_LED_R_NET0
+ string "Ethernet LED group 0 red LED bit"
+ depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA4"
help
- Bit to use for the first red LED (network LED).
- Most Axis products use bit A4 here.
+ Bit to use for the red LED in Ethernet LED group 0.
+
+config ETRAX_LED_G_NET1
+ string "Ethernet group 1 green LED bit"
+ depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
+ default ""
+ help
+ Bit to use for the green LED in Ethernet LED group 1.

-config ETRAX_LED2G
+config ETRAX_LED_R_NET1
+ string "Ethernet group 1 red LED bit"
+ depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
+ default ""
+ help
+ Bit to use for the red LED in Ethernet LED group 1.
+
+config ETRAX_V32_LED2G
string "Second green LED bit"
depends on ETRAX_ARCH_V32
default "PA5"
@@ -27,7 +75,7 @@ config ETRAX_LED2G
Bit to use for the first green LED (status LED).
Most Axis products use bit A5 here.

-config ETRAX_LED2R
+config ETRAX_V32_LED2R
string "Second red LED bit"
depends on ETRAX_ARCH_V32
default "PA6"
@@ -35,7 +83,7 @@ config ETRAX_LED2R
Bit to use for the first red LED (network LED).
Most Axis products use bit A6 here.

-config ETRAX_LED3G
+config ETRAX_V32_LED3G
string "Third green LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
@@ -43,7 +91,7 @@ config ETRAX_LED3G
Bit to use for the first green LED (drive/power LED).
Most Axis products use bit A7 here.

-config ETRAX_LED3R
+config ETRAX_V32_LED3R
string "Third red LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
@@ -52,39 +100,6 @@ config ETRAX_LED3R
Most Axis products use bit A7 here.

choice
- prompt "Product debug-port"
- depends on ETRAX_ARCH_V32
- default ETRAX_DEBUG_PORT0
-
-config ETRAX_DEBUG_PORT0
- bool "Serial-0"
- help
- Choose a serial port for the ETRAX debug console. Default to
- port 0.
-
-config ETRAX_DEBUG_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for the console.
-
-config ETRAX_DEBUG_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for the console.
-
-config ETRAX_DEBUG_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for the console.
-
-config ETRAX_DEBUG_PORT_NULL
- bool "disabled"
- help
- Disable serial-port debugging.
-
-endchoice
-
-choice
prompt "Kernel GDB port"
depends on ETRAX_KGDB
default ETRAX_KGDB_PORT0
@@ -93,204 +108,12 @@ choice
not be enabled under Drivers for built-in interfaces (as it has its
own initialization code) and should not be the same as the debug port.

-config ETRAX_KGDB_PORT0
- bool "Serial-0"
+config ETRAX_KGDB_PORT4
+ bool "Serial-4"
+ depends on ETRAX_SERIAL_PORTS = 5
help
- Use serial port 0 for kernel debugging.
-
-config ETRAX_KGDB_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for kernel debugging.
-
-config ETRAX_KGDB_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for kernel debugging.
-
-config ETRAX_KGDB_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for kernel debugging.
+ Use serial port 4 for kernel debugging.

endchoice

-config ETRAX_MEM_GRP1_CONFIG
- hex "MEM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "4044a"
- help
- Waitstates for flash. The default value is suitable for the
- standard flashes used in axis products (120 ns).
-
-config ETRAX_MEM_GRP2_CONFIG
- hex "MEM_GRP2_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for SRAM. 0 is a good choice for most Axis products.
-
-config ETRAX_MEM_GRP3_CONFIG
- hex "MEM_GRP3_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP0-3. 0 is a good choice for most Axis products.
- It may need to be changed if external devices such as extra
- register-mapped LEDs are used.
-
-config ETRAX_MEM_GRP4_CONFIG
- hex "MEM_GRP4_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP4-6. 0 is a good choice for most Axis products.
-
-config ETRAX_SDRAM_GRP0_CONFIG
- hex "SDRAM_GRP0_CONFIG"
- depends on ETRAX_ARCH_V32
- default "336"
- help
- SDRAM configuration for group 0. The value depends on the
- hardware configuration. The default value is suitable
- for 32 MB organized as two 16 bits chips (e.g. Axis
- part number 18550) connected as one 32 bit device (i.e. in
- the same group).
-
-config ETRAX_SDRAM_GRP1_CONFIG
- hex "SDRAM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM configuration for group 1. The default value is 0
- because group 1 is not used in the default configuration,
- described in the help for SDRAM_GRP0_CONFIG.
-
-config ETRAX_SDRAM_TIMING
- hex "SDRAM_TIMING"
- depends on ETRAX_ARCH_V32
- default "104a"
- help
- SDRAM timing parameters. The default value is ok for
- most hardwares but large SDRAMs may require a faster
- refresh (a.k.a 8K refresh). The default value implies
- 100MHz clock and SDR mode.
-
-config ETRAX_SDRAM_COMMAND
- hex "SDRAM_COMMAND"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM command. Should be 0 unless you really know what
- you are doing (may be != 0 for unusual address line
- mappings such as in a MCM)..
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- depends on ETRAX_ARCH_V32
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- depends on ETRAX_ARCH_V32
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PD_OE
- hex "GIO_PD_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port D bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PD_OUT
- hex "GIO_PD_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port D bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PE_OE
- hex "GIO_PE_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port E bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PE_OUT
- hex "GIO_PE_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port E bits. Most
- products should use 00000 here.
+endif
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index 9bccb5e..471c203 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -1,65 +1,105 @@
+if ETRAX_ARCH_V32
+
config ETRAX_ETHERNET
bool "Ethernet support"
depends on ETRAX_ARCH_V32
select NET_ETHERNET
+ select MII
help
This option enables the ETRAX FS built-in 10/100Mbit Ethernet
controller.

-config ETRAX_ETHERNET_HW_CSUM
- bool "Hardware accelerated ethernet checksum and scatter/gather"
+config ETRAX_NO_PHY
+ bool "PHY not present"
depends on ETRAX_ETHERNET
- depends on ETRAX_STREAMCOPROC
- default y
+ default N
help
- Hardware acceleration of checksumming and scatter/gather
+ This option disables all MDIO communication with an ethernet
+ transceiver connected to the MII interface. This option shall
+ typically be enabled if the MII interface is connected to a
+ switch. This option should normally be disabled. If enabled,
+ speed and duplex will be locked to 100 Mbit and full duplex.

config ETRAX_ETHERNET_IFACE0
depends on ETRAX_ETHERNET
bool "Enable network interface 0"

config ETRAX_ETHERNET_IFACE1
- depends on ETRAX_ETHERNET
+ depends on (ETRAX_ETHERNET && ETRAXFS)
bool "Enable network interface 1 (uses DMA6 and DMA7)"

+config ETRAX_ETHERNET_GBIT
+ depends on (ETRAX_ETHERNET && CRIS_MACH_ARTPEC3)
+ bool "Enable gigabit Ethernet support"
+
choice
- prompt "Network LED behavior"
- depends on ETRAX_ETHERNET
- default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+ prompt "Eth0 led group"
+ depends on ETRAX_ETHERNET_IFACE0
+ default ETRAX_ETH0_USE_LEDGRP0

-config ETRAX_NETWORK_LED_ON_WHEN_LINK
- bool "LED_on_when_link"
+config ETRAX_ETH0_USE_LEDGRP0
+ bool "Use LED grp 0"
+ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
+ Use LED grp 0 for eth0

- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
+config ETRAX_ETH0_USE_LEDGRP1
+ bool "Use LED grp 1"
+ depends on ETRAX_NBR_LED_GRP_TWO
+ help
+ Use LED grp 1 for eth0

-config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
- bool "LED_on_when_activity"
+config ETRAX_ETH0_USE_LEDGRPNULL
+ bool "Use no LEDs for eth0"
help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
+ Use no LEDs for eth0
+endchoice
+
+choice
+ prompt "Eth1 led group"
+ depends on ETRAX_ETHERNET_IFACE1
+ default ETRAX_ETH1_USE_LEDGRP1

- Selecting LED_on_when_activity will light the LED only when
- there is activity.
+config ETRAX_ETH1_USE_LEDGRP0
+ bool "Use LED grp 0"
+ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
+ help
+ Use LED grp 0 for eth1

- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
+config ETRAX_ETH1_USE_LEDGRP1
+ bool "Use LED grp 1"
+ depends on ETRAX_NBR_LED_GRP_TWO
+ help
+ Use LED grp 1 for eth1

+config ETRAX_ETH1_USE_LEDGRPNULL
+ bool "Use no LEDs for eth1"
+ help
+ Use no LEDs for eth1
endchoice

config ETRAXFS_SERIAL
bool "Serial-port support"
depends on ETRAX_ARCH_V32
+ select SERIAL_CORE
+ select SERIAL_CORE_CONSOLE
help
Enables the ETRAX FS serial driver for ser0 (ttyS0)
You probably want this enabled.

+config ETRAX_RS485
+ bool "RS-485 support"
+ depends on ETRAXFS_SERIAL
+ help
+ Enables support for RS-485 serial communication.
+
+config ETRAX_RS485_DISABLE_RECEIVER
+ bool "Disable serial receiver"
+ depends on ETRAX_RS485
+ help
+ It is necessary to disable the serial receiver to avoid serial
+ loopback. Not all products are able to do this in software only.
+
config ETRAX_SERIAL_PORT0
bool "Serial port 0 enabled"
depends on ETRAXFS_SERIAL
@@ -70,50 +110,28 @@ config ETRAX_SERIAL_PORT0
ser0 can use dma4 or dma6 for output and dma5 or dma7 for input.

choice
- prompt "Ser0 DMA in channel "
+ prompt "Ser0 default port type "
depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_NO_DMA_IN
- help
- What DMA channel to use for ser0.
-
-
-config ETRAX_SERIAL_PORT0_NO_DMA_IN
- bool "Ser0 uses no DMA for input"
+ default ETRAX_SERIAL_PORT0_TYPE_232
help
- Do not use DMA for ser0 input.
+ Type of serial port.

-config ETRAX_SERIAL_PORT0_DMA7_IN
- bool "Ser0 uses DMA7 for input"
- depends on ETRAX_SERIAL_PORT0
+config ETRAX_SERIAL_PORT0_TYPE_232
+ bool "Ser0 is a RS-232 port"
help
- Enables the DMA7 input channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
+ Configure serial port 0 to be a RS-232 port.

-choice
- prompt "Ser0 DMA out channel"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_NO_DMA_OUT
-
-config ETRAX_SERIAL_PORT0_NO_DMA_OUT
- bool "Ser0 uses no DMA for output"
+config ETRAX_SERIAL_PORT0_TYPE_485HD
+ bool "Ser0 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser0 output.
+ Configure serial port 0 to be a half duplex (two wires) RS-485 port.

-config ETRAX_SERIAL_PORT0_DMA6_OUT
- bool "Ser0 uses DMA6 for output"
- depends on ETRAX_SERIAL_PORT0
+config ETRAX_SERIAL_PORT0_TYPE_485FD
+ bool "Ser0 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Enables the DMA6 output channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
+ Configure serial port 0 to be a full duplex (four wires) RS-485 port.
endchoice

config ETRAX_SER0_DTR_BIT
@@ -139,52 +157,28 @@ config ETRAX_SERIAL_PORT1
Enables the ETRAX FS serial driver for ser1 (ttyS1).

choice
- prompt "Ser1 DMA in channel "
+ prompt "Ser1 default port type"
depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_IN
+ default ETRAX_SERIAL_PORT1_TYPE_232
help
- What DMA channel to use for ser1.
-
+ Type of serial port.

-config ETRAX_SERIAL_PORT1_NO_DMA_IN
- bool "Ser1 uses no DMA for input"
+config ETRAX_SERIAL_PORT1_TYPE_232
+ bool "Ser1 is a RS-232 port"
help
- Do not use DMA for ser1 input.
+ Configure serial port 1 to be a RS-232 port.

-config ETRAX_SERIAL_PORT1_DMA5_IN
- bool "Ser1 uses DMA5 for input"
- depends on ETRAX_SERIAL_PORT1
- help
- Enables the DMA5 input channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser1 DMA out channel "
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_OUT
- help
- What DMA channel to use for ser1.
-
-config ETRAX_SERIAL_PORT1_NO_DMA_OUT
- bool "Ser1 uses no DMA for output"
+config ETRAX_SERIAL_PORT1_TYPE_485HD
+ bool "Ser1 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser1 output.
+ Configure serial port 1 to be a half duplex (two wires) RS-485 port.

-config ETRAX_SERIAL_PORT1_DMA4_OUT
- bool "Ser1 uses DMA4 for output"
- depends on ETRAX_SERIAL_PORT1
+config ETRAX_SERIAL_PORT1_TYPE_485FD
+ bool "Ser1 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Enables the DMA4 output channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
+ Configure serial port 1 to be a full duplex (four wires) RS-485 port.
endchoice

config ETRAX_SER1_DTR_BIT
@@ -210,52 +204,31 @@ config ETRAX_SERIAL_PORT2
Enables the ETRAX FS serial driver for ser2 (ttyS2).

choice
- prompt "Ser2 DMA in channel "
+ prompt "Ser2 default port type"
depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_IN
+ default ETRAX_SERIAL_PORT2_TYPE_232
help
- What DMA channel to use for ser2.
+ What DMA channel to use for ser2

-
-config ETRAX_SERIAL_PORT2_NO_DMA_IN
- bool "Ser2 uses no DMA for input"
+config ETRAX_SERIAL_PORT2_TYPE_232
+ bool "Ser2 is a RS-232 port"
help
- Do not use DMA for ser2 input.
-
-config ETRAX_SERIAL_PORT2_DMA3_IN
- bool "Ser2 uses DMA3 for input"
- depends on ETRAX_SERIAL_PORT2
- help
- Enables the DMA3 input channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser2 DMA out channel"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_OUT
+ Configure serial port 2 to be a RS-232 port.

-config ETRAX_SERIAL_PORT2_NO_DMA_OUT
- bool "Ser2 uses no DMA for output"
+config ETRAX_SERIAL_PORT2_TYPE_485HD
+ bool "Ser2 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser2 output.
+ Configure serial port 2 to be a half duplex (two wires) RS-485 port.

-config ETRAX_SERIAL_PORT2_DMA2_OUT
- bool "Ser2 uses DMA2 for output"
- depends on ETRAX_SERIAL_PORT2
+config ETRAX_SERIAL_PORT2_TYPE_485FD
+ bool "Ser2 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Enables the DMA2 output channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
+ Configure serial port 2 to be a full duplex (four wires) RS-485 port.
endchoice

+
config ETRAX_SER2_DTR_BIT
string "Ser 2 DTR bit (empty = not used)"
depends on ETRAX_SERIAL_PORT2
@@ -279,71 +252,121 @@ config ETRAX_SERIAL_PORT3
Enables the ETRAX FS serial driver for ser3 (ttyS3).

choice
- prompt "Ser3 DMA in channel "
+ prompt "Ser3 default port type"
depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_IN
+ default ETRAX_SERIAL_PORT3_TYPE_232
help
What DMA channel to use for ser3.

+config ETRAX_SERIAL_PORT3_TYPE_232
+ bool "Ser3 is a RS-232 port"
+ help
+ Configure serial port 3 to be a RS-232 port.
+
+config ETRAX_SERIAL_PORT3_TYPE_485HD
+ bool "Ser3 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
+ help
+ Configure serial port 3 to be a half duplex (two wires) RS-485 port.

-config ETRAX_SERIAL_PORT3_NO_DMA_IN
- bool "Ser3 uses no DMA for input"
+config ETRAX_SERIAL_PORT3_TYPE_485FD
+ bool "Ser3 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser3 input.
+ Configure serial port 3 to be a full duplex (four wires) RS-485 port.
+endchoice

-config ETRAX_SERIAL_PORT3_DMA9_IN
- bool "Ser3 uses DMA9 for input"
+config ETRAX_SER3_DTR_BIT
+ string "Ser 3 DTR bit (empty = not used)"
depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_RI_BIT
+ string "Ser 3 RI bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_DSR_BIT
+ string "Ser 3 DSR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_CD_BIT
+ string "Ser 3 CD bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SERIAL_PORT4
+ bool "Serial port 4 enabled"
+ depends on ETRAXFS_SERIAL && CRIS_MACH_ARTPEC3
help
- Enables the DMA9 input channel for ser3 (ttyS3).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
+ Enables the ETRAX FS serial driver for ser4 (ttyS4).
+
+choice
+ prompt "Ser4 default port type"
+ depends on ETRAX_SERIAL_PORT4
+ default ETRAX_SERIAL_PORT4_TYPE_232
+ help
+ What DMA channel to use for ser4.
+
+config ETRAX_SERIAL_PORT4_TYPE_232
+ bool "Ser4 is a RS-232 port"
+ help
+ Configure serial port 4 to be a RS-232 port.

+config ETRAX_SERIAL_PORT4_TYPE_485HD
+ bool "Ser4 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
+ help
+ Configure serial port 4 to be a half duplex (two wires) RS-485 port.
+
+config ETRAX_SERIAL_PORT4_TYPE_485FD
+ bool "Ser4 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
+ help
+ Configure serial port 4 to be a full duplex (four wires) RS-485 port.
endchoice

choice
- prompt "Ser3 DMA out channel"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_OUT
+ prompt "Ser4 DMA in channel "
+ depends on ETRAX_SERIAL_PORT4
+ default ETRAX_SERIAL_PORT4_NO_DMA_IN
+ help
+ What DMA channel to use for ser4.
+

-config ETRAX_SERIAL_PORT3_NO_DMA_OUT
- bool "Ser3 uses no DMA for output"
+config ETRAX_SERIAL_PORT4_NO_DMA_IN
+ bool "Ser4 uses no DMA for input"
help
- Do not use DMA for ser3 output.
+ Do not use DMA for ser4 input.

-config ETRAX_SERIAL_PORT3_DMA8_OUT
- bool "Ser3 uses DMA8 for output"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SERIAL_PORT4_DMA9_IN
+ bool "Ser4 uses DMA9 for input"
+ depends on ETRAX_SERIAL_PORT4
help
- Enables the DMA8 output channel for ser3 (ttyS3).
+ Enables the DMA9 input channel for ser4 (ttyS4).
If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
+ used when receiveing data.
Normally you want to use DMA, unless you use the DMA channel for
something else.

endchoice

-config ETRAX_SER3_DTR_BIT
- string "Ser 3 DTR bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SER4_DTR_BIT
+ string "Ser 4 DTR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4

-config ETRAX_SER3_RI_BIT
- string "Ser 3 RI bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SER4_RI_BIT
+ string "Ser 4 RI bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4

-config ETRAX_SER3_DSR_BIT
- string "Ser 3 DSR bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SER4_DSR_BIT
+ string "Ser 4 DSR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4

config ETRAX_SER3_CD_BIT
- string "Ser 3 CD bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+ string "Ser 4 CD bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4

config ETRAX_RS485
bool "RS-485 support"
- depends on ETRAX_SERIAL
+ depends on ETRAXFS_SERIAL
help
Enables support for RS-485 serial communication. For a primer on
RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>.
@@ -354,7 +377,6 @@ config ETRAX_RS485_DISABLE_RECEIVER
help
It is necessary to disable the serial receiver to avoid serial
loopback. Not all products are able to do this in software only.
- Axis 2400/2401 must disable receiver.

config ETRAX_AXISFLASHMAP
bool "Axis flash-map support"
@@ -362,6 +384,7 @@ config ETRAX_AXISFLASHMAP
select MTD
select MTD_CFI
select MTD_CFI_AMDSTD
+ select MTD_JEDECPROBE
select MTD_CHAR
select MTD_BLOCK
select MTD_PARTITIONS
@@ -392,7 +415,7 @@ config ETRAX_SYNCHRONOUS_SERIAL0_DMA

config ETRAX_SYNCHRONOUS_SERIAL_PORT1
bool "Synchronous serial port 1 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL
+ depends on ETRAX_SYNCHRONOUS_SERIAL && ETRAXFS
help
Enabled synchronous serial port 1.

@@ -403,6 +426,31 @@ config ETRAX_SYNCHRONOUS_SERIAL1_DMA
A synchronous serial port can run in manual or DMA mode.
Selecting this option will make it run in DMA mode.

+config ETRAX_AXISFLASHMAP
+ bool "Axis flash-map support"
+ depends on ETRAX_ARCH_V32
+ select MTD
+ select MTD_CFI
+ select MTD_CFI_AMDSTD
+ select MTD_JEDECPROBE
+ select MTD_CHAR
+ select MTD_BLOCK
+ select MTD_PARTITIONS
+ select MTD_CONCAT
+ select MTD_COMPLEX_MAPPINGS
+ help
+ This option enables MTD mapping of flash devices. Needed to use
+ flash memories. If unsure, say Y.
+
+config ETRAX_AXISFLASHMAP_MTD0WHOLE
+ bool "MTD0 is whole boot flash device"
+ depends on ETRAX_AXISFLASHMAP
+ default N
+ help
+ When this option is not set, mtd0 refers to the first partition
+ on the boot flash device. When set, mtd0 refers to the whole
+ device, with mtd1 referring to the first partition etc.
+
config ETRAX_PTABLE_SECTOR
int "Byte-offset of partition table sector"
depends on ETRAX_AXISFLASHMAP
@@ -423,19 +471,27 @@ config ETRAX_NANDFLASH
This option enables MTD mapping of NAND flash devices. Needed to use
NAND flash memories. If unsure, say Y.

+config ETRAX_NANDBOOT
+ bool "Boot from NAND flash"
+ depends on ETRAX_NANDFLASH
+ help
+ This options enables booting from NAND flash devices.
+ Say Y if your boot code, kernel and root file system is in
+ NAND flash. Say N if they are in NOR flash.
+
config ETRAX_I2C
bool "I2C driver"
depends on ETRAX_ARCH_V32
help
- This option enabled the I2C driver used by e.g. the RTC driver.
+ This option enables the I2C driver used by e.g. the RTC driver.

-config ETRAX_I2C_DATA_PORT
+config ETRAX_V32_I2C_DATA_PORT
string "I2C data pin"
depends on ETRAX_I2C
help
The pin to use for I2C data.

-config ETRAX_I2C_CLK_PORT
+config ETRAX_V32_I2C_CLK_PORT
string "I2C clock pin"
depends on ETRAX_I2C
help
@@ -443,22 +499,10 @@ config ETRAX_I2C_CLK_PORT

config ETRAX_RTC
bool "Real Time Clock support"
- depends on ETRAX_ARCH_V32
+ depends on ETRAX_ARCH_V32 && ETRAX_I2C
help
Enabled RTC support.

-choice
- prompt "RTC chip"
- depends on ETRAX_RTC
- default ETRAX_PCF8563
-
-config ETRAX_PCF8563
- bool "PCF8563"
- help
- Philips PCF8563 RTC
-
-endchoice
-
config ETRAX_GPIO
bool "GPIO support"
depends on ETRAX_ARCH_V32
@@ -474,33 +518,36 @@ config ETRAX_GPIO
Remember that you need to setup the port directions appropriately in
the General configuration.

-config ETRAX_PA_BUTTON_BITMASK
- hex "PA-buttons bitmask"
+config ETRAX_VIRTUAL_GPIO
+ bool "Virtual GPIO support"
depends on ETRAX_GPIO
- default "0x02"
help
- This is a bitmask (8 bits) with information about what bits on PA
- that are used for buttons.
- Most products has a so called TEST button on PA1, if that is true
- use 0x02 here.
- Use 00 if there are no buttons on PA.
- If the bitmask is <> 00 a button driver will be included in the gpio
- driver. ETRAX general I/O support must be enabled.
+ Enables the virtual Etrax general port device (major 120, minor 6).
+ It uses an I/O expander for the I2C-bus.
+
+config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
+ int "Virtual GPIO interrupt pin on PA pin"
+ range 0 7
+ depends on ETRAX_VIRTUAL_GPIO
+ help
+ The pin to use on PA for virtual gpio interrupt.

config ETRAX_PA_CHANGEABLE_DIR
hex "PA user changeable dir mask"
depends on ETRAX_GPIO
- default "0x00"
+ default "0x00" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (8 bits) with information of what bits in PA that a
user can change direction on using ioctl's.
Bit set = changeable.
- You probably want 0x00 here, but it depends on your hardware.
+ You probably want 0 here, but it depends on your hardware.

config ETRAX_PA_CHANGEABLE_BITS
hex "PA user changeable bits mask"
depends on ETRAX_GPIO
- default "0x00"
+ default "0x00" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (8 bits) with information of what bits in PA
that a user can change the value on using ioctl's.
@@ -509,17 +556,19 @@ config ETRAX_PA_CHANGEABLE_BITS
config ETRAX_PB_CHANGEABLE_DIR
hex "PB user changeable dir mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PB
that a user can change direction on using ioctl's.
Bit set = changeable.
- You probably want 0x00000 here, but it depends on your hardware.
+ You probably want 0 here, but it depends on your hardware.

config ETRAX_PB_CHANGEABLE_BITS
hex "PB user changeable bits mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PB
that a user can change the value on using ioctl's.
@@ -528,17 +577,19 @@ config ETRAX_PB_CHANGEABLE_BITS
config ETRAX_PC_CHANGEABLE_DIR
hex "PC user changeable dir mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PC
that a user can change direction on using ioctl's.
Bit set = changeable.
- You probably want 0x00000 here, but it depends on your hardware.
+ You probably want 0 here, but it depends on your hardware.

config ETRAX_PC_CHANGEABLE_BITS
hex "PC user changeable bits mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PC
that a user can change the value on using ioctl's.
@@ -546,7 +597,7 @@ config ETRAX_PC_CHANGEABLE_BITS

config ETRAX_PD_CHANGEABLE_DIR
hex "PD user changeable dir mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PD
@@ -556,7 +607,7 @@ config ETRAX_PD_CHANGEABLE_DIR

config ETRAX_PD_CHANGEABLE_BITS
hex "PD user changeable bits mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PD
@@ -565,7 +616,7 @@ config ETRAX_PD_CHANGEABLE_BITS

config ETRAX_PE_CHANGEABLE_DIR
hex "PE user changeable dir mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
@@ -575,20 +626,36 @@ config ETRAX_PE_CHANGEABLE_DIR

config ETRAX_PE_CHANGEABLE_BITS
hex "PE user changeable bits mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
that a user can change the value on using ioctl's.
Bit set = changeable.

+config ETRAX_PV_CHANGEABLE_DIR
+ hex "PV user changeable dir mask"
+ depends on ETRAX_VIRTUAL_GPIO
+ default "0x0000"
+ help
+ This is a bitmask (16 bits) with information of what bits in PV
+ that a user can change direction on using ioctl's.
+ Bit set = changeable.
+ You probably want 0x0000 here, but it depends on your hardware.
+
+config ETRAX_PV_CHANGEABLE_BITS
+ hex "PV user changeable bits mask"
+ depends on ETRAX_VIRTUAL_GPIO
+ default "0x0000"
+ help
+ This is a bitmask (16 bits) with information of what bits in PV
+ that a user can change the value on using ioctl's.
+ Bit set = changeable.
+
config ETRAX_CARDBUS
bool "Cardbus support"
depends on ETRAX_ARCH_V32
- select PCCARD
- select CARDBUS
select HOTPLUG
- select PCCARD_NONSTATIC
help
Enabled the ETRAX Cardbus driver.

@@ -610,3 +677,203 @@ config ETRAX_STREAMCOPROC
help
This option enables a driver for the stream co-processor
for cryptographic operations.
+
+source drivers/mmc/Kconfig
+
+config ETRAX_MMC_IOP
+ tristate "MMC/SD host driver using IO-processor"
+ depends on ETRAX_ARCH_V32 && MMC
+ help
+ This option enables the SD/MMC host controller interface.
+ The host controller is implemented using the built in
+ IO-Processor. Only the SPU is used in this implementation.
+
+config ETRAX_SPI_MMC
+# Make this one of several "choices" (possible simultaneously but
+# suggested uniquely) when an IOP driver emerges for "real" MMC/SD
+# protocol support.
+ tristate
+ depends on !ETRAX_MMC_IOP
+ default MMC
+ select SPI
+ select MMC_SPI
+ select ETRAX_SPI_MMC_BOARD
+
+# For the parts that can't be a module (due to restrictions in
+# framework elsewhere).
+config ETRAX_SPI_MMC_BOARD
+ boolean
+ default n
+
+# While the board info is MMC_SPI only, the drivers are written to be
+# independent of MMC_SPI, so we'll keep SPI non-dependent on the
+# MMC_SPI config choices (well, except for a single depends-on-line
+# for the board-info file until a separate non-MMC SPI board file
+# emerges).
+# FIXME: When that happens, we'll need to be able to ask for and
+# configure non-MMC SPI ports together with MMC_SPI ports (if multiple
+# SPI ports are enabled).
+
+config SPI_ETRAX_SSER
+ tristate
+ depends on SPI_MASTER && ETRAX_ARCH_V32 && EXPERIMENTAL
+ select SPI_BITBANG
+ help
+ This enables using an synchronous serial (sser) port as a
+ SPI master controller on Axis ETRAX FS and later. The
+ driver can be configured to use any sser port.
+
+config SPI_ETRAX_GPIO
+ tristate
+ depends on SPI_MASTER && ETRAX_ARCH_V32 && EXPERIMENTAL
+ select SPI_BITBANG
+ help
+ This enables using GPIO pins port as a SPI master controller
+ on Axis ETRAX FS and later. The driver can be configured to
+ use any GPIO pins.
+
+config ETRAX_SPI_SSER0
+ tristate "SPI using synchronous serial port 0 (sser0)"
+ depends on ETRAX_SPI_MMC
+ default m if MMC_SPI=m
+ default y if MMC_SPI=y
+ default y if MMC_SPI=n
+ select SPI_ETRAX_SSER
+ help
+ Say Y for an MMC/SD socket connected to synchronous serial port 0,
+ or for devices using the SPI protocol on that port. Say m if you
+ want to build it as a module, which will be named spi_crisv32_sser.
+ (You need to select MMC separately.)
+
+config ETRAX_SPI_SSER0_DMA
+ bool "DMA for SPI on sser0 enabled"
+ depends on ETRAX_SPI_SSER0
+ depends on !ETRAX_SERIAL_PORT1_DMA4_OUT && !ETRAX_SERIAL_PORT1_DMA5_IN
+ default y
+ help
+ Say Y if using DMA (dma4/dma5) for SPI on synchronous serial port 0.
+
+config ETRAX_SPI_MMC_CD_SSER0_PIN
+ string "MMC/SD card detect pin for SPI on sser0"
+ depends on ETRAX_SPI_SSER0 && MMC_SPI
+ default "pd11"
+ help
+ The pin to use for SD/MMC card detect. This pin should be pulled up
+ and grounded when a card is present. If defined as " " (space), no
+ pin is selected. A card must then always be inserted for proper
+ action.
+
+config ETRAX_SPI_MMC_WP_SSER0_PIN
+ string "MMC/SD card write-protect pin for SPI on sser0"
+ depends on ETRAX_SPI_SSER0 && MMC_SPI
+ default "pd10"
+ help
+ The pin to use for the SD/MMC write-protect signal for a memory
+ card. If defined as " " (space), the card is considered writable.
+
+config ETRAX_SPI_SSER1
+ tristate "SPI using synchronous serial port 1 (sser1)"
+ depends on ETRAX_SPI_MMC
+ default m if MMC_SPI=m && ETRAX_SPI_SSER0=n
+ default y if MMC_SPI=y && ETRAX_SPI_SSER0=n
+ default y if MMC_SPI=n && ETRAX_SPI_SSER0=n
+ select SPI_ETRAX_SSER
+ help
+ Say Y for an MMC/SD socket connected to synchronous serial port 1,
+ or for devices using the SPI protocol on that port. Say m if you
+ want to build it as a module, which will be named spi_crisv32_sser.
+ (You need to select MMC separately.)
+
+config ETRAX_SPI_SSER1_DMA
+ bool "DMA for SPI on sser1 enabled"
+ depends on ETRAX_SPI_SSER1 && !ETRAX_ETHERNET_IFACE1
+ depends on !ETRAX_SERIAL_PORT0_DMA6_OUT && !ETRAX_SERIAL_PORT0_DMA7_IN
+ default y
+ help
+ Say Y if using DMA (dma6/dma7) for SPI on synchronous serial port 1.
+
+config ETRAX_SPI_MMC_CD_SSER1_PIN
+ string "MMC/SD card detect pin for SPI on sser1"
+ depends on ETRAX_SPI_SSER1 && MMC_SPI
+ default "pd12"
+ help
+ The pin to use for SD/MMC card detect. This pin should be pulled up
+ and grounded when a card is present. If defined as " " (space), no
+ pin is selected. A card must then always be inserted for proper
+ action.
+
+config ETRAX_SPI_MMC_WP_SSER1_PIN
+ string "MMC/SD card write-protect pin for SPI on sser1"
+ depends on ETRAX_SPI_SSER1 && MMC_SPI
+ default "pd9"
+ help
+ The pin to use for the SD/MMC write-protect signal for a memory
+ card. If defined as " " (space), the card is considered writable.
+
+config ETRAX_SPI_GPIO
+ tristate "Bitbanged SPI using gpio pins"
+ depends on ETRAX_SPI_MMC
+ select SPI_ETRAX_GPIO
+ default m if MMC_SPI=m && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
+ default y if MMC_SPI=y && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
+ default y if MMC_SPI=n && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
+ help
+ Say Y for an MMC/SD socket connected to general I/O pins (but not
+ a complete synchronous serial ports), or for devices using the SPI
+ protocol on general I/O pins. Slow and slows down the system.
+ Say m to build it as a module, which will be called spi_crisv32_gpio.
+ (You need to select MMC separately.)
+
+# The default match that of sser0, only because that's how it was tested.
+config ETRAX_SPI_CS_PIN
+ string "SPI chip select pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc3"
+ help
+ The pin to use for SPI chip select.
+
+config ETRAX_SPI_CLK_PIN
+ string "SPI clock pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc1"
+ help
+ The pin to use for the SPI clock.
+
+config ETRAX_SPI_DATAIN_PIN
+ string "SPI MISO (data in) pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc16"
+ help
+ The pin to use for SPI data in from the device.
+
+config ETRAX_SPI_DATAOUT_PIN
+ string "SPI MOSI (data out) pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc0"
+ help
+ The pin to use for SPI data out to the device.
+
+config ETRAX_SPI_MMC_CD_GPIO_PIN
+ string "MMC/SD card detect pin for SPI using gpio (space for none)"
+ depends on ETRAX_SPI_GPIO && MMC_SPI
+ default "pd11"
+ help
+ The pin to use for SD/MMC card detect. This pin should be pulled up
+ and grounded when a card is present. If defined as " " (space), no
+ pin is selected. A card must then always be inserted for proper
+ action.
+
+config ETRAX_SPI_MMC_WP_GPIO_PIN
+ string "MMC/SD card write-protect pin for SPI using gpio (space for none)"
+ depends on ETRAX_SPI_GPIO && MMC_SPI
+ default "pd10"
+ help
+ The pin to use for the SD/MMC write-protect signal for a memory
+ card. If defined as " " (space), the card is considered writable.
+
+# Avoid choices causing non-working configs by conditionalizing the inclusion.
+if ETRAX_SPI_MMC
+source drivers/spi/Kconfig
+endif
+
+endif
--
1.5.3.6.970.gd25430

2007-12-06 12:42:26

by Jesper Nilsson

Subject: [PATCH 02/47] Add new driver files for Artpec-3.

Adds gpio and nandflash handling for Artpec-3.

Signed-off-by: Jesper Nilsson <[email protected]>
---
arch/cris/arch-v32/drivers/mach-a3/Makefile | 6 +
arch/cris/arch-v32/drivers/mach-a3/gpio.c | 984 ++++++++++++++++++++++++
arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 178 +++++
3 files changed, 1168 insertions(+), 0 deletions(-)
create mode 100644 arch/cris/arch-v32/drivers/mach-a3/Makefile
create mode 100644 arch/cris/arch-v32/drivers/mach-a3/gpio.c
create mode 100644 arch/cris/arch-v32/drivers/mach-a3/nandflash.c

diff --git a/arch/cris/arch-v32/drivers/mach-a3/Makefile b/arch/cris/arch-v32/drivers/mach-a3/Makefile
new file mode 100644
index 0000000..5c6d2a2
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/mach-a3/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for Etrax-specific drivers
+#
+
+obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
+obj-$(CONFIG_ETRAX_GPIO) += gpio.o
diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
new file mode 100644
index 0000000..4c48065
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
@@ -0,0 +1,984 @@
+/*
+ * Artec-3 general port I/O device
+ *
+ * Copyright (c) 2007 Axis Communications AB
+ *
+ * Authors: Bjorn Wesen (initial version)
+ * Ola Knutsson (LED handling)
+ * Johan Adolfsson (read/set directions, write, port G,
+ * port to ETRAX FS.
+ * Ricard Wanderlof (PWM for Artpec-3)
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/etraxgpio.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/gio_defs.h>
+#include <hwregs/intr_vect_defs.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/arch/mach/pinmux.h>
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+#include "../i2c.h"
+
+#define VIRT_I2C_ADDR 0x40
+#endif
+
+/* The following gio ports on ARTPEC-3 is available:
+ * pa 32 bits
+ * pb 32 bits
+ * pc 16 bits
+ * each port has a rw_px_dout, r_px_din and rw_px_oe register.
+ */
+
+#define GPIO_MAJOR 120 /* experimental MAJOR number */
+
+#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
+
+#define D(x)
+
+#if 0
+static int dp_cnt;
+#define DP(x) \
+ do { \
+ dp_cnt++; \
+ if (dp_cnt % 1000 == 0) \
+ x; \
+ } while (0)
+#else
+#define DP(x)
+#endif
+
+static char gpio_name[] = "etrax gpio";
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg);
+#endif
+static int gpio_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
+ loff_t *off);
+static int gpio_open(struct inode *inode, struct file *filp);
+static int gpio_release(struct inode *inode, struct file *filp);
+static unsigned int gpio_poll(struct file *filp,
+ struct poll_table_struct *wait);
+
+/* private data per open() of this driver */
+
+struct gpio_private {
+ struct gpio_private *next;
+ /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
+ unsigned char clk_mask;
+ unsigned char data_mask;
+ unsigned char write_msb;
+ unsigned char pad1;
+ /* These fields are generic */
+ unsigned long highalarm, lowalarm;
+ wait_queue_head_t alarm_wq;
+ int minor;
+};
+
+static void gpio_set_alarm(struct gpio_private *priv);
+
+/* linked list of alarms to check for */
+
+static struct gpio_private *alarmlist;
+
+static int wanted_interrupts;
+
+static DEFINE_SPINLOCK(alarm_lock);
+
+#define NUM_PORTS (GPIO_MINOR_LAST+1)
+#define GIO_REG_RD_ADDR(reg) \
+ (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
+#define GIO_REG_WR_ADDR(reg) \
+ (volatile unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
+unsigned long led_dummy;
+unsigned long port_d_dummy; /* Only input on Artpec-3 */
+unsigned long port_e_dummy; /* Non existent on Artpec-3 */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static unsigned long virtual_dummy;
+static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
+static unsigned short cached_virtual_gpio_read;
+#endif
+
+static volatile unsigned long *data_out[NUM_PORTS] = {
+ GIO_REG_WR_ADDR(rw_pa_dout),
+ GIO_REG_WR_ADDR(rw_pb_dout),
+ &led_dummy,
+ GIO_REG_WR_ADDR(rw_pc_dout),
+ &port_d_dummy,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &port_e_dummy,
+ &virtual_dummy,
+#endif
+};
+
+static volatile unsigned long *data_in[NUM_PORTS] = {
+ GIO_REG_RD_ADDR(r_pa_din),
+ GIO_REG_RD_ADDR(r_pb_din),
+ &led_dummy,
+ GIO_REG_RD_ADDR(r_pc_din),
+ GIO_REG_RD_ADDR(r_pd_din),
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &port_e_dummy,
+ &virtual_dummy,
+#endif
+};
+
+static unsigned long changeable_dir[NUM_PORTS] = {
+ CONFIG_ETRAX_PA_CHANGEABLE_DIR,
+ CONFIG_ETRAX_PB_CHANGEABLE_DIR,
+ 0,
+ CONFIG_ETRAX_PC_CHANGEABLE_DIR,
+ 0,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ 0,
+ CONFIG_ETRAX_PV_CHANGEABLE_DIR,
+#endif
+};
+
+static unsigned long changeable_bits[NUM_PORTS] = {
+ CONFIG_ETRAX_PA_CHANGEABLE_BITS,
+ CONFIG_ETRAX_PB_CHANGEABLE_BITS,
+ 0,
+ CONFIG_ETRAX_PC_CHANGEABLE_BITS,
+ 0,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ 0,
+ CONFIG_ETRAX_PV_CHANGEABLE_BITS,
+#endif
+};
+
+static volatile unsigned long *dir_oe[NUM_PORTS] = {
+ GIO_REG_WR_ADDR(rw_pa_oe),
+ GIO_REG_WR_ADDR(rw_pb_oe),
+ &led_dummy,
+ GIO_REG_WR_ADDR(rw_pc_oe),
+ &port_d_dummy,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &port_e_dummy,
+ &virtual_rw_pv_oe,
+#endif
+};
+
+static void
+gpio_set_alarm(struct gpio_private *priv)
+{
+ int bit;
+ int intr_cfg;
+ int mask;
+ int pins;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
+ pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
+ mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
+
+ for (bit = 0; bit < 32; bit++) {
+ int intr = bit % 8;
+ int pin = bit / 8;
+ if (priv->minor < GPIO_MINOR_LEDS)
+ pin += priv->minor * 4;
+ else
+ pin += (priv->minor - 1) * 4;
+
+ if (priv->highalarm & (1<<bit)) {
+ intr_cfg |= (regk_gio_hi << (intr * 3));
+ mask |= 1 << intr;
+ wanted_interrupts = mask & 0xff;
+ pins |= pin << (intr * 4);
+ } else if (priv->lowalarm & (1<<bit)) {
+ intr_cfg |= (regk_gio_lo << (intr * 3));
+ mask |= 1 << intr;
+ wanted_interrupts = mask & 0xff;
+ pins |= pin << (intr * 4);
+ }
+ }
+
+ REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
+ REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
+ REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
+
+ local_irq_restore(flags);
+}
+
+static unsigned int
+gpio_poll(struct file *file, struct poll_table_struct *wait)
+{
+ unsigned int mask = 0;
+ struct gpio_private *priv = (struct gpio_private *)file->private_data;
+ unsigned long data;
+ unsigned long tmp;
+
+ if (priv->minor >= GPIO_MINOR_PWM0 &&
+ priv->minor <= GPIO_MINOR_LAST_PWM)
+ return 0;
+
+ poll_wait(file, &priv->alarm_wq, wait);
+ if (priv->minor <= GPIO_MINOR_D) {
+ data = *data_in[priv->minor];
+ REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
+ tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
+ tmp &= I2C_INTERRUPT_BITS;
+ tmp |= wanted_interrupts;
+ REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
+ } else
+ return 0;
+
+ if ((data & priv->highalarm) || (~data & priv->lowalarm))
+ mask = POLLIN|POLLRDNORM;
+
+ DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
+ return mask;
+}
+
+static irqreturn_t
+gpio_interrupt(int irq, void *dev_id)
+{
+ reg_gio_rw_intr_mask intr_mask;
+ reg_gio_r_masked_intr masked_intr;
+ reg_gio_rw_ack_intr ack_intr;
+ unsigned long tmp;
+ unsigned long tmp2;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ unsigned char enable_gpiov_ack = 0;
+#endif
+
+ /* Find what PA interrupts are active */
+ masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
+ tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
+
+ /* Find those that we have enabled */
+ spin_lock(&alarm_lock);
+ tmp &= wanted_interrupts;
+ spin_unlock(&alarm_lock);
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Something changed on virtual GPIO. Interrupt is acked by
+ * reading the device.
+ */
+ if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
+ i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
+ sizeof(cached_virtual_gpio_read));
+ enable_gpiov_ack = 1;
+ }
+#endif
+
+ /* Ack them */
+ ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
+ REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
+
+ /* Disable those interrupts.. */
+ intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
+ tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
+ tmp2 &= ~tmp;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Do not disable interrupt on virtual GPIO. Changes on virtual
+ * pins are only noticed by an interrupt.
+ */
+ if (enable_gpiov_ack)
+ tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+ intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
+ REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
+
+ return IRQ_RETVAL(tmp);
+}
+
+
+static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
+ loff_t *off)
+{
+ struct gpio_private *priv = (struct gpio_private *)file->private_data;
+ unsigned char data, clk_mask, data_mask, write_msb;
+ unsigned long flags;
+ unsigned long shadow;
+ volatile unsigned long *port;
+ ssize_t retval = count;
+ /* Only bits 0-7 may be used for write operations but allow all
+ devices except leds... */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ return -EFAULT;
+#endif
+ if (priv->minor == GPIO_MINOR_LEDS)
+ return -EFAULT;
+
+ if (priv->minor >= GPIO_MINOR_PWM0 &&
+ priv->minor <= GPIO_MINOR_LAST_PWM)
+ return -EFAULT;
+
+ if (!access_ok(VERIFY_READ, buf, count))
+ return -EFAULT;
+
+ clk_mask = priv->clk_mask;
+ data_mask = priv->data_mask;
+ /* It must have been configured using the IO_CFG_WRITE_MODE */
+ /* Perhaps a better error code? */
+ if (clk_mask == 0 || data_mask == 0)
+ return -EPERM;
+
+ write_msb = priv->write_msb;
+ D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
+ "msb: %i\n",
+ count, data_mask, clk_mask, write_msb));
+ port = data_out[priv->minor];
+
+ while (count--) {
+ int i;
+ data = *buf++;
+ if (priv->write_msb) {
+ for (i = 7; i >= 0; i--) {
+ local_irq_save(flags);
+ shadow = *port;
+ *port = shadow &= ~clk_mask;
+ if (data & 1<<i)
+ *port = shadow |= data_mask;
+ else
+ *port = shadow &= ~data_mask;
+ /* For FPGA: min 5.0ns (DCC) before CCLK high */
+ *port = shadow |= clk_mask;
+ local_irq_restore(flags);
+ }
+ } else {
+ for (i = 0; i <= 7; i++) {
+ local_irq_save(flags);
+ shadow = *port;
+ *port = shadow &= ~clk_mask;
+ if (data & 1<<i)
+ *port = shadow |= data_mask;
+ else
+ *port = shadow &= ~data_mask;
+ /* For FPGA: min 5.0ns (DCC) before CCLK high */
+ *port = shadow |= clk_mask;
+ local_irq_restore(flags);
+ }
+ }
+ }
+ return retval;
+}
+
+static int
+gpio_open(struct inode *inode, struct file *filp)
+{
+ struct gpio_private *priv;
+ int p = iminor(inode);
+
+ if (p > GPIO_MINOR_LAST_PWM ||
+ (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
+ return -EINVAL;
+
+ priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
+
+ if (!priv)
+ return -ENOMEM;
+ memset(priv, 0, sizeof(*priv));
+
+ priv->minor = p;
+ filp->private_data = (void *)priv;
+
+ /* initialize the io/alarm struct, not for PWM ports though */
+ if (p <= GPIO_MINOR_LAST) {
+
+ priv->clk_mask = 0;
+ priv->data_mask = 0;
+ priv->highalarm = 0;
+ priv->lowalarm = 0;
+
+ init_waitqueue_head(&priv->alarm_wq);
+
+ /* link it into our alarmlist */
+ spin_lock_irq(&alarm_lock);
+ priv->next = alarmlist;
+ alarmlist = priv;
+ spin_unlock_irq(&alarm_lock);
+ }
+
+ return 0;
+}
+
+static int
+gpio_release(struct inode *inode, struct file *filp)
+{
+ struct gpio_private *p;
+ struct gpio_private *todel;
+ /* local copies while updating them: */
+ unsigned long a_high, a_low;
+
+ /* prepare to free private structure */
+ todel = (struct gpio_private *)filp->private_data;
+
+ /* unlink from alarmlist - only for non-PWM ports though */
+ if (todel->minor <= GPIO_MINOR_LAST) {
+ spin_lock_irq(&alarm_lock);
+ p = alarmlist;
+
+ if (p == todel)
+ alarmlist = todel->next;
+ else {
+ while (p->next != todel)
+ p = p->next;
+ p->next = todel->next;
+ }
+
+ /* Check if there are still any alarms set */
+ p = alarmlist;
+ a_high = 0;
+ a_low = 0;
+ while (p) {
+ if (p->minor == GPIO_MINOR_A) {
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+ a_high |= p->highalarm;
+ a_low |= p->lowalarm;
+ }
+
+ p = p->next;
+ }
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Variable 'a_low' needs to be set here again
+ * to ensure that interrupt for virtual GPIO is handled.
+ */
+ a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+
+ spin_unlock_irq(&alarm_lock);
+ }
+ kfree(todel);
+
+ return 0;
+}
+
+/* Main device API. ioctl's to read/set/clear bits, as well as to
+ * set alarms to wait for using a subsequent select().
+ */
+
+inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
+{
+ /* Set direction 0=unchanged 1=input,
+ * return mask with 1=input
+ */
+ unsigned long flags;
+ unsigned long dir_shadow;
+
+ local_irq_save(flags);
+ dir_shadow = *dir_oe[priv->minor];
+ dir_shadow &= ~(arg & changeable_dir[priv->minor]);
+ *dir_oe[priv->minor] = dir_shadow;
+ local_irq_restore(flags);
+
+ if (priv->minor == GPIO_MINOR_C)
+ dir_shadow ^= 0xFFFF; /* Only 16 bits */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ else if (priv->minor == GPIO_MINOR_V)
+ dir_shadow ^= 0xFFFF; /* Only 16 bits */
+#endif
+ else
+ dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
+
+ return dir_shadow;
+
+} /* setget_input */
+
+inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
+{
+ unsigned long flags;
+ unsigned long dir_shadow;
+
+ local_irq_save(flags);
+ dir_shadow = *dir_oe[priv->minor];
+ dir_shadow |= (arg & changeable_dir[priv->minor]);
+ *dir_oe[priv->minor] = dir_shadow;
+ local_irq_restore(flags);
+ return dir_shadow;
+} /* setget_output */
+
+static int
+gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
+
+static int
+gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg);
+
+static int
+gpio_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ unsigned long flags;
+ unsigned long val;
+ unsigned long shadow;
+ struct gpio_private *priv = (struct gpio_private *)file->private_data;
+
+ if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
+ return -EINVAL;
+
+ /* Check for special ioctl handlers first */
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ return virtual_gpio_ioctl(file, cmd, arg);
+#endif
+
+ if (priv->minor == GPIO_MINOR_LEDS)
+ return gpio_leds_ioctl(cmd, arg);
+
+ if (priv->minor >= GPIO_MINOR_PWM0 &&
+ priv->minor <= GPIO_MINOR_LAST_PWM)
+ return gpio_pwm_ioctl(priv, cmd, arg);
+
+ switch (_IOC_NR(cmd)) {
+ case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
+ /* Read the port. */
+ return *data_in[priv->minor];
+ break;
+ case IO_SETBITS:
+ local_irq_save(flags);
+ /* Set changeable bits with a 1 in arg. */
+ shadow = *data_out[priv->minor];
+ shadow |= (arg & changeable_bits[priv->minor]);
+ *data_out[priv->minor] = shadow;
+ local_irq_restore(flags);
+ break;
+ case IO_CLRBITS:
+ local_irq_save(flags);
+ /* Clear changeable bits with a 1 in arg. */
+ shadow = *data_out[priv->minor];
+ shadow &= ~(arg & changeable_bits[priv->minor]);
+ *data_out[priv->minor] = shadow;
+ local_irq_restore(flags);
+ break;
+ case IO_HIGHALARM:
+ /* Set alarm when bits with 1 in arg go high. */
+ priv->highalarm |= arg;
+ gpio_set_alarm(priv);
+ break;
+ case IO_LOWALARM:
+ /* Set alarm when bits with 1 in arg go low. */
+ priv->lowalarm |= arg;
+ gpio_set_alarm(priv);
+ break;
+ case IO_CLRALARM:
+ /* Clear alarm for bits with 1 in arg. */
+ priv->highalarm &= ~arg;
+ priv->lowalarm &= ~arg;
+ gpio_set_alarm(priv);
+ break;
+ case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
+ /* Read direction 0=input 1=output */
+ return *dir_oe[priv->minor];
+ case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
+ /* Set direction 0=unchanged 1=input,
+ * return mask with 1=input
+ */
+ return setget_input(priv, arg);
+ break;
+ case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
+ /* Set direction 0=unchanged 1=output,
+ * return mask with 1=output
+ */
+ return setget_output(priv, arg);
+
+ case IO_CFG_WRITE_MODE:
+ {
+ unsigned long dir_shadow;
+ dir_shadow = *dir_oe[priv->minor];
+
+ priv->clk_mask = arg & 0xFF;
+ priv->data_mask = (arg >> 8) & 0xFF;
+ priv->write_msb = (arg >> 16) & 0x01;
+ /* Check if we're allowed to change the bits and
+ * the direction is correct
+ */
+ if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
+ (priv->data_mask & changeable_bits[priv->minor]) &&
+ (priv->clk_mask & dir_shadow) &&
+ (priv->data_mask & dir_shadow))) {
+ priv->clk_mask = 0;
+ priv->data_mask = 0;
+ return -EPERM;
+ }
+ break;
+ }
+ case IO_READ_INBITS:
+ /* *arg is result of reading the input pins */
+ val = *data_in[priv->minor];
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ return 0;
+ break;
+ case IO_READ_OUTBITS:
+ /* *arg is result of reading the output shadow */
+ val = *data_out[priv->minor];
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_INPUT:
+ /* bits set in *arg is set to input,
+ * *arg updated with current input pins.
+ */
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_input(priv, val);
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_OUTPUT:
+ /* bits set in *arg is set to output,
+ * *arg updated with current output pins.
+ */
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_output(priv, val);
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ default:
+ return -EINVAL;
+ } /* switch */
+
+ return 0;
+}
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static int
+virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ unsigned long flags;
+ unsigned short val;
+ unsigned short shadow;
+ struct gpio_private *priv = (struct gpio_private *)file->private_data;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_SETBITS:
+ local_irq_save(flags);
+ /* Set changeable bits with a 1 in arg. */
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ shadow |= ~*dir_oe[priv->minor];
+ shadow |= (arg & changeable_bits[priv->minor]);
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ local_irq_restore(flags);
+ break;
+ case IO_CLRBITS:
+ local_irq_save(flags);
+ /* Clear changeable bits with a 1 in arg. */
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ shadow |= ~*dir_oe[priv->minor];
+ shadow &= ~(arg & changeable_bits[priv->minor]);
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ local_irq_restore(flags);
+ break;
+ case IO_HIGHALARM:
+ /* Set alarm when bits with 1 in arg go high. */
+ priv->highalarm |= arg;
+ break;
+ case IO_LOWALARM:
+ /* Set alarm when bits with 1 in arg go low. */
+ priv->lowalarm |= arg;
+ break;
+ case IO_CLRALARM:
+ /* Clear alarm for bits with 1 in arg. */
+ priv->highalarm &= ~arg;
+ priv->lowalarm &= ~arg;
+ break;
+ case IO_CFG_WRITE_MODE:
+ {
+ unsigned long dir_shadow;
+ dir_shadow = *dir_oe[priv->minor];
+
+ priv->clk_mask = arg & 0xFF;
+ priv->data_mask = (arg >> 8) & 0xFF;
+ priv->write_msb = (arg >> 16) & 0x01;
+ /* Check if we're allowed to change the bits and
+ * the direction is correct
+ */
+ if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
+ (priv->data_mask & changeable_bits[priv->minor]) &&
+ (priv->clk_mask & dir_shadow) &&
+ (priv->data_mask & dir_shadow))) {
+ priv->clk_mask = 0;
+ priv->data_mask = 0;
+ return -EPERM;
+ }
+ break;
+ }
+ case IO_READ_INBITS:
+ /* *arg is result of reading the input pins */
+ val = cached_virtual_gpio_read;
+ val &= ~*dir_oe[priv->minor];
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ return 0;
+ break;
+ case IO_READ_OUTBITS:
+ /* *arg is result of reading the output shadow */
+ i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
+ val &= *dir_oe[priv->minor];
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_INPUT:
+ {
+ /* bits set in *arg is set to input,
+ * *arg updated with current input pins.
+ */
+ unsigned short input_mask = ~*dir_oe[priv->minor];
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_input(priv, val);
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ if ((input_mask & val) != input_mask) {
+ /* Input pins changed. All ports desired as input
+ * should be set to logic 1.
+ */
+ unsigned short change = input_mask ^ val;
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
+ sizeof(shadow));
+ shadow &= ~change;
+ shadow |= val;
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
+ sizeof(shadow));
+ }
+ break;
+ }
+ case IO_SETGET_OUTPUT:
+ /* bits set in *arg is set to output,
+ * *arg updated with current output pins.
+ */
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_output(priv, val);
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ default:
+ return -EINVAL;
+ } /* switch */
+ return 0;
+}
+#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
+
+static int
+gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
+{
+ unsigned char green;
+ unsigned char red;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_LEDACTIVE_SET:
+ green = ((unsigned char) arg) & 1;
+ red = (((unsigned char) arg) >> 1) & 1;
+ LED_ACTIVE_SET_G(green);
+ LED_ACTIVE_SET_R(red);
+ break;
+
+ default:
+ return -EINVAL;
+ } /* switch */
+
+ return 0;
+}
+
+static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
+{
+ int pinmux_pwm = pinmux_pwm0 + pwm_port;
+ int mode;
+ reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
+ .ccd_val = 0,
+ .ccd_override = regk_gio_no,
+ .mode = regk_gio_no
+ };
+ int allocstatus;
+
+ if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
+ return -EFAULT;
+ rw_pwm_ctrl.mode = mode;
+ if (mode != PWM_OFF)
+ allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
+ else
+ allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
+ if (allocstatus)
+ return allocstatus;
+ REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
+ 12 * pwm_port, rw_pwm_ctrl);
+ return 0;
+}
+
+static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
+{
+ struct io_pwm_set_period periods;
+ reg_gio_rw_pwm0_var rw_pwm_widths;
+
+ if (copy_from_user(&periods, (struct io_pwm_set_period *) arg,
+ sizeof(periods)))
+ return -EFAULT;
+ if (periods.lo > 8191 || periods.hi > 8191)
+ return -EINVAL;
+ rw_pwm_widths.lo = periods.lo;
+ rw_pwm_widths.hi = periods.hi;
+ REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
+ 12 * pwm_port, rw_pwm_widths);
+ return 0;
+}
+
+static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
+{
+ unsigned int duty;
+ reg_gio_rw_pwm0_data rw_pwm_duty;
+
+ if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
+ return -EFAULT;
+ if (duty > 255)
+ return -EINVAL;
+ rw_pwm_duty.data = duty;
+ REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
+ 12 * pwm_port, rw_pwm_duty);
+ return 0;
+}
+
+static int
+gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd, unsigned long arg)
+{
+ int pwm_port = priv->minor - GPIO_MINOR_PWM0;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_PWM_SET_MODE:
+ return gpio_pwm_set_mode(arg, pwm_port);
+ case IO_PWM_SET_PERIOD:
+ return gpio_pwm_set_period(arg, pwm_port);
+ case IO_PWM_SET_DUTY:
+ return gpio_pwm_set_duty(arg, pwm_port);
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+struct file_operations gpio_fops = {
+ .owner = THIS_MODULE,
+ .poll = gpio_poll,
+ .ioctl = gpio_ioctl,
+ .write = gpio_write,
+ .open = gpio_open,
+ .release = gpio_release,
+};
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static void
+virtual_gpio_init(void)
+{
+ reg_gio_rw_intr_cfg intr_cfg;
+ reg_gio_rw_intr_mask intr_mask;
+ unsigned short shadow;
+
+ shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
+ shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+
+ /* Set interrupt mask and on what state the interrupt shall trigger.
+ * For virtual gpio the interrupt shall trigger on logic '0'.
+ */
+ intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
+ intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
+
+ switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
+ case 0:
+ intr_cfg.pa0 = regk_gio_lo;
+ intr_mask.pa0 = regk_gio_yes;
+ break;
+ case 1:
+ intr_cfg.pa1 = regk_gio_lo;
+ intr_mask.pa1 = regk_gio_yes;
+ break;
+ case 2:
+ intr_cfg.pa2 = regk_gio_lo;
+ intr_mask.pa2 = regk_gio_yes;
+ break;
+ case 3:
+ intr_cfg.pa3 = regk_gio_lo;
+ intr_mask.pa3 = regk_gio_yes;
+ break;
+ case 4:
+ intr_cfg.pa4 = regk_gio_lo;
+ intr_mask.pa4 = regk_gio_yes;
+ break;
+ case 5:
+ intr_cfg.pa5 = regk_gio_lo;
+ intr_mask.pa5 = regk_gio_yes;
+ break;
+ case 6:
+ intr_cfg.pa6 = regk_gio_lo;
+ intr_mask.pa6 = regk_gio_yes;
+ break;
+ case 7:
+ intr_cfg.pa7 = regk_gio_lo;
+ intr_mask.pa7 = regk_gio_yes;
+ break;
+ }
+
+ REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
+ REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
+}
+#endif
+
+/* main driver initialization routine, called from mem.c */
+
+static __init int
+gpio_init(void)
+{
+ int res;
+
+ /* do the formalities */
+
+ res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
+ if (res < 0) {
+ printk(KERN_ERR "gpio: couldn't get a major number.\n");
+ return res;
+ }
+
+ /* Clear all leds */
+ LED_NETWORK_GRP0_SET(0);
+ LED_NETWORK_GRP1_SET(0);
+ LED_ACTIVE_SET(0);
+ LED_DISK_READ(0);
+ LED_DISK_WRITE(0);
+
+ printk(KERN_INFO "ETRAX FS GPIO driver v2.6, (c) 2003-2007 "
+ "Axis Communications AB\n");
+ if (request_irq(GIO_INTR_VECT, gpio_interrupt,
+ IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist))
+ printk(KERN_ERR "err: irq for gpio\n");
+
+ /* No IRQs by default. */
+ REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ virtual_gpio_init();
+#endif
+
+ return res;
+}
+
+/* this makes sure that gpio_init is called during kernel boot */
+
+module_init(gpio_init);
diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
new file mode 100644
index 0000000..2fda3db
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
@@ -0,0 +1,178 @@
+/*
+ * arch/cris/arch-v32/drivers/nandflash.c
+ *
+ * Copyright (c) 2007
+ *
+ * Derived from drivers/mtd/nand/spia.c
+ * Copyright (C) 2000 Steven J. Hill ([email protected])
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/memmap.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/pio_defs.h>
+#include <pinmux.h>
+#include <asm/io.h>
+
+#define MANUAL_ALE_CLE_CONTROL 1
+
+#define regf_ALE a0
+#define regf_CLE a1
+#define regf_NCE ce0_n
+
+#define CLE_BIT 10
+#define ALE_BIT 11
+#define CE_BIT 12
+
+/* Bitmask for control pins */
+#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
+
+static struct mtd_info *crisv32_mtd;
+/*
+ * hardware specific access to control-lines
+ */
+static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ unsigned long flags;
+ reg_pio_rw_dout dout;
+ struct nand_chip *this = mtd->priv;
+
+ local_irq_save(flags);
+
+ /* control bits change */
+ if (ctrl & NAND_CTRL_CHANGE) {
+ dout = REG_RD(pio, regi_pio, rw_dout);
+ dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
+
+#if !MANUAL_ALE_CLE_CONTROL
+ if (ctrl & NAND_ALE) {
+ /* A0 = ALE high */
+ this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
+ regi_pio, rw_io_access1);
+ } else if (ctrl & NAND_CLE) {
+ /* A1 = CLE high */
+ this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
+ regi_pio, rw_io_access2);
+ } else {
+ /* A1 = CLE and A0 = ALE low */
+ this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
+ regi_pio, rw_io_access0);
+ }
+#else
+
+ dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
+ dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
+#endif
+ REG_WR(pio, regi_pio, rw_dout, dout);
+ }
+
+ /* command to chip */
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+
+ local_irq_restore(flags);
+}
+
+/*
+* read device ready pin
+*/
+int crisv32_device_ready(struct mtd_info *mtd)
+{
+ reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
+ return din.rdy;
+}
+
+/*
+ * Main initialization routine
+ */
+struct mtd_info *__init crisv32_nand_flash_probe(void)
+{
+ void __iomem *read_cs;
+ void __iomem *write_cs;
+
+ struct nand_chip *this;
+ int err = 0;
+
+ reg_pio_rw_man_ctrl man_ctrl = {
+ .regf_NCE = regk_pio_yes,
+#if MANUAL_ALE_CLE_CONTROL
+ .regf_ALE = regk_pio_yes,
+ .regf_CLE = regk_pio_yes
+#endif
+ };
+ reg_pio_rw_oe oe = {
+ .regf_NCE = regk_pio_yes,
+#if MANUAL_ALE_CLE_CONTROL
+ .regf_ALE = regk_pio_yes,
+ .regf_CLE = regk_pio_yes
+#endif
+ };
+ reg_pio_rw_dout dout = { .regf_NCE = 1 };
+
+ /* Allocate pio pins to pio */
+ crisv32_pinmux_alloc_fixed(pinmux_pio);
+ /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
+ REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
+ REG_WR(pio, regi_pio, rw_dout, dout);
+ REG_WR(pio, regi_pio, rw_oe, oe);
+
+ /* Allocate memory for MTD device structure and private data */
+ crisv32_mtd = kmalloc(sizeof(struct mtd_info) +
+ sizeof(struct nand_chip), GFP_KERNEL);
+ if (!crisv32_mtd) {
+ printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
+ "device structure.\n");
+ err = -ENOMEM;
+ return NULL;
+ }
+
+ read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
+ rw_io_access0);
+
+ /* Get pointer to private data */
+ this = (struct nand_chip *) (&crisv32_mtd[1]);
+
+ /* Initialize structures */
+ memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
+ memset((char *) this, 0, sizeof(struct nand_chip));
+
+ /* Link the private data with the MTD structure */
+ crisv32_mtd->priv = this;
+
+ /* Set address of NAND IO lines */
+ this->IO_ADDR_R = read_cs;
+ this->IO_ADDR_W = write_cs;
+ this->cmd_ctrl = crisv32_hwcontrol;
+ this->dev_ready = crisv32_device_ready;
+ /* 20 us command delay time */
+ this->chip_delay = 20;
+ this->ecc.mode = NAND_ECC_SOFT;
+
+ /* Enable the following for a flash based bad block table */
+ /* this->options = NAND_USE_FLASH_BBT; */
+
+ /* Scan to find existance of the device */
+ if (nand_scan(crisv32_mtd, 1)) {
+ err = -ENXIO;
+ goto out_mtd;
+ }
+
+ return crisv32_mtd;
+
+out_mtd:
+ kfree(crisv32_mtd);
+ return NULL;
+}
+
--
1.5.3.6.970.gd25430