Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755188Ab2KISX2 (ORCPT ); Fri, 9 Nov 2012 13:23:28 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:56718 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753997Ab2KISXX (ORCPT ); Fri, 9 Nov 2012 13:23:23 -0500 MIME-Version: 1.0 In-Reply-To: References: <000001cdbe47$48f5dbc0$dae19340$%han@samsung.com> From: Bjorn Helgaas Date: Fri, 9 Nov 2012 11:23:00 -0700 Message-ID: Subject: Re: [PATCH] PCI: Fix bit definitions of PCI_EXP_LNKCAP2 register To: Alex Deucher Cc: Jingoo Han , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2540 Lines: 53 On Fri, Nov 9, 2012 at 10:37 AM, Alex Deucher wrote: > On Fri, Nov 9, 2012 at 12:15 PM, Bjorn Helgaas wrote: >> On Thu, Nov 8, 2012 at 11:56 PM, Jingoo Han wrote: >>> According to the PCIe 3.0 spec, PCI_EXP_LNKCAP2_SLS_2_5GB is >>> 1st bit of PCI_EXP_LNKCAP2 register, not 0th bit. So, the bit >>> definition of supported link speed vector should be fixed. >>> >>> Signed-off-by: Jingoo Han >>> --- >>> include/uapi/linux/pci_regs.h | 6 +++--- >>> 1 files changed, 3 insertions(+), 3 deletions(-) >>> >>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >>> index 20ae747..14a3184 100644 >>> --- a/include/uapi/linux/pci_regs.h >>> +++ b/include/uapi/linux/pci_regs.h >>> @@ -544,9 +544,9 @@ >>> #define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ >>> #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ >>> #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ >>> -#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ >>> -#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ >>> -#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ >>> +#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Current Link Speed 2.5GT/s */ >>> +#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Current Link Speed 5.0GT/s */ >>> +#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Current Link Speed 8.0GT/s */ >>> #define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ >>> #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ >>> #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ >> >> I think this patch is correct, per spec sec 7.8.18. If I apply it, I >> think the comments should also be changed to "Supported Link Speed" >> instead of "Current." > > Correct. > >> >> The only in-tree user of these symbols is >> drm_pcie_get_speed_cap_mask(). Dave, can you ack/nack this? I don't >> want to apply this if it's going to break something there. > > The patch is fine and shouldn't break anything. Thanks for checking this out, Alex. I applied this to my pci/misc branch as v3.8 material. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/