Date: Fri, 9 Nov 2012 19:44:09 +0100
From: Thierry Reding <thierry.reding@avionic-design.de>
To: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
        Terje =?utf-8?Q?Bergstr=C3=B6m?= <tbergstrom@nvidia.com>,
        Mark Zhang <markz@nvidia.com>
Subject: Re: [PATCH 0/2] Device tree updates for host1x support
Message-ID: <20121109184409.GB7663@avionic-0098.mockup.avionic-design.de>
References: <1352467202-27903-1-git-send-email-thierry.reding@avionic-design.de>
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On Fri, Nov 09, 2012 at 10:34:41AM -0700, Stephen Warren wrote:
> On 11/09/2012 06:20 AM, Thierry Reding wrote:
> > This set of patches are in preparation for the Tegra DRM driver. They
> > add the necessary nodes to the DTSI files and setup the clocks necessary
> > for host1x and the display controllers to work properly. The AUXDATA
> > table is updated with the entries for the newly added nodes and the PLL
> > frequency tables are extended with some frequencies required to make a
> > few of the more common LVDS panel and HDMI display modes work.
> >=20
> > By default, all output resources (RGB, HDMI, DSI and TVO) are disabled,
> > and individual boards need to enable those that they require.
> >=20
> > Note that there has been talk to replace the frequency tables by an
> > algorithmic computation of the dividers in order to avoid endless
> > additions to these tables. No code has surfaced yet, but eventually this
> > should replace the static tables.
>=20
> This basically looks reasonable.
>=20
> I assume the DT bindings are documented in the tegradrm driver series? I
> haven't looked at that yet.
>=20
> I'd like to see explicit acks for the DT changes from e.g. Terje and
> Mark Zhang, and anyone else involved in previous discussions about them.
>=20
> Could you please split up the patches a little differently? I'd like to s=
ee:
>=20
> 1) Changes to the clock driver
> 2) Changes to add AUXDATA
> 3) Changes to .dts files
>=20
> The reason being that these are logically separate changes. (1) and (2)
> would be applied to the "soc" branch, and (3) to the "dt" branch.

I'll split the patches up some more then.

> Finally, I'd prefer not to rename the match parameters in the clock
> drivers any more; just set up the AUXDATA to match whatever driver names
> the clock driver is expecting. That will reduce churn to the clock
> driver.

I updated the table mainly because the devices were named very
inconsistently. For instance, the output resources and host1x didn't
have the tegra- prefix, but the display controllers did. I still think
there's enough value in having a consistent set of device names, but
this is your tree, so I'll drop those changes and update the AUXDATA
table if that's what you want.

> I really hope soon that Tegra will support DT bindings for
> clocks so we can get rid of the AUXDATA, but unfortunately I haven't
> seen any movement towards this:-(

Oh yes, please. We wouldn't have any of the above problem if we had
proper DT bindings for this. Who needs to be prodded to speed this up?

Thierry

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