Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752491Ab2KLIdz (ORCPT ); Mon, 12 Nov 2012 03:33:55 -0500 Received: from mail-pb0-f46.google.com ([209.85.160.46]:51203 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752359Ab2KLIdx (ORCPT ); Mon, 12 Nov 2012 03:33:53 -0500 From: Huacai Chen To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Fuxin Zhang , Zhangjin Wu , Huacai Chen , Hongliang Tao , Hua Yan Subject: [PATCH V8 02/13] MIPS: Loongson: Add basic Loongson-3 CPU support Date: Mon, 12 Nov 2012 16:32:38 +0800 Message-Id: <1352709169-3481-3-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1352709169-3481-1-git-send-email-chenhc@lemote.com> References: <1352709169-3481-1-git-send-email-chenhc@lemote.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5096 Lines: 169 Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen Signed-off-by: Hongliang Tao Signed-off-by: Hua Yan --- arch/mips/kernel/cpu-probe.c | 14 +++++++--- arch/mips/mm/c-r4k.c | 62 +++++++++++++++++++++++++++++++++++++++++- arch/mips/mm/tlb-r4k.c | 2 +- arch/mips/mm/tlbex.c | 1 + 4 files changed, 73 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index cce3782..ee45efd 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -773,17 +773,23 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) MIPS_CPU_LLSC; c->tlbsize = 64; break; - case PRID_IMP_LOONGSON2: - c->cputype = CPU_LOONGSON2; - __cpu_name[cpu] = "ICT Loongson-2"; - + case PRID_IMP_LOONGSON2: /* Loongson-2/3 have the same PRID_IMP field */ switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_LOONGSON2E: + c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; set_elf_platform(cpu, "loongson2e"); break; case PRID_REV_LOONGSON2F: + c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; set_elf_platform(cpu, "loongson2f"); break; + case PRID_REV_LOONGSON3A: + c->cputype = CPU_LOONGSON3; + __cpu_name[cpu] = "ICT Loongson-3"; + set_elf_platform(cpu, "loongson3a"); + break; } c->isa_level = MIPS_CPU_ISA_III; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 2b61462..d52ffe4 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -971,6 +971,31 @@ static void __cpuinit probe_pcache(void) c->dcache.waybit = 0; break; + case CPU_LOONGSON3: + config1 = read_c0_config1(); + if ((lsize = ((config1 >> 19) & 7))) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + icache_size = c->icache.sets * + c->icache.ways * + c->icache.linesz; + c->icache.waybit = 0; + + if ((lsize = ((config1 >> 10) & 7))) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz = lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + dcache_size = c->dcache.sets * + c->dcache.ways * + c->dcache.linesz; + c->dcache.waybit = 0; + break; + default: if (!(config & MIPS_CONF_M)) panic("Don't know how to probe P-caches on this cpu."); @@ -1191,6 +1216,34 @@ static void __init loongson2_sc_init(void) } #endif +#if defined(CONFIG_CPU_LOONGSON3) +static void __init loongson3_sc_init(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config2, lsize; + + config2 = read_c0_config2(); + if ((lsize = ((config2 >> 4) & 15))) + c->scache.linesz = 2 << lsize; + else + c->scache.linesz = lsize; + c->scache.sets = 64 << ((config2 >> 8) & 15); + c->scache.ways = 1 + (config2 & 15); + + scache_size = c->scache.sets * + c->scache.ways * + c->scache.linesz; + /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ + scache_size *= 4; + c->scache.waybit = 0; + pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + if (scache_size) + c->options |= MIPS_CPU_INCLUSIVE_CACHES; + return; +} +#endif + extern int r5k_sc_init(void); extern int rm7k_sc_init(void); extern int mips_sc_init(void); @@ -1240,11 +1293,18 @@ static void __cpuinit setup_scache(void) #endif return; -#if defined(CONFIG_CPU_LOONGSON2) case CPU_LOONGSON2: +#if defined(CONFIG_CPU_LOONGSON2) loongson2_sc_init(); +#endif return; + + case CPU_LOONGSON3: +#if defined(CONFIG_CPU_LOONGSON3) + loongson3_sc_init(); #endif + return; + case CPU_XLP: /* don't need to worry about L2, fully coherent */ return; diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 4b9b935..6d11c6b 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -50,7 +50,7 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ -#if defined(CONFIG_CPU_LOONGSON2) +#if defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_LOONGSON3) /* * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, * unfortrunately, itlb is not totally transparent to software. diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 2833dcb..2cb4eb6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -550,6 +550,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BMIPS4380: case CPU_BMIPS5000: case CPU_LOONGSON2: + case CPU_LOONGSON3: case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); -- 1.7.7.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/