Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754934Ab2K2XMK (ORCPT ); Thu, 29 Nov 2012 18:12:10 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:33862 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752776Ab2K2XMI convert rfc822-to-8bit (ORCPT ); Thu, 29 Nov 2012 18:12:08 -0500 From: "Kim, Milo" To: Venu Byravarasu CC: Andrew Morton , Samuel Ortiz , "a.zummo@towertech.it" , "swarren@wwwdotorg.org" , Sivaram Nair , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH 2/2] rtc-tps65910: enable RTC power domain on initialization Thread-Topic: [PATCH 2/2] rtc-tps65910: enable RTC power domain on initialization Thread-Index: Ac3ODj+EBtR5lNOFQkugojWkudbjXgAASILgAB0lr6A= Date: Thu, 29 Nov 2012 23:11:37 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [157.87.185.123] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1637 Lines: 46 Hi Venu > > Enabling RTC HW block depends on the default value of TPS65910 > register. > > In some mode, RTC block is disabled by default.(eg. AM3517 > Craneboard) > > In this case, RTC_PWDN(RTC power down) bit should be cleared to > enable > > the RTC HW block. > > From the description of RTC_PWDN bit of DEVCTRL_REG in TPS65910 data > sheet > it is very evident that the default value of RTC_PWDN is 0. According to the datasheet(http://www.ti.com/lit/ds/swcs046q/swcs046q.pdf), the default value RTC_PWDN is 1 which means power down. The default values are loaded from the EEPROM with BOOT_MODE 0,1 pin connection. The RTC is disabled by default when BOOT_MODE = 00. The Craneboard has the BOOT_MODE 00. You may have other EEPROM settings, however the official datasheet shows the RTC block is off by default. Could you check the silicon version number? (0x80 register - JTAGVERNUM_REG) In my case, the read value is 0x01. > Probably on "AM3517 Craneboard", some code is running prior to the RTC > driver > which might be writing 1 on to this bit. IMO you must disable that > write operation > instead of just writing default value into a register. Thank you for your comment. I've read the DEVCTRL register (0x3F) in mfd tps65910 driver as soon as the regmap registration is done, however RTC_PWDN is always 1. That means the RTC is disabled by default. Best Regards, Milo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/