Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937115Ab3DJQbp (ORCPT ); Wed, 10 Apr 2013 12:31:45 -0400 Received: from mail-we0-f171.google.com ([74.125.82.171]:33798 "EHLO mail-we0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936705Ab3DJQbn (ORCPT ); Wed, 10 Apr 2013 12:31:43 -0400 MIME-Version: 1.0 In-Reply-To: <87sj2yzn1a.fsf@xmission.com> References: <20130408224328.GA17641@www.outflux.net> <51634935.9010905@zytor.com> <877gkc596d.fsf@xmission.com> <20130410095716.GF24443@gmail.com> <87sj2yzn1a.fsf@xmission.com> Date: Wed, 10 Apr 2013 09:31:41 -0700 Message-ID: Subject: Re: [PATCH] x86: make IDT read-only From: Eric Northup To: "Eric W. Biederman" Cc: Ingo Molnar , "H. Peter Anvin" , Kees Cook , Ingo Molnar , Linux Kernel Mailing List , Thomas Gleixner , "the arch/x86 maintainers" , Konrad Rzeszutek Wilk , Jeremy Fitzhardinge , Marcelo Tosatti , Alex Shi , Borislav Petkov , Alexander Duyck , Frederic Weisbecker , Steven Rostedt , "Paul E. McKenney" , Xen Devel , lf-virt , "kernel-hardening@lists.openwall.com" , Dan Rosenberg , Julien Tinnes , Will Drewry Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2730 Lines: 63 On Wed, Apr 10, 2013 at 3:40 AM, Eric W. Biederman wrote: > Ingo Molnar writes: > >> * Eric W. Biederman wrote: >> >>> "H. Peter Anvin" writes: >>> >>> > On 04/08/2013 03:43 PM, Kees Cook wrote: >>> >> This makes the IDT unconditionally read-only. This primarily removes >>> >> the IDT from being a target for arbitrary memory write attacks. It has >>> >> an added benefit of also not leaking (via the "sidt" instruction) the >>> >> kernel base offset, if it has been relocated. >>> >> >>> >> Signed-off-by: Kees Cook >>> >> Cc: Eric Northup >>> > >>> > Also, tglx: does this interfere with your per-cpu IDT efforts? >>> >>> Given that we don't change any IDT entries why would anyone want a >>> per-cpu IDT? The cache lines should easily be shared accross all >>> processors. >> >> That's true iif they are cached. >> >> If not then it's a remote DRAM access cache miss for all CPUs except the node that >> holds that memory. >> >>> Or are there some giant NUMA machines that trigger cache misses when accessing >>> the IDT and the penalty for pulling the cache line across the NUMA fabric is >>> prohibitive? >> >> IDT accesses for pure userspace execution are pretty rare. So we are not just >> talking about huge NUMA machines here but about ordinary NUMA machines taking a >> remote cache miss hit for the first IRQ or other IDT-accessing operation they do >> after some cache-intense user-space processing. >> >> It's a small effect, but it exists and improving it would be >> legitimate. > > If the effect is measurable I agree it is a legitimate optimization. At > one point there was a suggestion to make the code in the IDT vectors > differ based on the which interrupt was registed. While that can also > reduce cache misses that can get hairy very quickly, and of course that > would require read-write IDTs. read-write IDT or GDT are fine: map them twice, once read+write, once read-only. Point the GDTR and IDTR at the read-only alias. > > My only practical concern with duplicating the IDT tables per cpu is (a) > there are generic idt handlers that remain unduplicated reducing the > benefit and this is essentially the same optimization as making the > entire kernel text per cpu which last time it was examined was not an > optimization worth making. So I wonder if just a subset of the > optimization is worth making. > > Eric -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/