Message-ID: <516597DB.4020208@zytor.com>
Date: Wed, 10 Apr 2013 09:48:27 -0700
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Eric Northup <digitaleric@google.com>
CC: "Eric W. Biederman" <ebiederm@xmission.com>,
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Subject: Re: [PATCH] x86: make IDT read-only
References: <20130408224328.GA17641@www.outflux.net> <51634935.9010905@zytor.com> <877gkc596d.fsf@xmission.com> <20130410095716.GF24443@gmail.com> <87sj2yzn1a.fsf@xmission.com> <CAG7+5M06h_UEy39OQqdT7Z6r-85q_R9zHHKGO6F2PX2pgT6U9g@mail.gmail.com>
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On 04/10/2013 09:31 AM, Eric Northup wrote:
>>
>> If the effect is measurable I agree it is a legitimate optimization.  At
>> one point there was a suggestion to make the code in the IDT vectors
>> differ based on the which interrupt was registed.  While that can also
>> reduce cache misses that can get hairy very quickly, and of course that
>> would require read-write IDTs.
> 
> read-write IDT or GDT are fine: map them twice, once read+write, once
> read-only.  Point the GDTR and IDTR at the read-only alias.
> 

Well, it is weaker, because if you can discover the pointer to the
writable alias you win.

Now, as has been pointed out the GDT needs to be writable on 32 bits as
a matter of hardware requirement.  However, doing it for 64 bits only is
probably enough of a win.

	-hpa


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