Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933250Ab3DLWzV (ORCPT ); Fri, 12 Apr 2013 18:55:21 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:32788 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753683Ab3DLWzL (ORCPT ); Fri, 12 Apr 2013 18:55:11 -0400 From: Nishanth Menon To: CC: , , , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , Paul Walmsley , Kevin Hilman , Mike Turquette , Nishanth Menon Subject: [PATCH V4 4/6] ARM: dts: AM33XX: add clock nodes for CPU Date: Fri, 12 Apr 2013 17:54:36 -0500 Message-ID: <1365807278-554-5-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1365807278-554-1-git-send-email-nm@ti.com> References: <1365807278-554-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2337 Lines: 66 AM33XX based platforms use dpll_mpu clock. Add same to common dtsi and remove the dummy clock node entry as AM33XX platform supports only device tree based boot. Cc: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Tony Lindgren Signed-off-by: Nishanth Menon --- RFC of this patch was discussed in http://marc.info/?t=136370325600009&r=1&w=2 along with the detailed context as to why this is an intermediate step. previous revisions of cpufreq-cpu0 support do not use this approach. [Probably belongs to Benoit/Tony/Paul tree?] arch/arm/boot/dts/am33xx.dtsi | 7 +++++++ arch/arm/mach-omap2/cclock33xx_data.c | 1 - 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index df62830..3aed044 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -42,6 +42,8 @@ 275000 1125000 >; voltage-tolerance = <2>; /* 2 percentage */ + clocks = <&dpll_mpu>; + clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; @@ -89,6 +91,11 @@ reg = <0x48200000 0x1000>; }; + dpll_mpu: dpll_mpu { + #clock-cells = <0>; + compatible = "ti,omap-clock"; + }; + gpio0: gpio@44e07000 { compatible = "ti,omap4-gpio"; ti,hwmods = "gpio1"; diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 7f091c8..8be6832 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -852,7 +852,6 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), - CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX), CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/