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Date: Tue, 24 Sep 2002 10:28:43 -0700
From: Dave Olien <dmo@osdl.org>
To: davidm@hpl.hp.com
Cc: "David S. Miller" <davem@redhat.com>, phillips@arcor.de,
       davidm@napali.hpl.hp.com, axboe@suse.de, _deepfire@mail.ru,
       linux-kernel@vger.kernel.org
Subject: Re: DAC960 in 2.5.38, with new changes
Message-ID: <20020924102843.C17658@acpi.pdx.osdl.net>
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Hmm, interesting.  A big part of what I'm doing to the driver
right now is plugging in calls to the PCI DMA interfaces.
So unless the underlying implementation is aware of these
platform limitations and "doing the right thing", I'm adding
a bunch of bounce buffer activity for many ia64 platforms.
That would be too bad.

I distantly recall that the cost of doing PCI DAC isn't really
that high for bursty transfers, because the bus is able to
group packets of data cycles behind one initial address cycle.
But it's been many years since I last looked at this and I could have
this wrong.


On Tue, Sep 24, 2002 at 10:11:26AM -0700, David Mosberger wrote:
> >>>>> On Tue, 24 Sep 2002 09:54:56 -0700, Dave Olien <dmo@osdl.org> said:
> 
>   Dave> According to the Documentation/DMA-mapping.txt file, the new
>   Dave> DMA mapping interfaces should allow all PCI transfers to use
>   Dave> 32-bit DMA addresses. Controllers on the PCI bus should never
>   Dave> need to use DAC PCI transfers.  Based on this, writel() should
>   Dave> work even on ia64.
> 
> Warning: there is a big difference between *can* and *want*.  On ia64
> machines with an Intel chipset, the PCI DMA interface is implemented
> via bounce buffers, so it will be *much* slower than DAC.  For this
> reason, it is preferable on ia64 to use DAC where possible (and just
> in case Dave Miller starts asking about this: yes, the hp zx1 chipset
> for Itanium 2 does have a hardware I/O TLB... ;-).
> 
> 	--david
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