Date: Tue, 23 Apr 2013 11:02:08 +0200
From: Thierry Reding <thierry.reding@avionic-design.de>
To: Axel Lin <axel.lin@ingics.com>
Cc: Alexandre Pereira da Silva <aletes.xgr@gmail.com>,
        Roland Stigge <stigge@antcom.de>, linux-kernel@vger.kernel.org
Subject: Re: [RESEND][PATCH RFT 1/2] pwm: lpc32xx: Properly set PWM_ENABLE
 bit in lpc32xx_pwm_[enable|disable]
Message-ID: <20130423090207.GA29222@avionic-0098.mockup.avionic-design.de>
References: <1366696891.28314.1.camel@phoenix>
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On Tue, Apr 23, 2013 at 02:01:31PM +0800, Axel Lin wrote:
> According to the LPC32x0 User Manual [1]:
>=20
> For both PWM1 and PWM2 Control Registers:
> BIT 31:
> This bit gates the PWM_CLK signal and enables the external output pin
> to the PWM_PIN_STATE logical level.
>=20
> 0 =3D PWM disabled. (Default)
> 1 =3D PWM enabled
>=20
> So in lpc32xx_pwm_enable(), we should set PWM_ENABLE bit.
> In lpc32xx_pwm_disable(), we should just clear PWM_ENABLE bit rather than
> write 0 to the register which will also clear PWMx_RELOADV and PWMx_DUTY =
bits.
>=20
> [1] http://www.nxp.com/documents/user_manual/UM10326.pdf
>=20
> Signed-off-by: Axel Lin <axel.lin@ingics.com>
> ---
> Hi,
> I don't have this hardware handy so I'd appreciate if someone can test th=
is
> patch serial.
>=20
> This patch serial was sent on https://lkml.org/lkml/2013/3/30/104
> Seems no feedback so far.
> So I just try again, maybe someone can help testing it.
> Thanks,
> Axel

Both patches applied with Roland's Tested-by. Thanks.

Thierry

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