Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753515Ab3EGWZp (ORCPT ); Tue, 7 May 2013 18:25:45 -0400 Received: from mail-lb0-f178.google.com ([209.85.217.178]:33718 "EHLO mail-lb0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750796Ab3EGWZn (ORCPT ); Tue, 7 May 2013 18:25:43 -0400 MIME-Version: 1.0 In-Reply-To: References: <337833384.57445.1361860509194.JavaMail.mail@webmail08> <569718148.80620.1361906088301.JavaMail.mail@webmail13> <771333906.75854.1367057440028.JavaMail.mail@webmail08> <518097B8.4020402@gmail.com> <384171828.66802.1367942365492.JavaMail.mail@webmail05> Date: Wed, 8 May 2013 00:25:41 +0200 Message-ID: Subject: Re: Abysmal HDD/USB write speed after sleep on a UEFI system From: Patrik Jakobsson To: Bjorn Helgaas Cc: Robert Hancock , "Artem S. Tashkinov" , Alan Stern , Linus Torvalds , linux-kernel , "linux-pci@vger.kernel.org" , "Rafael J. Wysocki" , Phillip Susi Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2489 Lines: 50 On Wed, May 8, 2013 at 12:02 AM, Bjorn Helgaas wrote: > On Tue, May 7, 2013 at 2:48 PM, Patrik Jakobsson > wrote: >> On Tue, May 7, 2013 at 10:20 PM, Bjorn Helgaas wrote: >>>> I'm not sure if reading /proc/mtrr actually reads the registers out of >>>> the CPU each time, or whether we just return the cached values we read >>>> out during initial boot-up. If the latter, then this output isn't >>>> really useful as there's no guarantee the values are still intact. >>> >>> Good point. From what I can tell, on Artem's system with "CPU0: >>> Intel(R) Core(TM) i5-2500 CPU @ 3.30GHz," we would be using >>> generic_mtrr_ops, and generic_get_mtrr() appears to read from the >>> MSRs, so I think it should be useful. >> >> FWIW, that motherboard suffers from a PCI to PCIE bridge problem. It might >> have been fixed by bios upgrades by now but not sure. >> >> It might also suffer (depending on the revision) from the Sandy bridge SATA >> issue. So if affected, SATA controller is a ticking bomb. >> >> I have a P8H67-V motherboard but I haven't seen any suspend related issues. >> >> If this is totally unrelated I'm sorry for wasting your time. Just thought it >> might be good to know. > > Thanks for chiming in. I'm not familiar with either of the issues you > mentioned. Do you have any references where I could read up on them? I think this is the official statement from Intel on the SATA issue: http://newsroom.intel.com/community/intel_newsroom/blog/2011/01/31/intel-identifies-chipset-design-error-implementing-solution And here's a link to a discussion about the PCIe-to-PCI bridge stuff: https://lkml.org/lkml/2012/1/30/216 > Artem's system has a PCIe-to-PCI bridge (not a PCI-to-PCIe bridge) at > 05:00.0, but it leads to [bus 06] and there's nothing on bus 06, so I > don't think that's the problem. I meant what you said ;) and yes, it seems unrelated. Both my P8H67 and a P8P67 I've built behave nicely if nothing is connected. > And the issue affects both USB and a hard drive, so I suspect it's > more than just SATA. Artem, did you identify the PCI devices leading > to your USB and hard drive? I can't remember if I've actually seen > that. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/