Date: Wed, 15 May 2013 08:46:04 +0400
From: Mark Brown <broonie@kernel.org>
To: Philip Balister <philip@balister.org>
Cc: Mike Turquette <mturquette@linaro.org>,
        =?iso-8859-1?Q?S=F6ren?= Brinkmann <soren.brinkmann@xilinx.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
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MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha1;
	protocol="application/pgp-signature"; boundary="CE+1k2dSO48ffgeK"
Content-Disposition: inline
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Subject: Re: [PATCH RFC] clk: Introduce userspace clock driver
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Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline

On Tue, May 14, 2013 at 02:09:47PM -0400, Philip Balister wrote:

> First of all, the driver that loads the bitstream into the fpga
> fabric does not know ANYTHING about what the bitstream does. So it
> cannot do any setup based on the contents of the file that is
> loaded. (And this can also be loaded during the SoC bootup,
> bypassing this driver completely)

This is a problem that is going to need to be fixed - there will be some
things going on the FPGAs that do need drivers and so there needs to be
some way to instantiate a driver for a FPGA image.  Things like adding
extra DT blobs along with the FPGA image have been talked about

> Second, there are four clocks that feed the FPGA fabric. We will
> want to set these clocks from user space somehow. It is perfectly
> valid to use a uio driver to interface with logic in the fpga. If we
> take the approach of using such general purpose techniques to
> interface with fpga logic, we must have ways for the user to control
> the fpga clocks.

Right, and if the specific device is being controlled by UIO then having
UIO create some clocks makes sense but then that should be integrated
into the UIO instantiation rather than done as a separate thing.

--CE+1k2dSO48ffgeK
Content-Type: application/pgp-signature; name="signature.asc"
Content-Description: Digital signature

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)

iQIcBAEBAgAGBQJRkxMJAAoJELSic+t+oim9TloP/09KWTifHEusxdNgDH2WZOou
K0K6gLkl1uxOYzFteuewoM4m5kQMgmlZtdkdgZKCgiAq9RpBpwxPBtsXJns6PiDW
4rbFyS8XZ0lBHryLJ2g1ghrN8Im2mFLF2u722yQOVRrOalFmpoPhZB6LRcJmP1ts
mT037sdwCz5OWV397nYusnzoZKbCBwf363yw3hcgs0f0dKty16lEwJIzVcl0ba/T
+2mfdHoxL2KjwqsJgs+2bxlVGzXKmBXGEbB4Pbp0yTmQLqwXFxOeMvJR1fB2ZUAd
wbEQ326U+7YS5+waik6XUz84YUBFDHVzw0u6b7hK3bfCBoA6Od9QvARSrogvjLs9
v+TZBFnnn3VZ1f5xuQo5zv5j9bpZ8PtkY+zAtk4xPZ5mwBA/sWm94xJWtlaYQ0rF
iB83EXg7b7bQVr4KXQ8LR3ZXXaYdQNCPipx8RgPR+hdDMG47B/tR6JxmoE4hrKSN
b9Tz07+EnyZv1LExcZsF0/P+J/QzVyGQgf4/ekFZDAPHq6NgxZom30w2rDiYqeOQ
RTgryikXtRDSOiUsDQ6ZYpCgnB94w6lJe1d12q0WJu/RiF9kSAQd6PJ0htku7jqH
mq3L48xbcXhiU6i2FwsOxfUKRR3vjSF6BQ7qKZ2/STAPrufxqVOY5FzvmhGCdl+/
wMhevKQU6hCbYUBZEICe
=zteZ
-----END PGP SIGNATURE-----

--CE+1k2dSO48ffgeK--
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