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Date: Tue, 1 Oct 2002 12:06:28 +0100
From: Dave Jones <davej@codemonkey.org.uk>
To: Alexander Hoogerhuis <alexh@ihatent.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>, linux-kernel@vger.kernel.org,
       marcelo@conectiva.com.br
Subject: Re: CPU/cache detection wrong
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On Tue, Oct 01, 2002 at 09:21:26AM +0200, Alexander Hoogerhuis wrote:
 > Dave Jones <davej@codemonkey.org.uk> writes:
 > 
 > > On Mon, Sep 30, 2002 at 07:43:16PM +0200, Alexander Hoogerhuis wrote:
 > > 
 > >  > PU: Before vendor init, caps: 3febf9ff 00000000 00000000, vendor = 0
 > >  > Cache info byte: 50
 > > 
 > > Instruction TLB (ignored)
 > > 
 > >  > Cache info byte: 5B
 > > 
 > > Data TLB (ignored)
 > > 
 > >  > Cache info byte: 66
 > > 
 > > 8K L1 data cache
 > >  
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > >  > Cache info byte: 00
 > > 
 > > Null
 > >  
 > >  > Cache info byte: 40
 > > 
 > > No 3rd level cache.
 > > 
 > >  > Cache info byte: 70
 > > 
 > > 12K-uops trace cache
 > > 
 > >  > Cache info byte: 7B
 > > 
 > > 512K L2 cache
 > > 
 > >  > Cache info byte: 00
 > > 
 > > Null.
 > >  
 > >  > CPU: L1 I cache: 0K, L1 D cache: 8K
 > >  > CPU: L2 cache: 512K
 > > 
 > 
 > Here we go:
 > 
 > CPU: Trace cache: 12K uops, L1 D cache: 8K
 > CPU: L2 cache: 512K
 > 
 > But my BIOS still say I should have 8Kb/8Kb I/D L1 cache... oh
 > well. I'm sure Alan Cox would just write it up as marketing, since
 > thats about how reliable a BIOS is :)

Hmm, can a P4 have a trace cache AND an L1 I cache ?
I thought they were exclusive, which is why the code
doesn't take this into account. Easily fixed if so though..

		Dave

-- 
| Dave Jones.        http://www.codemonkey.org.uk
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