Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758325Ab3E3V34 (ORCPT ); Thu, 30 May 2013 17:29:56 -0400 Received: from mail-wg0-f50.google.com ([74.125.82.50]:53717 "EHLO mail-wg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757756Ab3E3V3t (ORCPT ); Thu, 30 May 2013 17:29:49 -0400 From: Grant Likely Subject: Re: [RFC PATCHv4 6/6] irqchip: TI-Nspire irqchip support To: Daniel Tang , linux-arm-kernel@lists.infradead.org, "linux@arm.linux.org.uk ARM Linux" Cc: Daniel Tang , Linus Walleij , Arnd Bergmann , "fabian@ritter-vogt.de Vogt" , Lionel Debroux , linux-kernel@vger.kernel.org, Thomas Gleixner In-Reply-To: <1369480087-24786-7-git-send-email-dt.tangr@gmail.com> References: <1369480087-24786-1-git-send-email-dt.tangr@gmail.com> <1369480087-24786-7-git-send-email-dt.tangr@gmail.com> Date: Thu, 30 May 2013 22:29:45 +0100 Message-Id: <20130530212945.C026C3E0A90@localhost> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1766 Lines: 68 On Sat, 25 May 2013 21:08:07 +1000, Daniel Tang wrote: > Add support for the interrupt controller on TI-Nspires. > > Signed-off-by: Daniel Tang [...] > +static void nspire_irq_ack(struct irq_data *irqd) > +{ > + void __iomem *base = irq_io_base; > + > + if (irqd->hwirq < FIQ_START) > + base += IO_IRQ_BASE; > + else > + base += IO_FIQ_BASE; > + > + readl(base + IO_RESET); > +} > + > +static void nspire_irq_unmask(struct irq_data *irqd) > +{ > + void __iomem *base = irq_io_base; > + int irqnr = irqd->hwirq; > + > + if (irqnr < FIQ_START) { > + base += IO_IRQ_BASE; > + } else { > + irqnr -= MAX_INTRS; > + base += IO_FIQ_BASE; > + } > + > + writel((1< +} > + > +static void nspire_irq_mask(struct irq_data *irqd) > +{ > + void __iomem *base = irq_io_base; > + int irqnr = irqd->hwirq; > + > + if (irqnr < FIQ_START) { > + base += IO_IRQ_BASE; > + } else { > + irqnr -= FIQ_START; > + base += IO_FIQ_BASE; > + } > + > + writel((1< +} > + > +static struct irq_chip nspire_irq_chip = { > + .name = "nspire_irq", > + .irq_ack = nspire_irq_ack, > + .irq_mask = nspire_irq_mask, > + .irq_unmask = nspire_irq_unmask, > +}; Should be using irq_generic_chip here. There is no need to reimplement the above ack, mask and unmask functions. You should find the irq_alloc_domain_generic_chips() patch in the tip tree irq/for-arm branch. That branch is staged for merging in v3.11 Otherwise the patch looks good. g. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/