Date: Mon, 10 Jun 2013 22:36:42 +0200
From: Thierry Reding <thierry.reding@gmail.com>
To: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: gregkh@linuxfoundation.org, linux-tegra@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] memory: tegra20-mc: Fix hang in IRQ handler.
Message-ID: <20130610203641.GA26036@mithrandir>
References: <1370855624-30564-1-git-send-email-ttynkkynen@nvidia.com>
 <1370855624-30564-2-git-send-email-ttynkkynen@nvidia.com>
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On Mon, Jun 10, 2013 at 12:13:43PM +0300, Tuomas Tynkkynen wrote:
> In Tegra20 memory controller any MC interrupt would cause an
> infinite loop in the IRQ handler.
>=20
> Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
> ---
>  drivers/memory/tegra20-mc.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>=20
> diff --git a/drivers/memory/tegra20-mc.c b/drivers/memory/tegra20-mc.c
> index 2ca5f28..bd5a553 100644
> --- a/drivers/memory/tegra20-mc.c
> +++ b/drivers/memory/tegra20-mc.c
> @@ -193,8 +193,11 @@ static irqreturn_t tegra20_mc_isr(int irq, void *dat=
a)
>  	mask &=3D stat;
>  	if (!mask)
>  		return IRQ_NONE;
> -	while ((bit =3D ffs(mask)) !=3D 0)
> +	while ((bit =3D ffs(mask)) !=3D 0) {
>  		tegra20_mc_decode(mc, bit - 1);
> +		mask &=3D BIT(bit);

Shouldn't this be "mask &=3D ~BIT(bit);"? The intent of the code is to
clear the bit which was handled by the loop body, right? The above
clears all other bits instead.

Thierry

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