Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754620Ab3FKKl2 (ORCPT ); Tue, 11 Jun 2013 06:41:28 -0400 Received: from hqemgate03.nvidia.com ([216.228.121.140]:2124 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754568Ab3FKKl0 convert rfc822-to-8bit (ORCPT ); Tue, 11 Jun 2013 06:41:26 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 11 Jun 2013 03:40:59 -0700 From: Jay Agarwal To: "'Thierry Reding'" CC: Stephen Warren , "linux@arm.linux.org.uk" , "bhelgaas@google.com" , Laxman Dewangan , "olof@lixom.net" , Hiroshi Doyu , Prashant Gaikwad , "mturquette@linaro.org" , Peter De Schrijver , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , Juha Tukkinen , Krishna Thota Date: Tue, 11 Jun 2013 16:10:43 +0530 Subject: RE: [PATCH V3 2/4] ARM: tegra: pcie: Add tegra3 support Thread-Topic: [PATCH V3 2/4] ARM: tegra: pcie: Add tegra3 support Thread-Index: Ac5mjL53g9Ui0MOBQVGHGwSqPjuxWAAAE55Q Message-ID: References: <1370372252-4332-1-git-send-email-jagarwal@nvidia.com> <1370372252-4332-2-git-send-email-jagarwal@nvidia.com> <51AE3D3B.6080102@wwwdotorg.org> <20130610195028.GB25859@mithrandir> <20130611101610.GB932@manwe> In-Reply-To: <20130611101610.GB932@manwe> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1036 Lines: 20 > > I have mentioned it in description as -> "Corrected logic in read/write > config space to display right device number on bus 0" > > > > > Device 0:00.0 is usually the root complex, and device 0:01.0, 0:02.0 > > > etc are the root ports. The change proposed above makes 0:00.0 the > > > first root port, therefore breaking what systems usually expect. > > > > > I was seeing root port 2 in cardhu being enumerated as pci_bus 0000:03, > which I thought should be pci_bus 0000:02, so made this change. > > Yes, that's done on purpose to mirror what a typical PCI tree looks like, as I > already explained. So unless this fixes a real bug I'll just drop it while > applying. Please apply V4 patch instead which does not contain this change along with taking care of other review comments. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/