Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753659Ab3FKNai (ORCPT ); Tue, 11 Jun 2013 09:30:38 -0400 Received: from www.linutronix.de ([62.245.132.108]:34326 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751899Ab3FKNah (ORCPT ); Tue, 11 Jun 2013 09:30:37 -0400 Date: Tue, 11 Jun 2013 15:30:26 +0200 (CEST) From: Thomas Gleixner To: Sebastian Hesselbarth cc: Grant Likely , Rob Herring , Rob Landley , John Stultz , Russell King , Jason Cooper , Andrew Lunn , Thomas Petazzoni , Gregory Clement , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/6] irqchip: add support for Marvell Orion SoCs In-Reply-To: Message-ID: References: <1370536034-23956-1-git-send-email-sebastian.hesselbarth@gmail.com> <1370536034-23956-2-git-send-email-sebastian.hesselbarth@gmail.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1209 Lines: 33 On Tue, 11 Jun 2013, Thomas Gleixner wrote: > On Thu, 6 Jun 2013, Sebastian Hesselbarth wrote: > > > This patch adds an irqchip driver for the main interrupt controller found > > on Marvell Orion SoCs (Kirkwood, Dove, Orion5x, Discovery Innovation). > > Corresponding device tree documentation is also added. > > > > Signed-off-by: Sebastian Hesselbarth > > Reviewed-by: Thomas Gleixner Second thoughts: >+static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc) >+{ >+ struct irq_domain *d = irq_get_handler_data(irq); >+ struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq); >+ u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & >+ gc->mask_cache; In init you map the first irq of that chip and install the chain handler for it. Now if that first irq fires, isn't that set in the cause register as well? And what acks that first irq? Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/