Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935685Ab3FUHWF (ORCPT ); Fri, 21 Jun 2013 03:22:05 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:41750 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932206Ab3FUHWA (ORCPT ); Fri, 21 Jun 2013 03:22:00 -0400 X-AuditID: cbfee68e-b7f276d000002279-ee-51c3ff164c9d From: Jingoo Han To: "'Kukjin Kim'" , "'Bjorn Helgaas'" Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, "'Grant Likely'" , "'Andrew Murray'" , "'Thomas Petazzoni'" , "'Thierry Reding'" , "'Jason Gunthorpe'" , Arnd Bergmann , "'Surendranath Gurivireddy Balla'" , "'Siva Reddy Kallam'" , "'Thomas Abraham'" , "'Tomasz Figa'" , "'Pratyush Anand'" , "'Mohit KUMAR'" , Jingoo Han Subject: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC Date: Fri, 21 Jun 2013 16:21:57 +0900 Message-id: <003901ce6e50$03d039a0$0b70ace0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Outlook 14.0 Thread-index: Ac5uT90LHqWwUhcTQLCaT7R8bNm9Xw== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMKsWRmVeSWpSXmKPExsVy+t8zY12x/4cDDRbfU7Jo/r+d1eLvpGPs FkuaMixeHtK0ODD7IavFqzMb2SwuL7zEavH9hqlF74KrbBabHl9jtbi8aw6bxdl5x9ksZpzf x2SxceovRov2S8oWK5q2Mlosvric2WL9jNcsFrtXLmGxODZjCaPF0wdNTA6iHmvmrWH0+P1r EqNH35SrbB5PNl1k9FiwqdTjzrU9bB6bl9R7nJ+xkNHj+45eoIItqxg9fr7U8Xj6Yy+zx+dN cgG8UVw2Kak5mWWpRfp2CVwZxz49YyxY0MdYcfbVVeYGxjcpXYwcHBICJhJP+7O7GDmBTDGJ C/fWs3UxcnEICSxjlNgzbzYbRMJE4kfvLnaIxCJGiR1nN7FAOL8YJU51nmEHqWITUJP48uUw mC0i4C9x7WorWBGzQBubxPpnH8ESwgIOEruO9zCD2CwCqhLTJx9mAbF5BSwlNs/4yQRhC0r8 mHwPLM4soCWxfudxJghbXmLzmrfMECcpAF3xmhFimZ7E/v97mCFqRCT2vXjHCLJYQuAJh8Sf G3tYIJYJSHybfIgF4mdZiU0HoOZIShxccYNlAqPYLCSrZyFZPQvJ6llIVixgZFnFKJpakFxQ nJReZKRXnJhbXJqXrpecn7uJEZJg+nYw3jxgfYgxGWj9RGYp0eR8YILKK4k3NDYzsjA1MTU2 Mrc0I01YSZxXrcU6UEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVANj1fLlS04/5bh+M3T/X93T n85s2BzlfuiSjofY8y0zf+r6H3pgGx+x848lX+HX5T90e5ZfaJSozDJe0XPCyCtjU++RH4F+ J675vdo5UWftTpXUx3d0r749tPvcEf399212WvZlu7FoCcd/VJxpvfHbf/7jkebLJyhfqpZs uGEdFmzTO+VY77S7vUosxRmJhlrMRcWJAMZmMj5GAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIJsWRmVeSWpSXmKPExsVy+t9jAV2x/4cDDX5dlLRo/r+d1eLvpGPs FkuaMixeHtK0ODD7IavFqzMb2SwuL7zEavH9hqlF74KrbBabHl9jtbi8aw6bxdl5x9ksZpzf x2SxceovRov2S8oWK5q2Mlosvric2WL9jNcsFrtXLmGxODZjCaPF0wdNTA6iHmvmrWH0+P1r EqNH35SrbB5PNl1k9FiwqdTjzrU9bB6bl9R7nJ+xkNHj+45eoIItqxg9fr7U8Xj6Yy+zx+dN cgG8UQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlA 7yoplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCesYM459esZYsKCPseLsq6vM DYxvUroYOTkkBEwkfvTuYoewxSQu3FvP1sXIxSEksIhRYsfZTSwQzi9GiVOdZ8Cq2ATUJL58 OQxmiwj4S1y72gpWxCzQxiax/tlHsISwgIPEruM9zCA2i4CqxPTJh1lAbF4BS4nNM34yQdiC Ej8m3wOLMwtoSazfeZwJwpaX2LzmLTPESQpAV7xmhFimJ7H//x5miBoRiX0v3jFOYBSYhWTU LCSjZiEZNQtJywJGllWMoqkFyQXFSem5RnrFibnFpXnpesn5uZsYwQnsmfQOxlUNFocYBTgY lXh4A5QOBwqxJpYVV+YeYpTgYFYS4Q2+AxTiTUmsrEotyo8vKs1JLT7EmAz06URmKdHkfGBy zSuJNzQ2MTOyNDKzMDIxNydNWEmc92CrdaCQQHpiSWp2ampBahHMFiYOTqkGxrpM1eMPfjt4 X13HUm/w2VJMNaAtK3bR8+D/Xzz09004mlYg8sCD53XdT6XSV6tO6Ynv6g248F521tppfj+M 6+5tn3ZHoKrtpr2TLs+itRYLdxWlH7FRcfjG2Ga2aWV29eWruvKBW80k2peqvE+rWG7auY2p WmOdhrRHgebLR+JTvxUYX17go8RSnJFoqMVcVJwIAHdx/e+kAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 18157 Lines: 301 Hi, This series of patches introduces PCIe support for Samsung Exynos5440, and is based on the latest 'linux-next' tree (20130620). These patches was tested with Intel e1000e LAN card on Exynos5440. This PATCH v10 follows: * PATCH v9, sent on June, 21st 2013 * PATCH v8, sent on June, 20th 2013 * PATCH v7, sent on June, 20th 2013 * PATCH v6, sent on June, 20th 2013 * PATCH v5, sent on June, 13th 2013 * PATCH v4, sent on June, 12th 2013 * PATCH v3, sent on June, 6th 2013 * PATCH v2, sent on March, 23rd 2013 * PATCH v1, sent on March, 4th 2013 Changes between v9 and v10: * Changed the file name from 'pci-designware.c' to 'pcie-designware.c' guided by Pratyush Anand, because synopsis pcie and pci controllers are different. * Fixed the typos of document, reported by Sachin Kamat. Changes between v8 and v9: * Changed the file name from 'exynos-pcie.txt' to 'designware-pcie.txt'. * Added 'snps,dw-pcie' string to compatible property. Changes between v7 and v8: * Changed the file name from 'pci-exynos.c' to 'pci-designware.c', and added a generic string for compatible property to exynos-pcie.txt * Moved pci_add_resource_offset() for I/O space to the 'if' clause * Added Arnd's Acked-by Changes between v6 and v7: * Split ARM DT patch to two patches * Fixed node naming * Added Arnd's Acked-by Changes between v5 and v6: * Replaced phys_addr_t with u64 for physical addresses of regions * Removed unnecessary inbound functions * Added handling of io_offset, mem_offset as Arnd Bergmann guided * Fixed calculating 'io' resource * Removed module_exit() in order not to allow module unload Changes between v4 and v5: * Used gpio binding in DT * Increased the size of MEM region to 512 MB including CFG and IO regions in DT * Reduced the size of CFG region to 4096 byte in DT * Used the size of MEM region instead of hard-coded in_mem_size * Fixed exynos_pcie_prog_viewport_{mem/io}_{outbound/inbound} functions to use both translated addresses and untranslated addresses * Replaced pci_add_resource_offset() with pci_add_resource() * Added values from the DT individually to io_base, mem_base Changes between v3 and v4: * Added support for multi domains as reviewed by Jason Gunthorpe, and Arnd Bergmann. * Fixed both MEM space and I/O space in DT. * Removed redundant physical addresses from struct pcie_port, added devm_ioremap_resource() to make add_pcie_port() simpler. * Added clock names and clock enable/disable. Changes between v2 and v3: * Rebased on the top of 3.10-rc4 * Updated names of PCIe PHY registers Changes between v1 and v2: * Moved Exynos PCIe driver from arch/arm to drivers/pci/host. * Added DT properties of PCI DT standard. Here is the lspci -vv output. 0000:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <2us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [148 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 0000:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection Subsystem: Intel Corporation Gigabit CT Desktop Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <2us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [148 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 0001:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection Subsystem: Intel Corporation Gigabit CT Desktop Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-