Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754105Ab3F0Sdx (ORCPT ); Thu, 27 Jun 2013 14:33:53 -0400 Received: from caramon.arm.linux.org.uk ([78.32.30.218]:46729 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753671Ab3F0Sdw (ORCPT ); Thu, 27 Jun 2013 14:33:52 -0400 Date: Thu, 27 Jun 2013 19:32:22 +0100 From: Russell King - ARM Linux To: James Bottomley Cc: Grant Likely , Matthew Garrett , linux-efi@vger.kernel.org, Stephen Warren , "linux-doc@vger.kernel.org" , Linux Kernel Mailing List , Leif Lindholm , Matt Fleming , "patches@linaro.org" , Thomas Gleixner , "H. Peter Anvin" , matt.fleming@intel.com, "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH 1/4] Documentation: arm: [U]EFI runtime services Message-ID: <20130627183222.GE4283@n2100.arm.linux.org.uk> References: <51CA2B03.4080106@wwwdotorg.org> <20130626135311.GA9078@rocoto.smurfnet.nu> <20130626135933.GQ22026@console-pimps.org> <1372257499.2168.5.camel@dabdike> <20130627013219.GA346@srcf.ucam.org> <1372314821.557.33.camel@dabdike> <1372345486.2522.23.camel@dabdike> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1372345486.2522.23.camel@dabdike> User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1097 Lines: 20 On Thu, Jun 27, 2013 at 08:04:46AM -0700, James Bottomley wrote: > That's what the x86_64 proposal from Borislav Petkov does. We alter the > page tables before calling into the UEFI hooks to make sure both the > physical and virtual addresses work. Your problem on ARM with this > approach is that you're a VI platform, not a PI platform like intel, so Let me correct that. Historically, ARM has had virtual indexed caches, and some of its caches still are (eg, the instruction cache). Some data caches might still be technically indexed by virtual address but as the virtual index uses the address bits below the page size, it's equivalent to a physically indexed cache. >From ARMv7, practially all data caches now do not suffer from aliasing with themselves. We do still suffer from data <-> instruction, and cache <-> dma incoherence though. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/