Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755587Ab3GOUzV (ORCPT ); Mon, 15 Jul 2013 16:55:21 -0400 Received: from mga02.intel.com ([134.134.136.20]:34970 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754787Ab3GOUzS (ORCPT ); Mon, 15 Jul 2013 16:55:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.89,671,1367996400"; d="scan'208";a="346060853" Message-ID: <1373921717.3475.203.camel@envy.home> Subject: Re: [PATCH 3/3] pch_gbe: Add MinnowBoard support From: Darren Hart To: Linux Kernel Mailing List Cc: "David S. Miller" , "H. Peter Anvin" , Peter Waskiewicz , Andy Shevchenko , netdev@vger.kernel.org, stable@vger.kernel.org Date: Mon, 15 Jul 2013 13:55:17 -0700 In-Reply-To: References: <1373677087-7747-1-git-send-email-dvhart@linux.intel.com> Organization: Intel Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.8.3 (3.8.3-2.fc19) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1930 Lines: 47 On Fri, 2013-07-12 at 17:58 -0700, Darren Hart wrote: > The MinnowBoard uses an AR803x PHY with the PCH GBE which requires > special handling. Use the MinnowBoard PCI Subsystem ID to detect this > and add a pci_device_id.driver_data structure and functions to handle > platform setup. > > The AR803x does not implement the RGMII 2ns TX clock delay in the trace > routing nor via strapping. Add a detection method for the board and the > PHY and enable the TX clock delay via the registers. > > This PHY will hibernate without link for 10 seconds. Ensure the PHY is > awake for probe and then disable hibernation. A future improvement would > be to convert pch_gbe to using PHYLIB and making sure we can wake the > PHY at the necessary times rather than permanently disabling it. > > Signed-off-by: Darren Hart > Cc: "David S. Miller" > Cc: "H. Peter Anvin" > Cc: Peter Waskiewicz > Cc: Andy Shevchenko > Cc: netdev@vger.kernel.org ... > @@ -277,4 +286,93 @@ void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw) > pch_gbe_phy_read_reg_miic(hw, PHY_PHYSP_CONTROL, &mii_reg); > mii_reg |= PHYSP_CTRL_ASSERT_CRS_TX; > pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, mii_reg); > + > + /* Setup a TX clock delay on certain platforms */ > + if (adapter->pdata->phy_tx_clk_delay) This is missing an adapter->pdata !NULL test. Fixed in V3. Holding off a bit more on that in case Dave M. has anything he wants to see changed in the next revision. -- Darren Hart Intel Open Source Technology Center Yocto Project - Technical Lead - Linux Kernel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/