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From: <hongbo.zhang@freescale.com>
To: <vinod.koul@intel.com>, <djbw@fb.com>, <leoli@freescale.com>,
        <scottwood@freescale.com>, <linuxppc-dev@lists.ozlabs.org>
CC: <devicetree-discuss@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
        <vakul@freescale.com>, Hongbo Zhang <hongbo.zhang@freescale.com>
Subject: [PATCH v4 1/3] DMA: Freescale: revise device tree binding document
Date: Mon, 22 Jul 2013 13:55:38 +0800
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From: Hongbo Zhang <hongbo.zhang@freescale.com>

This updates the discription of each type of DMA controller and its channels,
it is preparation for adding another new DMA controller binding, also fixes
some defects of indent for text alignment at the same time.

Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
---
 .../devicetree/bindings/powerpc/fsl/dma.txt        |   56 +++++++++++---------
 1 file changed, 30 insertions(+), 26 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
index 2a4b4bc..0650171 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
@@ -1,33 +1,33 @@
-* Freescale 83xx DMA Controller
+* Freescale DMA Controllers
 
-Freescale PowerPC 83xx have on chip general purpose DMA controllers.
+** Freescale ELO DMA Controller
+   This is a little-endian DMA controller.
+   Used in Freescale PowerPC 83xx series, such as:
+   mpc8313, mpc8315, mpc8323, mpc8347, mpc8349, mpc8360, mpc8377, mpc8378, mpc8379.
 
 Required properties:
 
 - compatible        : compatible list, contains 2 entries, first is
-		 "fsl,CHIP-dma", where CHIP is the processor
-		 (mpc8349, mpc8360, etc.) and the second is
-		 "fsl,elo-dma"
+                      "fsl,CHIP-dma", where CHIP is the processor
+                      and the second is "fsl,elo-dma"
 - reg               : <registers mapping for DMA general status reg>
-- ranges		: Should be defined as specified in 1) to describe the
-		  DMA controller channels.
+- ranges            : physical address range of DMA controller channels
 - cell-index        : controller index.  0 for controller @ 0x8100
 - interrupts        : <interrupt mapping for DMA IRQ>
 - interrupt-parent  : optional, if needed for interrupt mapping
 
-
 - DMA channel nodes:
         - compatible        : compatible list, contains 2 entries, first is
-			 "fsl,CHIP-dma-channel", where CHIP is the processor
-			 (mpc8349, mpc8350, etc.) and the second is
-			 "fsl,elo-dma-channel". However, see note below.
+                              "fsl,CHIP-dma-channel", where CHIP is the processor
+                              and the second is "fsl,elo-dma-channel".
+                              However, see note below.
         - reg               : <registers mapping for channel>
         - cell-index        : dma channel index starts at 0.
 
 Optional properties:
         - interrupts        : <interrupt mapping for DMA channel IRQ>
-			  (on 83xx this is expected to be identical to
-			   the interrupts property of the parent node)
+                              (on 83xx this is expected to be identical to
+                              the interrupts property of the parent node)
         - interrupt-parent  : optional, if needed for interrupt mapping
 
 Example:
@@ -70,27 +70,31 @@ Example:
 		};
 	};
 
-* Freescale 85xx/86xx DMA Controller
-
-Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
+** Freescale ELOPLUS DMA Controller
+   This is DMA controller with extended addresses and chaining.
+   Used in Freescale PowerPC 85xx/86xx and pxxx series chips, such as:
+   [1] mpc8540, mpc8541, mpc8555, mpc8560, mpc8610, mpc8641,
+   [2] mpc8536, mpc8544, mpc8548, mpc8568, mpc8569, mpc8572, p1010, p1020, p1021,
+       p1022, p1023, p2020, p2041, p3041, p4080, p5020, p5040, and also bsc9131.
 
 Required properties:
 
-- compatible        : compatible list, contains 2 entries, first is
-		 "fsl,CHIP-dma", where CHIP is the processor
-		 (mpc8540, mpc8540, etc.) and the second is
-		 "fsl,eloplus-dma"
+- compatible        : compatible list, contains 2 entries for chips in above
+                      list[1], the first is "fsl,CHIP-dma", where CHIP is the
+                      processor and the second is "fsl,eloplus-dma". contains
+                      only one "fsl,eloplus-dma" for chips in above list[2]
 - reg               : <registers mapping for DMA general status reg>
 - cell-index        : controller index.  0 for controller @ 0x21000,
                                          1 for controller @ 0xc000
-- ranges		: Should be defined as specified in 1) to describe the
-		  DMA controller channels.
+- ranges            : physical address range of DMA controller channels
 
 - DMA channel nodes:
-        - compatible        : compatible list, contains 2 entries, first is
-			 "fsl,CHIP-dma-channel", where CHIP is the processor
-			 (mpc8540, mpc8560, etc.) and the second is
-			 "fsl,eloplus-dma-channel". However, see note below.
+        - compatible        : compatible list, contains 2 entries for chips in
+                              above list[1], the first is "fsl,CHIP-dma-channel",
+                              where CHIP is the processor and the second is
+                              "fsl,eloplus-dma-channel". contains only one
+                              "fsl,eloplus-dma-channel" for chips in above list[2]
+                              However, see note below.
         - cell-index        : dma channel index starts at 0.
         - reg               : <registers mapping for channel>
         - interrupts        : <interrupt mapping for DMA channel IRQ>
-- 
1.7.9.5



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