Date: Wed, 24 Jul 2013 23:23:08 +0200
From: Daniel Vetter <daniel@ffwll.ch>
To: Keith Packard <keithp@keithp.com>
Cc: Daniel Vetter <daniel@ffwll.ch>, linux-kernel@vger.kernel.org,
        Dave Airlie <airlied@redhat.com>, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915: Add async page flip support for IVB
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On Wed, Jul 24, 2013 at 01:26:32PM -0700, Keith Packard wrote:
> Daniel Vetter <daniel@ffwll.ch> writes:
> 
> > Matching tiling modes is actually already a requirement on gen4+ (since
> > the tiling bit and the linear/tiled offset registers can't be changed with
> > a MI_DISPLAY_FLIP command).
> 
> Async flip has a harder requirement -- you must use X tiling, both
> before and after the flip. Oh, and async flips require a 32KB aligned
> buffer, which I'm not actually checking for. Not sure how to

We could just unconditionally increase the alignement in
intel_pin_and_fence_fb_obj - we already have more strict requirements due
to a bunch of w/a in other places. So shouldn't hurt at all really.

> > But atm we fail to check that in the common
> > code, so imo better to move that to there.
> >
> > We already check for matching strides in common code, so with the tile
> > check added we could drop this all here.
> 
> I don't see a requirement for matching stride and tile parameter in the
> MI_DISPLAY_FLIP docs for synchronous operations, at least on DevGT+. Is
> the common code too restrictive?

Hm right, I've mixed that. I guess we could be a bit more sloppy with
this, otoh no one yet seems to want it and Ville's pageflip stuff is
rather madly flexible.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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